KR20080041479A - Data erase scheme of nand type flash memory device - Google Patents

Abstract

A method for erasing data of a NAND flash memory device is provided to improve the operation reliability of the device by omitting a pre-program influencing program-worst influence in a reliability experiment of program/erase cycling. According to a method for erasing data of a NAND flash memory device including a plurality of memory cells programmed with data as being connected to N word lines, data of the programmed memory cell is erased. Post-program is performed sequentially by applying a program bias to each word line for the memory cell(290). The post-program step includes a step of programming one word line and a step of verifying the memory cell connected to the programmed word line repetitively.

Description

Data erase scheme of NAND type flash memory device

1 is an equivalent circuit diagram illustrating a pre-program operation of a NAND flash memory device.

2 is a graph illustrating cell threshold voltage distribution after a pre-program operation of a NAND flash memory device.

3 is an equivalent circuit diagram illustrating a post-program operation of a NAND flash memory device.

4 is a graph illustrating threshold voltage distribution of a cell after a post-program operation of a NAND flash memory device.

5 is a flowchart illustrating a post-program method of a conventional NAND flash memory device.

6 is an equivalent circuit diagram illustrating a data erase method of a NAND flash memory device according to the present invention.

7 is a flowchart illustrating a post-program process in a data erasing method of a NAND flash memory device according to the present invention.

8 is a graph illustrating a distribution of cell threshold voltages after a post-program process is performed in a data erase method of a NAND flash memory device according to the present invention.

FIG. 9 is a graph illustrating a distribution of cell threshold voltages after post-program in a multi-level cell (MLC) of 2 bits or more.

The present invention relates to a data erasing method of a flash memory device, and more particularly, to a data erasing method of a NAND flash memory device suitable for a multilevel cell structure.

NAND flash memory devices are nonvolatile memory devices that can be electrically programmed and erased. They are MP3 players, digital cameras, camcorders, notebook computers, PDAs, and cellular phones. It is widely used in portable electronics, computer bios, printers, USB drives, and the like.

Currently, the use of NAND flash memory devices as a data storage medium continues to increase, and thus a large capacity flash memory device is required. In order to increase the storage capacity at a smaller chip size, a multi-level cell (MLC) structure has been proposed to selectively store two or more bits of data in one memory cell. MLC is an effective way to increase data storage capacity without major changes in manufacturing technology. That is, unlike a single level cell (SLC) structure, the MLC has one program cell threshold voltage distribution and may represent two bits, three bits, and four or more bits of data.

1 is an equivalent circuit diagram illustrating a pre-program operation of a NAND flash memory device, and FIG. 2 is a graph showing a threshold voltage distribution of a cell after the pre-program operation. 3 is an equivalent circuit diagram illustrating a post-program operation of a NAND flash memory device, and FIG. 4 is a graph showing a threshold voltage distribution of a cell after a post-program operation.

Referring to FIG. 1, an even bit line BLe and an odd bit line BLO are connected to one page buffer one by one. The memory cell array is composed of a plurality of cell strings connected to corresponding bit lines BLe and BLo. Each cell string consists of a string select transistor, memory cells, and a drain select transistor. Memory cells are connected in series between the string select transistor and the drain select transistor. The number of memory cells included in one string may vary depending on the storage capacity of 32 or memory devices as shown. Gates of the string select transistors are commonly connected to the string select line SSL. Gates of the drain select transistors of the cell strings are connected to the drain select line DSL. Word lines are connected to each of the control gates of the memory cells.

The method commonly used for data erasing of the NAND flash memory device having such a structure proceeds in the order of pre-program-erase-post-program. The pre-program is verified by applying a pulse of program bias (Vpgm, e.g. 20V) to all word lines of a block, as shown in FIG. Without step), as shown in FIG. 2, various program states such as PV1, PV2, PV3, and the like are raised to approximately PV3 level. This pre-programming process is performed to prevent over erase that may occur during the erasing process.

However, when the pre-program is performed every erase operation, it becomes a program-worst form in the reliability experiment of program / erase cycling. In addition, the post-program proceeding after applying an erase voltage (for example, 20 V) of one pulse is a soft-program process performed before creating various program states. In this case, as shown in FIG. 3, a page by page program method and a bit by bit verification process used in an Incremental Step Pulse Program (ISPP) method are not used. A program bias is applied to all word lines at the same time, for example, a 17V start bias (Vstart) and a 0.2V step bias (Vstep) are programmed to a desired verification level (for example, 0.3V).

5 is a flowchart for explaining a conventional post-program operation.

When the post-program is started (step 110), a program bias (Vpgm) of one pulse is applied to all word lines (step 120). The threshold voltage is scanned for all cells to which the program bias is applied (step 130), and it is determined whether there is a cell that has passed the verification level Vf (step 140). If any cell has passed the verification level Vt, the post-program is completed as it is (step 160). If none of the cells have passed the verification level, the program bias is increased by a step bias (Vstep) and applied to all word lines (step 150).

As described above, the conventional post-program method is a method of soft programming all cells simultaneously with a wide cell threshold voltage (Vt) distribution after performing an erase operation. Therefore, a program speed among all cells of one block is high. If at least one cell is present, the rest of the cell is terminated regardless of the program state. Therefore, after a normal program, a lot of interference is caused by a cell having various program states, and when an MLC is changed from 2 bits to 3 bits or 4 bits, The effect of the erase method is even greater.

The technical problem to be achieved by the present invention is to improve the operation reliability of the device by eliminating the pre-program that has a program-warped effect in the reliability experiment of program / erase cycling, and to apply the same program vias to all word lines during post-program The present invention provides a data erasing method of a NAND flash memory device capable of narrowing the distribution of a cell threshold voltage after a post-program by performing a program and a verify operation one word line without an application.

In order to achieve the above technical problem, a data erasing method of a NAND flash memory device according to the present invention includes a NAND type memory cell including a plurality of memory cells connected to each of N (N is a natural number) word lines and programmed with predetermined data. A data erasing method of a flash memory device, comprising: erasing data of the programmed memory cell; And sequentially performing post-program by applying a program bias to each of the memory cells by one word line.

In the performing of the post-program, the programming of one word line and the verification of a memory cell connected to the programmed word line are repeatedly performed.

The performing of the post-program may include: programming one word line with a predetermined program bias Vstart, and comparing a threshold voltage of a memory cell connected to the programmed word line with a reference level Vf. Determining whether the programmed word line is an N-th word line corresponding to the last word line if there is a cell that has passed the reference level as a result of the comparison; And if the programmed word line is an N-th word line, completing the post-program.

If the threshold voltage of the memory cell connected to the programmed word line does not pass the reference level Vf, the program bias may be increased by a step bias Vstep and then applied again to program.

If the programmed word line is not the N-th word line, the step of programming, comparing with a reference level, and determining whether the N-th word line is performed until the word line number is increased by one to become the N-th word line is performed. can do.

The reference level Vf for verifying the programmed memory cell has a positive value.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. However, embodiments of the present invention may be modified in many different forms, and the scope of the present invention should not be construed as being limited by the embodiments described below.

In a conventional MLC structure, the actual program / erase operation proceeds in a normal program-pre-program-erase-post-program manner. This approach deteriorates the tunnel oxide due to the continuous application of high program voltages, indicating a weak problem in program / erase cycling reliability tests. In the present invention, by eliminating the pre-program process in the data erase method of the MLC structure, it is intended to improve the reliability of the device. In addition, the wide threshold voltage distribution of the erase cells generated at this time can be reduced by using a modified post-program method.

The conventional post-program approach is to soft program to the desired verify level by applying program bias to all word lines. This method is a method of soft programming all cells at the same time in the state of having wide cell threshold voltage after erasing. Therefore, the verification operation is performed irrespective of the program state of the remaining cells by one cell having a high program speed among all the cells of one block. Since this is completed, it still has a wide cell threshold voltage distribution. According to the present invention, the cell threshold voltage distribution can be narrowed by performing the post-program by one word line and performing the verify operation. In this case, after performing various normal programs, interference by cells with various program states can be reduced, and even if MLC is changed from 2 bits to 3 bits or 4 bits, the conventional erase method is used. Effective. The data erasing method of the present invention will be described in more detail with reference to the drawings.

6 is an equivalent circuit diagram illustrating a data erasing method of a NAND flash memory device according to the present invention, and FIG. 7 illustrates a post-program process in a data erasing method of the NAND flash memory device according to the present invention. 8 is a graph illustrating a distribution of cell threshold voltages after a post-program process in the data erasing method of the present invention.

Referring to FIG. 6, an even bit line BLe and an odd bit line BLO are connected to one page buffer one by one. The memory cell array is composed of a plurality of cell strings connected to corresponding bit lines BLe and BLo. Each cell string consists of a string select transistor, memory cells, and a drain select transistor. Memory cells are connected in series between the string select transistor and the drain select transistor. The number of memory cells included in one string may vary depending on the storage capacity of 32 or memory devices as shown. Gates of the string select transistors are commonly connected to the string select line SSL. Gates of the drain select transistors of the cell strings are connected to the drain select line DSL. Word lines are connected to each of the control gates of the memory cells.

The data erase process of the present invention skips the pre-program and proceeds to erase-post-program. Since the erase operation is performed in the same manner as the general method, a description thereof will be omitted and the post-program process will be described in detail.

6 and 7, when the post-program process is started (step 210), a program voltage is applied to the first word line (steps 220 and 230). Unlike the conventional post-program method, in which a program bias of one pulse is applied to one entire block, the present invention performs the post-program in word lines. That is, one program bias is applied to one word line. At this time, since the even bit line BLe and the odd bit line BLO are connected to one page buffer one by one, the even and odd pages are alternately programmed in programming. That is, the program bias is sequentially applied from the even page of the first word line WL0 to the odd page of the last word line WL31.

After programming by applying a program bias to one word line, the threshold voltage of the cell connected to the programmed word line is scanned (step 240), and the verify level is compared with the threshold voltage of the cell connected to the programmed word line. It is determined whether there is a cell that has passed (step 250). As a result, if there is a cell that has passed the verification level in the programmed word line, proceed to the next step. Vstep) is applied to the word line again (step 260).

If there is a cell that has passed the verification level in the programmed word line, it is determined whether the word line is the last word line WL31 (step 270), and if it has been programmed up to the last word line WL31, the post-program operation is completed ( Step 290). If there is a cell that passes the verification level in the programmed word line, but the word line is not the last word line WL31, the program process is performed on the next word line (step 280).

8 is a graph showing the distribution of cell threshold voltages after a post-program process in the data erasing method of the NAND flash memory device of the present invention. Compared with the graph showing the cell threshold voltage distribution after the conventional post-program of FIG. 4, it can be seen that the cell threshold voltage distribution width is reduced compared with the conventional art. This is because, unlike the conventional method in which the post-program is performed in the entire block unit, the present invention performs the post-program in the word line unit. That is, since post-programming is performed by two-page program-verification-two-page program-verification, interference by cells having various program states can be reduced.

The data erasing method of the present invention is further used when the program state is used not only for the most basic 2-bit MLC having two data but also for 3-bit, 4-bit or more MLC structure that can increase data storage capacity. effective.

FIG. 9 is a graph illustrating a distribution of cell threshold voltages after post-program in a multi-level cell (MLC) of 2 bits or more. As shown, interference by cells with various program states can be reduced.

According to the data erasing method of the NAND type flash memory device having the multi-level cell structure according to the present invention, the pre-program process performed in the data erasing process is omitted, thereby preventing the deterioration of the reliability of device operation due to deterioration of the tunnel oxide film. can do. In addition, by performing the post-program process in units of word lines, interference by cells having various program states can be reduced, thereby reducing the cell threshold voltage distribution width. The data erasing method of the present invention can be effectively applied not only to 2-bit MLC whose program state has two data but also to 3-bit, 4-bit or more MLC structure that can increase data storage capacity. have.

Although the present invention has been described in detail with reference to preferred embodiments, the present invention is not limited to the above embodiments, and various modifications may be made by those skilled in the art within the technical spirit of the present invention. Do.

Claims (7)

A data erasing method of a NAND flash memory device comprising a plurality of memory cells connected to each of N (N is a natural number) word lines and programmed with predetermined data, Erasing data of the programmed memory cells; And And sequentially performing a post-program by applying a program bias to each of the memory cells by one word line. The method of claim 1, wherein performing the post-program comprises: A method of erasing data of a NAND flash memory device, characterized by repeatedly performing a step of programming one word line and verifying a memory cell connected to the programmed word line. The method of claim 2, wherein performing the post-program comprises: Programming with a predetermined program bias (Vstart) for one word line, Comparing the threshold voltage of the memory cell connected to the programmed word line with a reference level Vf; Determining whether the programmed word line is the N-th word line corresponding to the last word line if there is a cell that has passed the reference level as a result of the comparison; And And if the programmed word line is an N-th word line, completing a post-program. The method of claim 3, If the threshold voltage of at least one of the memory cells connected to the programmed word line does not pass the reference level Vf, the program bias is increased by a step bias Vstep, and the program voltage is applied again to perform programming. And a data erasing method for a NAND flash memory device. The method of claim 3, If the programmed word line is not the N-th word line, increasing the word line number by one until the N-word word line is programmed, comparing with a reference level, and determining whether it is an N-th word line. And a data erasing method for a NAND flash memory device. The method of claim 2, And a reference level (Vf) for verifying the programmed memory cell has a positive value. The method of claim 3, The initial program bias (Vstart) is 16V, and the step bias (Vstep) is 0.2V data erasing method of the flash memory device.

Images