KR20080062720A - Method of programming nand flash memory device - Google Patents

Abstract

A method of programming a NAND flash memory device is provided to suppress the generation of over-program by performing program by decreasing a start voltage during re-program operation after a block address is stored when over-program is generated. Program is performed by applying a first program voltage to a block including a cell to be programmed(520). Generation of over-program is judged by performing read operation for the block to perform the program(560). The program is repeated by applying a second program voltage lower than the first program voltage to a block with over-program, and a start voltage is maintained for a block without over-program. The first and the second program voltage are applied through ISPP(Incremental Step Pulse Program) method.

Description

Program method of NAND flash memory device {Method of programming NAND flash memory device}

FIG. 1 is a diagram illustrating a relationship between word line voltages, read voltages, and cell voltage distributions of erased and programmed cells of a NAND flash memory device.

FIG. 2 is a diagram illustrating a method of programming a NAND flash memory device using an incremental step pulse program (ISPP).

3 is a diagram illustrating an over-program problem of a NAND flash memory device.

4 is a diagram illustrating a cell array structure of a NAND flash memory device.

5 is a flowchart illustrating a program method of a NAND flash memory device according to the present invention.

6 to 8 illustrate incremental step pulse program (ISPP) pulses applied to a method of programming a NAND flash memory device according to the present invention.

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to memory devices, and more particularly, to a method of programming a NAND flash memory device such that over-program is suppressed.

Flash memory devices are widely used in many electronic applications in which nonvolatile memory devices are employed. Generally, flash memory devices use one transistor cell, which provides high memory density, high reliability, and low power consumption. Generally, flash memory devices are used in portable computers, personal digital assistants (PDAs), digital cameras, portable telephones, and the like. In addition, program code, system data such as basic input / output systems (BIOS), and other firmware may also be stored in flash memory devices. Among flash memory devices, especially NAND flash memory devices have been recently used in a wider range in that high memory density can be obtained at relatively low cost.

FIG. 1 shows the relationship between the word line voltage Vword, the read voltage Vread, and the cell voltage distribution Vth of the erased and programmed cells of the NAND flash memory device. As shown in FIG. 1, the erased cell has a negative cell voltage distribution Vth, and the programmed cell has a positive cell voltage distribution Vth. As the word line voltage Vword is applied to the control gate, the erased cell turns on and becomes on-cell and the programmed cell turns off and becomes off-cell.

Typically, the cell voltage distribution Vth is controlled by an incremental step pulse program (ISP). 2 shows the pulses at the ISPP. As shown in Fig. 2, a starting voltage, for example, a voltage of 15V is used during the first program period. And finally use a step pulse, for example a voltage increased by 0.5V, for each subsequent program period until the final voltage, for example 19V, is reached. Although not shown in the figure, program verification is performed by applying a constant voltage, for example, a voltage of 1.2V, in the verify period between program periods.

3 is a diagram illustrating an over-program problem of a NAND flash memory device. As shown in FIG. 3, when the cell threshold voltage Vth is greater than the read voltage Vread, the normal read operation in the NAND cell string may not be performed properly. There may be various causes of such an over-program, but as an example, there is a fast cell in which the threshold voltage increases relatively faster than other cells even when the same program voltage is applied.

SUMMARY OF THE INVENTION The present invention has been made in an effort to provide a method for programming a NAND flash memory device in which over-program generation is suppressed.

In order to achieve the above technical problem, a program method of a NAND flash memory device according to the present invention includes: performing a program by applying a first program voltage to a block including a cell to be programmed; Determining whether an over-program occurs by performing a read operation on a block on which the program is performed; And performing the program again by applying a second program voltage lower than the first program voltage to the block on which the over-program has occurred, and maintaining a start voltage on a block on which the over-program has not occurred. do.

The first and second program voltages may be applied in an incremental step pulse program (ISPP) scheme.

The method may further include storing a block address of a block in which the over-program has occurred.

The block address may be stored in a spare cell or a spare block.

The second program voltage may be reduced by 0.25V relative to the first program voltage.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. However, embodiments of the present invention may be modified in many different forms, and the scope of the present invention should not be construed as being limited by the embodiments described below.

4 illustrates an example of a cell array structure of a NAND flash memory device. As shown in FIG. 4, the cell array includes a first cell string 410 and a second cell string 420. Although only two cell strings are shown in the figures, this is for illustrative simplicity and includes substantially more cell strings. In some cases, a cell string may be referred to as a NAND string. The first cell string 410 is disposed between the first bit line BL1 and the common source line CSL. The second cell string 420 is disposed between the second bit line BL2 and the common source line CSL. The first bit line 410 is connected to the first page buffer PB1 430. The second bit line 420 is connected to the second page buffer PB2 440. The first cell string 410 and the second cell string 420 have the same structure. The string select transistors 411/421 and the plurality of cell transistors 413/423 connected in series to a common drain / source region. And source select transistors 412/422. The gate of the string select transistor 411/421 is connected to the drain select line DSL, the gate of the cell transistor 413/423 is connected to the word line WL, and the source select transistor 412/422 of the source select transistor 412/422. The gate is connected to the source select line SSL. Although not shown, in the case where the bit line is divided into an even bit line and an odd bit line for the application of the bit line shielding technique, the cell transistors 413/423 are divided into the even bit line and the odd bit line. Alternately arranges bit lines and connects even bit lines and odd bit lines to one page buffer.

Programs and reads of NAND flash memory devices having such cell arrays are generally made in page units, and erase is generally made in blocks. Typically, one block is composed of 32 pages or 64 pages, but may be composed of more pages as the density increases. As the program is programmed in units of pages, the cell transistors belonging to the fast cell among the cell transistors belonging to the same page may be over-programmed because the threshold voltage increases greatly by the start voltage of the ISPP. Therefore, in this embodiment, the ISPP program is performed using a low start voltage for a block including a cell transistor that is fast-existed and over-programmed.

5 illustrates a program method of such a NAND flash memory device. 6 to 8 also show ISPP pulses. Referring to FIG. 5, an erase operation is first performed (step 510). The erase operation is performed in blocks. Next, a program operation using an ISPP is performed (step 520). That is, as shown in FIG. 6, a starting voltage of 16 V is applied to the selected word line as the program voltage Vpgm, while a voltage of 10 V is applied as the pass voltage Vpass to the unselected word lines. A program check is then performed (step 530). As a result of the program check, it is determined whether the program check is passed (step 540). If the program check is not passed in this judgment, the program of step 520 is executed again by setting the program voltage Vpgm to 16.5V plus the 0.5V step pulse? V.

If the program check passes as a result of the determination, a block unit read is performed (step 550). It is determined whether an over-program has occurred in a cell in the read result block (step 560). This determination is determined by whether there is a cell that is turned off by applying the read voltage Vread to the word line. If there is no cell to be off, the over-program does not occur, whereas if there is a cell to be off, it is the case that over-program has occurred. If the over-program occurs in this determination, i.e., if a fast cell exists, the block address is stored (step 570). The block address is stored in an extra spare cell or spare block. The starting voltage is then reduced from 16V to 0.25V less by 15.75V (step 580). After erasing in units of blocks in step 510, the program operation is performed using 15.75V as a start voltage as shown in FIG. 7 (step 520). Specifically, a start voltage of 15.75 V is applied to the selected word line as the program voltage Vpgm, while a voltage of 10 V is applied as the pass voltage Vpass to the unselected word lines. A program check is then performed (step 530). As a result of the program check, it is determined whether the program check is passed (step 540). If the program check is not passed in this determination, the program of step 520 is executed again with 16.25V plus 0.5V step pulse? V as the program voltage Vpgm. In the case where the program check is passed as a result of the determination, a read is performed in block units of step 550, and then it is determined whether an over-program occurs in step 560.

When the over-program occurs in the determination, i.e., when the fast cell exists, the block address is stored (step 570). The starting voltage is then reduced from 15.75V to 15.50V less 0.25V (step 580). After erasing in units of blocks in step 510, a program operation is performed with 15.50V as a start voltage as shown in FIG. 8 (step 520). Specifically, a start voltage of 15.50 V is applied to the selected word line as the program voltage Vpgm, while a voltage of 10 V is applied as the pass voltage Vpass to the unselected word lines. A program check is then performed (step 530). As a result of the program check, it is determined whether the program check is passed (step 540). If the program check is not passed in this judgment, the program of step 520 is executed again with 16.00V plus 0.5V step pulse? V as the program voltage Vpgm. In the case where the program check is passed as a result of the determination, a read is performed in block units of step 550, and then it is determined whether an over-program occurs in step 560.

This process is performed repeatedly until no over-program occurs. If the over-program does not occur, it means that the fast cell does not have a threshold voltage greater than the read voltage Vread by the program operation with the reduced start voltage even if the fast cell exists, and thus the over-program Occurrence of an inappropriate read operation is suppressed.

As described above, according to the program method of the NAND flash memory device according to the present invention, after performing a program, a block unit read is performed to determine whether an over-program occurs, and when an over-program occurs, a block address is determined. When saving and reprogramming after saving, the advantage is that the occurrence of over-programming can be suppressed by reducing the starting voltage to perform the program.

Although the present invention has been described in detail with reference to preferred embodiments, the present invention is not limited to the above embodiments, and various modifications may be made by those skilled in the art within the technical spirit of the present invention. Do.

Claims (5)

Performing a program by applying a first program voltage to a block including a cell to be programmed; Determining whether an over-program occurs by performing a read operation on a block on which the program is performed; And Performing the program again by applying a second program voltage lower than the first program voltage to the block on which the over-program has occurred, and maintaining a start voltage on a block on which the over-program has not occurred; Program method of NAND flash memory device. The method of claim 1, And programming the first and second program voltages by an incremental step pulse program (ISPP) method. The method of claim 1, And storing a block address of a block in which the over-program has occurred. The method of claim 3, And the block address is stored in a spare cell or a spare block. The method of claim 1, And the second program voltage decreases by 0.25V relative to the first program voltage.

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