KR20080040698A - Methods of channel coding for communication systems - Google Patents

Abstract

A method of encoding data for transmission to one or more users selects a given number of bits of data from a transport block to be subject to hybrid ARQ functionality for channel coding. Only the selected bits are channel coded in a HARQ block for subsequent transmission using a given set of channelization codes to one or more users.

Description

Data encoding method and data bit determination method {METHODS OF CHANNEL CODING FOR COMMUNICATION SYSTEMS}

The present invention relates generally to channel coding for wireless communication systems.

Wideband Code Division Multiple Access (WCDMA), also known as Universal Mobile Telecommunications System (UMTS), is a technology for broadband digital wireless communications in applications that require the Internet, multimedia, video, and other capacities. WCDMA uses a spectrum with 5MHZ carriers to provide 50 times higher data rates than current Global System for Mobile Communication (GSM) networks and 10 times higher data than conventional packet radio service (GPRS) networks. Provide rate. WCDMA is one technology for 3G telecom systems that provides higher capacity and higher data rates for voice and data.

High Speed Downlink Packet Access (HSDPA) is a packet-based data service in W-CDMA downlink with data transmissions currently reaching 8-10 Mbps (and 14.4 Mbps in current MIMO systems) in the 5 MHz bandwidth of the WCDMA downlink. to be. HSDPA implementations include Adaptive Modulation and Coding (AMC), Hybrid Automatic Request (HARQ), and advanced receiver design.

HSDPA consists of a forward link data channel called High-Speed Downlink Shared Channel (HS-DSCH). This is based on shared channel transmissions, that is, some channelization codes and transmission powers in a given cell are treated as shared resources that are dynamically shared between users in time and code domains. Shared channel transmission results in more efficient use of available code and power resources.

Shared channel transmission currently leads to more efficient use of available code and power resources compared to dedicated channel use in WCDMA. The shared code resource to which the HS-DSCH is mapped may consist of up to 15 codes. The actual number employed depends on the number of codes supported by the terminal / system, operator settings, desired system capacity, and the like. The spreading factor (SF) is fixed at 16 and the sub-frame length (Transmission Time Interval (TTI) is only 2 ms. The modulation schemes used are Quadrature Phase Shift Keying (QPSK) and 16-QAM.

For HSDPA, fast link adaptation is accomplished using adaptive modulation and coding based on channel quality indicator (CQI) feedback instead of power control as in WCDMA. By link adaptation for both near users (high coding rate) and far users (low coding rate), the highest possible data rate on a given link is guaranteed. While connected, the HSDPA user equipment (UE) periodically sends a CQI to the base station (BS) indicating the data rate, the coding and modulation scheme to be used, and the number of multiple codes that the UE can support under current radio conditions. The CQI also contains information about the power level to be used.

Fast retransmission is achieved using hybrid ARQ with incremental redundancy or chase combining. For 16-QAM modulation, the retransmitted packet also uses a different Gray coded constellation based on bit reliability using Log Likelihood Ratio (LLR). This modulation rearrangement improves turbo decoding performance by averaging the bit reliability of QAM arrays to alphabetical sizes greater than four. In order for the BS to know when to start retransmission, the UE also sends an ACK / NACK for each packet.

For HSDPA services, fast scheduling occurs at the BS, not at the Radio Network Controller (RNC), as in WCDMA. This is done based on information regarding channel quality, terminal performance, and quality of service (QoS) classes and power / code availability. Opportunistic scheduling sensitive to this channel achieves multi-user diversity by preferentially transmitting to users with better channel conditions.

In the 3rd Generation Partnership Project (3GPP) standard, the Release 5 specification focuses on HSDPA, which provides data rates up to about 10 Mbps to support packet-based multimedia services. Release 6 and beyond focus on MIMO systems that are being developed to support higher data transmission rates up to 14.4 Mbps. HSDPA has evolved to be backward compatible from Release 99 WCDMA systems.

Communications networks and systems adapted for HSDPA services are required to support transmission in up to 15 16-Orthogonal Amplitude Modulation (QAM) channelization codes to multiple users and / or single users. In a conventional example, each channel element (here, understood as a given baseband processor capable of processing and transmitting digital bits of information over an air interface) may support four 16-QAM codes. Therefore, to support (e.g.) twelve 16-QAM codes, a baseband processor must be used that can process and transmit digital bits of information through three channel elements (CE), e.g., air interfaces. Each CE transmits four 16-QAM codes.

Typically, in order to transmit data to a single user using all 12 QAM channelization codes, the channel encoding of a given transmission time interval (TTI) transport channel block of the HS-DSCH, or "TTI block", is single up to physical channel segmentation. In CE, the data can then be split between multiple physical channels (PhCh). After physical channel segmentation, data may be sent to multiple CEs to wirelessly transmit data using the corresponding 12 16-QAM transmitters.

There are at least two potential drawbacks to the conventional approach. First, most channel encoding is done in a single CE, and then data is typically delivered to multiple CEs using a high speed serial bus, so that channel encoding of the TTI block can cause long latency. Next, the use of a high speed CE-to-serial bus is required, which can add to system cost and complexity.

Exemplary embodiments of the invention relate to a method of encoding data for transmission to one or more users. In an example method, a given number of data bits may be selected from a transport block to be delivered to hybrid ARQ functionality for channel coding, wherein the bits selected in the HARQ block for transmission to one or more users using a given channelization code set may be selected. Can be channel coded.

Another exemplary embodiment of the present invention is directed to a method of distributing channel coding for a transport block received by a plurality of channel elements for transmission to one or more users. The method may include separating, at each given channel element, a transport block coded with system bits, parity one bits and parity one bits. For hybrid ARQ processing, a given smaller number of systems, parity ones and parity to bits may be selected to channel encode the bits for subsequent transmission by a given channel element to one or more users.

Another exemplary embodiment of the present invention is directed to a method of determining data bits to be passed to a rate matching function within a channel element for encoding the bits prior to transmission by the channel element to one or more users. The method may include separating the transmission block received by the channel element into a full set of system bits, parity one bit and parity to bit. A given number of systems, parity ones and parity two bits, smaller than the entire set, may be selected to go through the rate matching function in the HARQ block of the channel element for channel coding. Only bits selected for transmission using a given set of channelization codes to one or more users are entered in the HARQ block.

Another exemplary embodiment of the present invention is directed to a method of determining which bits of a received transport block will pass through a rate matching function implemented within the channel element to channel code the bit for transmission by the channel element. The method includes determining, based on the set of bits to be output of the second rate matching end, bits that are to be input and not punctured at the first rate matching end of the two-speed rate matching function.

Another exemplary embodiment of the present invention is directed to a method of determining which bits in a received transport block are not to be punctured and transmitted to a rate matching function to channel code the bits for transmission by a channel element. The method includes determining a bit to be input to a first rate matching stage of an N-stage (N> 2) rate matching function implemented in a HARQ block of the channel element based on output bits from a subsequent rate matching stage. .

Exemplary embodiments of the present invention will be more fully understood from the following detailed description taken in conjunction with the accompanying drawings, in which like elements are designated by like reference numerals, and these are given by way of example only; It is not intended to limit the exemplary embodiment of the.

BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is a block diagram illustrating input data flow from a base station scheduler to a plurality of channel elements in order to explain a channel coding method according to an exemplary embodiment of the present invention.

2 is a block diagram illustrating HS-DSCH hybrid ARQ functionality.

3 is a block diagram illustrating a two stage rate matching algorithm, in accordance with an exemplary embodiment of the present invention.

4 is a diagram of passing and puncturing any bits of a received transport block based on HARQ functionality implemented to channel code the bits for transmission by a channel element to a given user, in accordance with one exemplary embodiment of the present invention. Process flow diagram illustrating how to decide whether or not to punch.

The following description is directed to a communication network or system based on one or more CDMA (IS95, cdma000, and various technology variants), WCDMA / UMTS, and / or related technology, which will be described in the context of the present example, but is illustrated and described herein. It should be noted that the embodiments are exemplary only and are not limitative in any way. As such, various modifications will be apparent to those skilled in the art for application to a communication system or network based on techniques that may be substituted for or used with the network or system at various stages of development in addition to those described above.

Here, the term user may be synonymous with a mobile station, mobile user, user equipment (UE), user, subscriber, wireless terminal and / or remote station, to refer to a remote user of a radio resource in a wireless communication network. Can be. The term 'cell' may be understood as a base station (also referred to as node B), an access point, and / or the end of any radio frequency communication. Channel elements may be understood as baseband processors capable of processing and transmitting digital bits of information over an air interface.

In general, exemplary embodiments of the present invention provide a method of data encoding for transmission to one or more users, and / or a method of distributing channel coding for transport blocks between multiple channel elements for transmission to one or more users, and / or one. A method for determining data bits to be HARQ encoded in a given channel element for transmission to a user above. Each example methodology may support transmitting data to a single user or multiple users using at least 12 16-QAM codes. The example methodology described below does not require the use of a high speed serial bus and can achieve low latency compared to conventional channel coding methodologies.

In one aspect of the invention, the exemplary methodology may be extended to enable the transmission of data using up to 15 16-QAM codes. In this case, four CEs may be used for transmission of the HS-DSCH channel, where three CEs are configured to transmit using four channelization codes and the fourth CE uses three channelization codes to transmit data. Can be sent.

1 is a block diagram illustrating an input data flow from a base station scheduler to a plurality of channel elements in order to explain a channel coding method according to an exemplary embodiment of the present invention. In the example as shown in FIG. 1, three channel elements CE may be assigned to the HS-DSCH. Each CE can transmit data using four 16-QAM transmitters. In this example, the Node B scheduler is configured to send a single HS-DSCH transport block (“block”) to a single user using twelve 16-QAM codes.

In FIG. 1 a power PC is shown, which is a processor in Node B that is responsible for generating HS-DSCH transport blocks for all CEs. For the received transport block, each CE calculates a cyclic redundancy check (CRC) attachment and performs bit scrambling and turbo encoding (also code block segmentation and code block concatenation) for the entire block. Can be done. 3GPP TS 25.121 Version 6.4.0 Release 6 (2005-03), Section 4.2 to Section 4.2, entitled "Coding for HS-DSCH," within the 3GPP Technical Manual UMTS Channel Coding and Multiplexing (FDD). As described with reference to the various parts of "General coding and Multiplexing of TrChs", CRC attachment, bit mixing, turbo encoding, code block segmentation and concatenation in the 3GPP standard are well known and It is explained. Therefore, detailed descriptions of these known processes are omitted for simplicity.

On the other hand, as described below in connection with the exemplary embodiment, starting with the HARQ processing functionality (“HARQ block”) for the input bits of the block received from the turbo encoder, it may be transmitted by each given CE. Only bits will be encoded. In the exemplary methodology described below, the number of system bits, parity one bits, and parity to bits at the input of the HARQ block, which will fill a given column in the bit collection matrix of the HARQ block, is actually the HARQ block. It may be determined prior to entering the HARQ process in. These bits are transmitted using the 16-QAM channelization code. Therefore, only these bits need to pass through the HARQ block. The remaining bits from the turbo encoder are ignored in this channel element.

As described in section 4.5 of 3GPP TS 25.212 version 6.4.0 Release 6, most of the Million Instructions per Second (MIPS) usage is not only in the HARQ function but also in physical channel segmentation, HS-DSCH interleaving, constellation for 16-QAM. Generated from functions such as rearrangement and physical channel mapping. Also, since turbo encoding can be performed using an ASIC accelerator, encoding does not consume any MIPS in the processor performing channel coding. This is important because it allows the power PC to transmit a complete block to each channel device, and the pre-HARQ (pre-HARQ) function is performed on the ASIC accelerator or consumes less MIPS.

For example, if the data is 2 Mbps, the channel coding function before HARQ consumes less than 8 MIPS (which includes writing data to the ASIC encoder and reading data from the ASIC encoder). The channel coding function after and after HARQ consumes about 164 MIPS. This is about 20 times the MIPS consumed by the pre HARQ channel coding function. Therefore, by performing channel encoding for the entire block before the HARQ block, the increase in MIPS can be relatively small compared to the MIPS used in HARQ and subsequent channel coding functions.

many CE  Between HARQ  Encoding Distribution

2 is a block diagram illustrating HS-DSCH hybrid ARQ functionality. 2 is shown in section 4.5.4 of TS 25.212 and is provided in the context. In general, the degree hybrid ARQ functionality is "N _data the number of bits at the output of the channel encoder (turbo encoder), shown as" N ^TTI "in Figure 2, in Figure 2, also referred to as a" HARQ block "as illustrated in Matched to the total number of bits of the fast physical downlink shared channel (HS-PDSCH) to which the HS-DSCH is mapped. Hybrid ARQ functionality can be controlled by redundant version (RV) parameters, which are used to calculate the rate matching parameters e _minus , e _plus and e _ini .

Hybrid ARQ functionality consists of two rate matching stages and one virtual buffer as shown in FIG. In general, the first rate matching stage matches the number of input bits to the virtual IR buffer, information about which is provided in the higher layer. If the number of input bits (shown as N ^TTI ) does not exceed the virtual IR buffering capacity, the first rate matching stage is transparent. The second rate matching stage matches the number of bits after the first rate matching stage with the number of available physical channel bits of the HS-PDSCH set in the TTI.

To illustrate the example methodology, the input data from the turbo encoder to the HARQ block can be represented by C ₁ , C ₂ ,... C _N , where N is the total number of bits in the input to the HARQ block. In an example, N may be a multiple of three.

As shown in Fig. 2, the HARQ bit separation function separates the input data into three streams of system bits, parity one bit and parity two bit. These bits go through the first and second stages of rate matching and finally go through a bit collection function. Table 1 defines the parameters used in the equations to illustrate the exemplary methodology according to the present invention. Table 1 should be consulted frequently for the following discussion.

HARQ bit collection can be achieved by writing data to a rectangular matrix with the following dimensions represented by equation (1):

here,

(1)

(One)

Therefore, in equation (1), N _row is the number of rows of the bit collection matrix of FIG. 2, and N _col represents the number of columns of the bit collection matrix. The system bit fills all columns of the first N _r rows and the first N _c columns of row N _r +1. The parity bits (parity one and / or parity two) fill the remaining columns of this row and all columns of the remaining rows. Filling rows and columns is described in detail in the 3GPP standard document TS25.212, so the detailed description is omitted here for simplicity.

By way of example, without losing generality, the channelization codes may be numbered consecutively starting with channelization code zero. In this example, a given channel element CE will collectively transmit channelization codes ch _s (s = start code) to ch _e (e = end code). Therefore, bits from the column N _{col , s} = 480 × ch _s +1 of the HARQ bit collection matrix and up to column N _{col , e} = 480 × ( ch _e +1) of the HARQ bit collection matrix are generated by this channel element. Can be sent.

Therefore, the HARQ function should output only these bits, and an inverse transform is performed to determine which input bits (at the input of the HARQ block) will give the desired bits at the output of the HARQ block. Therefore, HARQ functionality is only implemented for these bits. In other words, the exemplary methodology is, among the entire set or total amount of system bits, parity one bits, and / or parity two bits input from the turbo encoder, which bits are given for the final transmission from a given CE to one or more users. And determine whether to undergo HARQ functionality in the HARQ block for channel encoding (HARQ encoding).

HARQ  Determination of System Bits Through Functionality

로 표시될 수 있다. 비트

는 열 N_{col , s} 의 제 1 시스템 비트를 나타낼 수 있으며, 비트

는 열 N_{col , e} 의 마지막 시스템 비트를 나타낼 수 있다. 따라서, 비트 N_{t , sys _s} 는 이 CE 에 의해 송신될 레이트 매칭의 제 2 단 (스테이지 2) 의 출력에서의 '첫 번째' 또는 '시작' 시스템 비트이고, 다음 식 (2) 로 주어질 수 있다.In this example, the system bits at the output of the second stage of rate matching are

It may be represented as. beat

Can represent the first system bit of column N _{col , s} ,

May represent the last system bit of the column N _{col , e} . Thus, the bit N _{t , sys s} is the 'first' or 'start' system bit at the output of the second stage (stage 2) of rate matching to be transmitted by this CE, and can be given by the following equation (2): .

(2)

(2)

Bit N _{t , sys _ e} is the 'last' or 'end' system bit at the output of the second stage of rate matching to be transmitted by this CE, and can be given by the following equation (3).

(3)

(3)

If N _{t , sys s} is greater than N _{t , sys e} , no system bits are sent by this CE. Thus, the first step in determining the system bits undergoing HARQ functionality is that N _{t , sys s} and N _{t , sys _ e} at the output of the second stage of rate matching are determined from known parameters, and by this CE A threshold evaluation type that compares two bit values to determine if one system bit will be transmitted.

이고, 여기서

는 레이트 매칭의 제 2 단의 출력에서 시스템 비트

를 주는 레이트 매칭의 제 1 단의 출력에서의 시스템 비트를 나타낸다. 펑쳐링 (puncturing) 의 경우, 레이트 매칭의 제 1 단의 출력에서의 '최초' 또는 '시작' 시스템 비트이고 이 CE 에 의해 처리될 N_{sys _s} 는 식 (4) 로 표시될 수 있음을 보일 수 있다.Also in this example, the system bits at the output of the first stage of rate matching are

, Where

Is the system bit at the output of the second stage of rate matching

Denotes the system bit at the output of the first stage of rate matching. In the case of puncturing, it can be shown that N _{sys _s that} is the 'first' or 'start' system bit at the output of the first stage of rate matching and to be processed by this CE can be represented by equation (4). have.

(4)

(4)

Therefore, Equation (4) indicates that the first system bit (to be processed by CE) at the output of stage 1 is equal to the first system bit and the system bit at stage 2 at the output of the second stage of rate matching to be transmitted by the given CE. It can be determined as a function of the rate matching parameter.

The puncturing occurs when the number of bits at the output of the second rate matching stage (stage 2) is smaller than the number of bits at the input to stage 2 of the rate matching function. In this case some bits are discarded (punctured or discarded). On the other hand, iteration occurs if the number of bits at the output of the rate matching function is greater than the number of bits at the input to the rate matching function. In this case, some input bits are repeated.

In equation (4) and the following equations, the rate matching state parameters e _{minus , sys _2} and e _{plus _ sys _2} are the same across all CEs (this is e _{minus , p1 _1} , for rate matching of parity 1 and parity 2 bits). The same _{applies to} e _{minus , p1 _2} , e _{minus , p2 _1} , e _{minus , p2 _2} , e _{plus , p1 _1} , e _{plus , p1 _2} , e _{plus , p2 _1} and e _{plus, p2_2} ). The rate matching state variable e _ini in equation (4) is the state variable for the first bit to be processed by this CE. Unlike the same rate matching state parameter across all CEs, the value of e _ini may vary from CE to CE. N _sys value of the rate matching state variable e _ini in _{_ s} can be expressed by equation (5).

(5)

(5)

Hence, for puncturing, the state variable for the first bit to be processed by this CE is the rate matching state variable (e _{ini , sys _2} ) for stage 2 rate matching, the stage 2 rate matching parameter e _{minus ,} the first system bit (N _{sys _s} ) at the output of stage 1 to be processed by _{sys _2} and e _{plus , sys _2} , CE and the first system bit (N _t at the output of stage 2 rate matching to be transmitted by a given CE _{, sys _s} ).

Equation (6) describes N _{sys _ s} for the case of repetition.

(6)

(6)

For the repetition rate matching state variable, the value of e _ini in N _{sys _ s} can be given by the formula (7).

(7)

(7)

는 레이트 매칭의 제 2 단의 출력에서 시스템 비트

를 주는 레이트 매칭의 제 1 단의 출력에서의 시스템 비트를 나타낸다. 그러므로, 식 (8)은, 펑쳐링의 경우, 이 CE 에 의해 처리되는 레이트 매칭의 제 1 단의 출력에서의 '마지막' 또는 '종료' 시스템 비트인 N_{sys _e} 는 다음으로 주어짐을 보일 수 있다.As mentioned above,

Is the system bit at the output of the second stage of rate matching

Denotes the system bit at the output of the first stage of rate matching. Therefore, equation (8) can be shown that, in the case of puncturing, N _{sys _e, which} is the 'last' or 'end' system bit at the output of the first stage of rate matching processed by this CE, is given by .

(8)

(8)

Therefore, the last system bit at the output of stage 1 is the last system bit of the output of the second stage of rate matching to be transmitted by this CE, the stage 2 rate matching state variable (e _{ini , sys _2} ) for the system bit and the stage. 2 rate matching parameters e _{minus , sys _2} and e _{plus , sys _ 2} .

Equation (9) shows that for repetition, the following holds true.

(9)

(9)

The first stage of rate matching is always transparent to system bits. Therefore, it is possible to extract the system bits between N _{sys _s} and N _{sys _e} at the output of the first stage of rate matching and to perform the second stage of rate matching only on those bits. Therefore, equations 4 to 9 determine which system bits of the full set of system bits generated by the turbo encoder are to be processed and finally transmitted by this channel element. These equations also show how to determine e _ini for the first bit to be processed by this channel element, which is necessary for the rate matching algorithm.

HARQ  Determination of Parity Bits Through Functionality

이다. 본 설명에서,

는 열 N_{col , s} 의 최초 패리티 비트를 나타내고,

는 열 N_{col , e} 의 마지막 패리티 비트이다.The determination of which parity one and parity two bits will go through the HARQ functionality can be made independently of the system bit determination, for example in parallel. As given by the standard, parity bits (parity one and parity two bits) are combined (multiplexed) at the output of the second stage of rate matching, and then the bit collection is

to be. In this description,

_Represents the first parity bit in column N _{col , s} ,

Is the last parity bit in column N _{col , e} .

N _{t, p_s,} which represents the first parity bit after the collection of bits to be processed by the given CE, is given by equation (10).

(10)

10

In equation (10), and as described above, N _row is the number of _rows in the bit collection array, 2 for QPSK and 4 for 16-QAM.

N _{t , p_e} representing the last parity bit to be processed by this CE can be given by equation (11).

(11)

(11)

N _t, N _t and _{p_s,} the difference between the _{p_e} exhibits the total number of bits to be processed by this CE, N _t, N _t is greater than _{p_s, p_e} parity bits by the CE is not transmitted. If this number is negative, no bits are processed by this CE. In other words, this bit comparison after the bit collection (ie, the number of the first and last parity bits to be processed by this CE) can serve as an initial threshold decision as to whether any parity bits should be HARQ encoded or discarded.

HARQ  Selection of parity one bit to be encoded

이라고 가정하자. 열 N_{col ,s} 과 N_{col ,e} 사이에서 사용되는 최초 패리티 원 비트는

이다. 그러므로, 레이트 매칭의 제 2 단의 출력에서 패리티 원 시작 비트의 수는 식 (12) 로 주어질 수 있다.The parity one bit at the output of the second stage of rate matching

Assume that The first parity one bit used between columns N _{col , s} and N _{col , e} is

to be. Therefore, the number of parity one start bits at the output of the second stage of rate matching can be given by equation (12).

(12)

(12)

In other words, equation (12) shows how to select the parity one start bit at the output of stage 2 rate matching, which is determined as a function of dividing the number of the first parity bits by two after the collection of bits. This can be explained by the fact that half of the bits are parity circles and half is parity two, and the first parity bits inserted into the bit collection matrix are parity two bits.

이다. 그러므로, 레이트 매칭의 제 2 단의 출력에서 마지막 또는 종결 패리티 원 비트는 식 (13) 으로 주어질 수 있다.The last parity one bit processed by this CE is

to be. Therefore, the last or terminating parity one bit at the output of the second stage of rate matching can be given by equation (13).

(13)

(13)

In other words, equation (13) describes how to select the last parity one bit at the output of stage 2 rate matching. This can be explained by the fact that half of the bits are parity circles and half is parity two, and the first parity bits inserted into the bit collection matrix are parity two bits.

으로 표시되고,

는 레이트 매칭의 제 2 단의 출력에서 패리티 원 비트

를 주는 레이트 매칭의 제 1 단의 출력에서의 패리티 원 비트라고 가정한다. 펑쳐링의 경우, 레이트 매칭의 제 1 단의 출력에서의 최초 패리티 원 비트 N_{p1 _s} 는 식 (14) 로 주어질 수 있음을 보일 수 있다.The parity one bit at the output of the first stage of rate matching is

Displayed as

Is a parity one bit at the output of the second stage of rate matching

Assume that it is the parity one bit at the output of the first stage of rate matching that gives. In the case of puncturing, it can be shown that the first parity one bit N _{p1 _s} at the output of the first stage of rate matching can be given by equation (14).

(14)

(14)

Therefore N _{p1 s} can be determined as a function of the stage 2 rate matching parameter for the parity one bit, and the first parity one start bit at the output of the rate matching second stage from equation (12). In addition, the rate matching state value of the parameter e _ini in N _{p1 _ s} can be given by equation (15). The value of e _ini may vary depending on CE and depends on N _{p1_s} .

(15)

(15)

In the case of repetition, N _{p1 s} can be given by equation (16).

(16)

(16)

For the repetition value of the rate matching state variable at the N _{p1 _ s} can be given by equation (17).

(17)

(17)

는 레이트 매칭의 제 2 단의 출력에서 패리티 원 비트

를 주는 레이트 매칭의 제 1 단의 출력에서의 패리티 원 비트라고 가정하자. 펑쳐링의 경우, 레이트 매칭의 제 1 단의 출력에서의 패리티 원 종료 비트 N_{p1 _e} 는 식 (18) 로 주어질 수 있음을 볼 수 있다.

Is a parity one bit at the output of the second stage of rate matching

Assume that it is the parity one bit at the output of the first stage of rate matching that gives. In the case of puncturing, it can be seen that the parity one end bit N _{p1 _e} at the output of the first stage of rate matching can be given by equation (18).

(18)

(18)

Therefore, for puncturing, N _{p1 _ e} is a function of the rate matching parameter for the parity one bit for the second stage of rate matching, and the last parity one bit at the output of the stage 2 rate matching determined from equation (13). Can be determined. In the case of repetition, N _{p1 _e} can be given by equation (19).

(19)

(19)

으로 표시되는 것으로 가정하며, 여기서

는 레이트 매칭의 제 1 단의 출력에서 패리티 원 비트

를 주는 레이트 매칭의 제 1 단의 입력에서의 원 패리티 비트이다. 따라서 레이트 매칭의 제 1 단의 입력에서의 패리티 원 시작 비트 (예를 들어, 도 2 의 HARQ 블록으로의 입력을 위하여 실제로 선택된 (나머지 전부는 폐기된다) 패리티 원 시작 비트) (이 CE 에 의해 처리될 최초 비트), 즉 N_{in,p1_s} 는 식 (20) 에 의해 주어지는 것으로 결정될 수 있다.The parity one bit at the input of the first stage of rate matching is

Is assumed to be represented by

Is a parity one bit at the output of the first stage of rate matching

Is one parity bit at the input of the first stage of rate matching. Thus the parity one start bit at the input of the first stage of rate matching (e.g., the parity one start bit actually selected for the input to the HARQ block of FIG. 2 (the rest are discarded)) (processed by this CE) The first bit to be), i.e., N _{in, p1_s,} can be determined as given by equation (20).

(20)

20

Further, the value of the rate matching state variable at N _{in, p1 _ s} is given by the equation (21).

(21)

(21)

There is no repetition in the first stage of rate matching in the 3GPP standard.

는, 레이트 매칭의 제 1 단의 출력에서 패리티 원 비트

를 주는 레이트 매칭의 제 1 단의 입력에서의 패리티 원 비트라고 가정하자. 레이트 매칭의 제 1 단의 입력에서의 마지막 패리티 원 비트 (예를 들어, 도 2 의 HARQ 블록으로의 입력을 위하여 실제로 선택된 (나머지 전부는 폐기된다) 마지막 패리티 원 비트) N_{in , p1 _e} 는 식 (22) 로 의해 주어질 수 있다.

Is a parity one bit at the output of the first stage of rate matching.

Assume that it is the parity one bit at the input of the first stage of rate matching that gives. The last parity one bit at the input of the first stage of rate matching (e.g., the last parity one bit actually selected for input to the HARQ block of FIG. 2 (all remaining is discarded)) N _{in , p1 _e} It can be given by (22).

(22)

(22)

As described above, there is no repetition in the first stage of rate matching.

Therefore, equations 12-22 describe how to determine which parity one bit at the input of the HARQ block will be selected to fill the parity one bit position between columns N _{col , s} to N _{col , e} in the bit collection matrix. Using channelization codes ch _s to ch _e (e.g. 16-QAM or QPSK codes), these are transmitted with any system bits selected as described above and any parity to bits selected as described below. Parity one bit.

By way of example and as described above, the selection of parity one bit through HARQ functionality can be summarized as follows. A priority decision is made as to which parity bit should be selected for transmission by the CE (threshold decision, equations (10) and (11)). Secondly, the determination of the first and last parity one bit at the output of the second stage of rate matching is made as a function of the determined first and last parity bits after bit collection (Equations (12) and (13)).

Third, the first and last parity one bit at the output of the first stage of rate matching is at a corresponding rate matching parameter for the parity bit at the second stage of rate matching, and at the output of the second stage of rate matching. It can be determined as a function of the determined first and last one bit (Equations (14) to (19)). Finally, the parity one bit to be selected for input into the HARQ block for channel coding (e.g. parity one bit to fill between columns N _{col , s} to N _{col , e} of the bit collection matrix) is determined. It can be determined as a function of the first and last parity one bit at the output of the first stage of, and the corresponding rate matching stage 1 rate matching parameter for the parity one bit (Equations (20)-(22)).

Thus, each given CE pre-encodes the entire HS-DSCH transport block, but may post-encode only selected bits (eg by implementing HARQ functionality). Therefore, only selected bits (system, parity one, parity two bits) are channel coded (HARQ encoded) to be finally transmitted using a 16-QAM (or QPSK) channelization code from a given CE to one or more users. This channel encoding methodology can eliminate the need for a high speed serial bus and can allow for reduced latency compared to conventional channel coding methodologies.

HARQ  Selection of parity to bits to be encoded

The equations and decisions for selecting which parity-to-bit should go through channel coding in the HARQ block are substantially the same as those described above for the parity one bit, so the relevant equations are provided below for convenience and consistency, and the equations (10) and (11) ) is noted in the N _{t, p_s} these crystals are carried out for the N _t, parity-to-bit only if less than or equal to _{p_e} as determined. Assuming such a case, each given CE will make the following decisions to select parity to bits to be HARQ encoded, as detailed above in equations (23)-(33).

로 표시될 수 있다. 열 N_{col ,s} 와 N_{col ,e} 사이에서 사용되는 최초 패리티 투 비트는

이다. 레이트 매칭의 제 2 단의 출력에서의 패리티 투 비트의 수는 식 (23) 으로 주어질 수 있다.The parity to bit at the output of the second stage of rate matching is

It may be represented as. The first parity-to-bit used between columns N _{col , s} and N _{col , e} is

to be. The number of parity to bits at the output of the second stage of rate matching can be given by equation (23).

(23)

(23)

이다. 레이트 매칭의 제 2 단의 출력에서의 최종 패리티 투 비트의 수는 식 (24) 로 주어질 수 있다.The final (or end) parity-to-bit used between columns N _{col , s} and N _{col , e} is

to be. The number of final parity to bits at the output of the second stage of rate matching can be given by equation (24).

(24)

(24)

로 나타낼 수 있다. 비트

는 레이트 매칭의 제 2 단의 출력에서

를 주는 레이트 매칭의 제 1 단의 출력에서의 최초 패리티 투 비트이다. 펑쳐링의 경우, 레이트 매칭의 제 1 단의 출력에서의 최초 패리티 투 비트의 수는 식 (25) 로 주어질 수 있다.The parity to bit at the output of the first stage of rate matching is

It can be represented as. beat

At the output of the second stage of rate matching

Is the first parity to bit at the output of the first stage of rate matching. For puncturing, the number of first parity to bits at the output of the first stage of rate matching can be given by equation (25).

(25)

(25)

Further, the value of the rate matching state variable e _ini in N _{p2 _ s} can be given by equation (26).

(26)

(26)

In the case of repetition, N _{p2 s} can be determined by equation (27).

(27)

(27)

Further, in the case of repeating the value of the rate matching state variable at N _{_ s p2} is represented by formula (28).

(28)

(28)

는 레이트 매칭의 제 2 단의 출력에서 최종 패리티 투 비트

를 주는 레이트 매칭의 제 1 단의 출력에서의 최종 패리티 투 비트이다. 그에 따라, 펑쳐링의 경우, 레이트 매칭의 제 1 단의 출력에서의 최종 패리티 투 비트의 수 N_{p2 _e} 는 식 (29) 에 의해 주어질 수 있다.beat

Is the final parity to bit at the output of the second stage of rate matching.

Is the last parity to bit at the output of the first stage of rate matching. Accordingly, in the case of puncturing, the number N _{p2 _ e} of the last parity to bits at the output of the first stage of rate matching can be given by equation (29).

(29)

(29)

In the case of repetition, N _{p2 _e} can be given by equation (30).

(30)

(30)

Thus, similar to the determination of parity one bit, the first and last parity bits at the output of the second stage of rate matching can be calculated as a function of the first and last parity bits after the bit collection (Equations (23) and (24). )). The first and last parity to bits at the output of the first stage of rate matching are then the corresponding rate matching parameter for parity to bits at the second stage of rate matching, and the determined first at the output of the second stage of rate matching. And a final parity to bit function (Equations (25) through (30)). And, the final parity to bit calculation is performed by the first and last parity to bits to be input into the HARQ block for channel coding (e.g., the remaining columns N _{col , s in the} collection of bits not filled by the selected system and / or parity one bit). N _{par , e} to fill the parity to bit).

로 표현될 수 있으며,

는 레이트 매칭의 제 1 단의 출력에서 패리티 투 비트

를 주는 레이트 매칭 제 1 단의 입력에서의 패리티 투 비트이다. 따라서, 레이트 매칭의 제 1 단의 입력에서의 최초 패리티 투 비트 (예를 들어, 도 2 의 HARQ 블록으로의 입력을 위해 실제로 선택된 (나머지는 모두 무시됨) 패리티 투 시작 비트) 는 식 (31) 에 의해 주어진 것과 같이 결정될 수 있다.The parity to bit at the input of the first stage of rate matching is

Can be expressed as

Parity to bit at the output of the first stage of rate matching

Parity to bit at the input of the rate matching first stage. Thus, the first parity to bit at the input of the first stage of rate matching (e.g., the parity to start bit actually selected for the input to the HARQ block of FIG. 2 (all others are ignored)) is Can be determined as given by

(31)

(31)

The value of the rate matching state variable at N _{in, p2 _ s} is given by the equation (32).

(32)

(32)

As mentioned above, there is no repetition in the first stage of rate matching.

는 레이트 매칭의 제 1 단의 출력에서의 최종 패리티 투 비트

를 주는 레이트 매칭의 제 1 단의 입력에서의 최종 패리티 투 비트이다. 레이트 매칭의 제 1 단의 입력에서의 최종 패리티 투 종결 비트 (예를 들어, 도 2 의 HARQ 블록으로의 입력을 위해 실제로 선택된 (나머지는 모두 무시됨) 최종 패리티 투 비트) N_{in , p2 _e} 는 식 (33) 으로 주어질 수 있다.parameter

Is the last parity to bit at the output of the first stage of rate matching.

Is the last parity to bit at the input of the first stage of rate matching. Final parity-to-end bit of the first in the input of first stage of rate matching (e.g., as actually selected (all others ignored for input to the HARQ block of FIG. 2) the final parity-to-bit) N _{in, p2 _e} is Can be given by equation (33).

(33)

(33)

There is no repetition in the first stage of rate matching.

Thus, the above equations describe how to determine which system bits, parity one bit and parity two bits in the input to the HARQ block will fill the columns N _{col , s} to N _{col , e} of the bit collection matrix. It is these bits that are to be transmitted using channelization codes ch _s through ch _e (eg, 16-QAM (or QPSK) codes). It is only these bits that must pass through the HARQ block of FIG. The remaining bits from the turbo encoder are ignored by the HARQ functionality.

Having described channel coding of bits in an HS-DSCH transport block, the rate matching principle can also be used to determine which bits of a turbo encoded transport block should be delivered with HARQ functionality and not punctured.

3 is a block diagram illustrating a two stage rate matching algorithm. In the following, reference may be made to FIG. 3 to describe a method of determining bits of an HS-DSCH transport block that will pass through an HARQ block and will not be punctured in accordance with an exemplary embodiment of the invention.

This example method is applicable to systems employing HSDPA where the puncturing rate is close to or near 1 (ie, a high puncturing rate environment). The purpose of this example methodology is that most of the separated bits at the output of the bit separator in the HARQ block are punctured (e.g. discarded by HARQ functionality), ie substantially system parity circles and / or It may be to save MIPS (or DSP cycle time in a DSP implementation) in a high puncturing rate environment where parity to bits are rarely passed to the first and second rate matching stages.

For example, in a given HSDPA channel in a relatively ideal environment, system bits are passed to the rate matching stage and most, if not all, parity bits are punctured. This brings the coding rate closer to 1, which can be interpreted as improving efficiency, reducing redundant information, and increasing overall system throughput. However, even in a less ideal channel environment, it may have a high puncturing rate, such as when data is repeated over multiple transmissions. Thus, the example methodology can be applied to any communication system and / or channel environment that suffers from high puncturing rates.

Puncturing Rate  By approaching 1 Puncturing  algorithm

3 is a simple two stage rate matching algorithm. The ratio between the number of bits at the input / output of each rate matching stage can be given by equation (34).

(34)

(34)

In equation (34), X ₁ and X ₂ represent integer values of bits, and Y ₁ and Y ₂ represent fractional values of bits. Therefore, Equation (34) states that for every 1 bit at the output of the stage 2 rate matching, there is X ₁ .Y ₁ bit at the input to the first rate matching stage (stage 1) and the input / stage 1 rate to stage 2 The output of the match explains that there are X ₂ .Y ₂ bits. The rate matching parameter for the first stage of rate matching may be represented by e _{ini _1} , e _{minus _1} and e _{plus _ 1} . The rate matching parameter for the second stage of rate matching may be represented by e _{ini _2} , e _{minus _2} and e _{plus _ 2} .

Thus, a set of the following equations (35) to (40) can be defined for bits X ₂ and bits Z ₂ , X _A , Z _A , X _B and Z _B. The parameter X ₂ may indicate a floor, ie, a lower limit, of X ₂ .Y ₂ bits at the input of input / stage 1 rate matching to stage 2 (X ₂ = floor (X ₂ .Y ₂ )), Z2 may indicate a ceiling, or upper limit, of X ₂ .Y ₂ bits at the input of input / stage 1 rate matching to stage 2 (Z ₂ = celing (X ₂ .Y ₂ )). Using this notation further, X _A = floor (X ₂ * X ₃ .Y ₃ ), ie X ₃ in stage 1 rate matching _. Y ₃ bit times lower bound of X ₂ , Z _A = ceiling (X ₂ * X ₃ .Y ₃ ), X _B = ceiling (Z ₂ * X ₃ .Y ₃ ), and Z _B = ceiling (Z ₂ * X ₃ .Y ₃ ). If X ₃ .Y ₃ is the ratio between N _in and N ₁ (described in the previous paragraph), then X ₃ .Y ₃ bits at the input of stage 1 produce one bit at the output of stage 1.

Justice:

(35)

(35)

(36)

(36)

here,

이 정수이면,

If is an integer

이다.Otherwise

to be.

Justice

(37)

(37)

(38)

(38)

here,

이 정수이면,

이고,

If is an integer

ego,

이다.Otherwise

to be.

Justice

(39)

(39)

(40)

40

here,

이 정수이면,

이고,

If is an integer

ego,

이다.Otherwise

to be.

If X ₁ and X ₂ are much greater than 1, then the output bits are fewer than the input bits, so performing on output bits rather than input bits may be a more efficient implementation of the rate matching algorithm. In one example, the k th input bit A _k produces the m th bit B _m at the output of the first stage of rate matching, which produces the n th bit C _n at the output of the second stage of rate matching. Therefore, the (n + 1) th bit at the output of the second stage of rate matching is the (m + X ₂ ) or (m + Z ₂ ) bit at the output of stage 1, which is (k + at the input of stage 1). X _A ), (k + Z _A ), (k + X _B ) or (k + Z _B ).

In other words, to select the next output bit, skip the X ₂ -1 or Z ₂ -1 bit at the output of stage 1 (the input of stage 2). Skipping the X ₂ -1 bits at the output of stage 2 (these bits are punctured and / or discarded), skips the X _A -1 or Z _A -1 bits at the input of stage 1. Alternatively, skipping the Z ₂ -1 bits at the output of stage 1 skips the X _B -1 or Z _B -1 bits at the input to stage 1.

Table 2 lists the definitions of the rate matching state variables below used in the rate matching stage. The rate matching state variable e is updated each time the input bit is processed (e _{minus _} is subtracted) as described in TS 25.212. If the state variable is updated and its value is negative, the bits are punctured and e _{plus _} is added to make the value positive.

The update of the stage 1 and stage 2 rate matching state variables e ₁ (n) and e ₂ (n) and the selection of the input bits corresponding to the (n + 1) output bits may be performed as indicated in the algorithm below. Describes how bits are selected to pass through the HARQ block and not be punctured. In general, each rate matching stage has a state variable associated with it. If the state variable meets a certain condition or is negative, the output bit is punctured. In general, the algorithm looks at the output bits from the second rate matching stage and determines whether the output bits match the input bits input to the first stage of rate matching. For an output bit that satisfies a particular discriminant in the algorithm, the next bit that causes the output of the bit that satisfies the condition from stage 2 passes through the input of stage 1 and is not punctured.

Thus, for stage 2 rate matching, the algorithm processes X ₂ bits, and if the state variable e ₂ (n) is not positive, an “add bit” is processed. For stage 1 rate matching, the number of bits processed is X _A or X _B (depending on the number of bits processed in stage 2). If the state variable e ₁ (n) is negative, an "add bit" is processed.

4 illustrates which bits of a received transport block are passed and not punctured, based on HARQ functionality implemented to channel code the bits for transmission to a given user by a channel element, in accordance with an exemplary embodiment of the present invention. A process flow diagram that describes how to determine. We will often quote Figure 4 for discussion of the algorithm below.

In the algorithm below, "k" represents the index of the bit at the input to the first stage of rate matching, and "m" represents the index of the bit at the output of the first stage of input / second stage of rate matching. Denotes an index of the bit output from the second stage of rate matching. For ease of understanding, the process steps of FIG. 4 corresponded to the steps of the algorithm below.

Let:

//X₂ 비트가 처리되고, 그 중 X₂-1 가 펑쳐링된다 (404)

// X ₂ bits are processed, of which X ₂ -1 is punctured (404)

(406 의 출력이 "예")if

(406 output is "Yes")

{

//스테이지 2 레이트 매칭에서 추가 비트가 처리된다 (408)

// Additional bits are processed in stage 2 rate matching (408)

선택. (410)Bits at Input to Stage 2

Selection. (410)

//스테이지 1 레이트 매칭에서 X_B 비트가 처리되고, 그 중 X_B-Z₂ 가 펑쳐링된다. (412)

// X _B bits are processed in stage 1 rate matching, of which X _B -Z ₂ are punctured. (412)

(414 의 출력이 "예")if

(414 output is "yes")

{

//스테이지 1 레이트 매칭에서 추가 비트가 처리된다 (416)

// Additional bits are processed in stage 1 rate matching (416)

선택. (418)Bits at Input to Stage 1

Selection. (418)

}

(420)else

(420)

선택. (422)Bits at Input to Stage 1

Selection. (422)

}

(406 의 출력이 '아니오'. 424 참조)else

(The output of 406 is no. See 424.)

{

선택. (426)Bits at Input to Stage 2

Selection. (426)

//스테이지 1 레이트 매칭에서 X_A 비트가 처리되고, 그 중 X_A-X₂ 가 펑쳐링된다. (428)

// X _A bits are processed in stage 1 rate matching, of which X _A -X ₂ is punctured. (428)

(430 의 출력이 '예')if

(430 output is yes)

{

//스테이지 1 레이트 매칭에서 추가 비트가 처리된다 (432)

// Additional bits are processed in stage 1 rate matching (432)

선택. (434)Bits at Input to Stage 1

Selection. (434)

}

(436)else

(436)

선택. (438)Bits at Input to Stage 1

Selection. (438)

}

Depending on which sub-criteria in the algorithm is satisfied, as shown in FIG. 4, the next bit (k (n + 1)) at the input to the first stage of rate matching is from the second stage of rate matching. Is selected from the next bit output n (n + 1) (440), and the algorithm repeats (output 442 is 'no') until there are no more bits to process. Assuming that at least X ₂ bit is present to produce the following output bit from the stage 2, and X ₂ ≤Z _2. If this relationship is correct, the value of e ₂ (rate matching state variable for stage 2) must be positive. e ₂ If is negative or 0, this means that the Z ₂ bits should have been processed by the second rate matching stage.

reset

Initialization must be performed to determine the behavior of rate matching at startup. Assume that input bit k ₁ (input to stage 1) produces bit m ₁ at the output of the first stage of rate matching, which in turn produces the first output bit n ₁ from the second stage of rate matching. Therefore, the first bit k to pass through the HARQ block can be determined from the following equation.

(41)

(41)

And

(42)

(42)

In other words, m ₁ is determined as a function of rate matching parameter for the second stage of rate matching, and k ₁ is determined as a function of rate matching parameter and m ₁ for the first stage of rate matching.

The rate matching state variable of the second stage after processing bit m ₁ can be given by equation (43).

(43)

(43)

The rate matching state variable of the first stage after processing bit k ₁ may be given by equation (44).

(44)

(44)

In equations (43) and (44), the values of e ₂ (1) and e ₁ (1) after bit n is passed and not punctured are the rate matching parameters for the first and second stages of rate matching and m Can be determined based on the initial values calculated for ₁ and k ₁ .

Therefore, based on the HARQ functionality implemented for channel coding bits for transmission to one or more users by a channel element, an exemplary method of determining which bits of a received transport block are not to be passed and punctured is Computational complexity can be reduced by processing the data based on the output bit rate rather than the bit rate. In this case, the output bit rate may be substantially smaller than the input bit rate. Although this example has been described for a two-stage rate matching algorithm, the method can be extended to (N> 2) multi-stage rate matching implementations where there are more than two rate matching stages.

While the exemplary embodiments of the invention have been described above, it will be apparent that they can be modified in various ways. Such modifications should not be construed as departing from the spirit and scope of the exemplary embodiments of the invention, and all such modifications apparent to those skilled in the art are intended to be included within the scope of the following claims.

Claims (11)

A method of encoding data for transmission to one or more users, the method comprising: Selecting a given number of data bits from the transport block to be delivered to the Hybrid Automatic Request (HARQ) block for channel coding; Channel coding the selected bits in a HARQ block for transmission to one or more users using a given set of channelization codes. Data encoding method. The method of claim 1, The encoded input data stream is divided into a full set of system bits, parity one bit and parity two bits, The selecting includes selecting a given number of system bits, parity one bits, and parity two bits, less than the entire set, for channel coding in the HARQ block, The method, Subjecting the selected system bits, parity one bit and parity to bit to a rate matching algorithm having a first rate matching stage and a second rate matching stage; Combining the system bits, the parity one bit and the parity to bit output of the second rate matching stage by filling in a column in a bit collection matrix, The bits in the bit collection matrix are transmitted using the given channelization code set. Data encoding method. The method of claim 2, Selecting the given number of data bits from the transport block to be delivered to the HARQ block for channel coding, For channel coding and the final transmission and determining a first systematic bits, N _{sys _ s} at the output of the first stage of rate matching to be processed by the HARQ block, Determining a last system bit, N _{sys _ e} , at the output of the first stage of rate matching to be processed by the HARQ block for channel coding and final transmission; Selecting a system bit between N _{sys _s} and N _{sys _e} , Performing a second stage of rate matching only for the selected system bit, N _{sys s} is determined based on the rate matching parameter for the first system bit N _{t , sys s,} and the system bit at the second stage of the rate matching, which is to be transmitted at the output of the second stage of the rate matching, N _{sys _ e} is determined based on the last system bit N _{t , sys _ e to} be transmitted at the output of the second stage of the rate matching, and the rate matching parameter for the system bit at the second stage of the rate matching. Data encoding method. The method of claim 3, wherein The rate matching state variable for the first bit to be processed in the HARQ block for transmission is the rate matching state variable e _{ini , sys _2} for the second stage of the rate matching and the system at the second stage of the rate matching. Determined as a function of the rate matching parameters (e _{minus , sys _2} and e _{plus , sys _2} ) for the bits Data encoding method. The method of claim 2, Selecting the given number of data bits from the transport block to be delivered to the HARQ block for channel coding, Performing an initial threshold determination as to whether system bits, parity one bits, and parity to bits should be processed by the HARQ block for final transmission; If the threshold determination is satisfied, a given parity one bit and parity two bit is selected from the entire set, otherwise only system bits are passed and all parity one bit and parity two bit are punctured by the HARQ block ( puncturing) and not going through channel coding Data encoding method. The method of claim 5, wherein The selecting step, Determine a first and last parity one bit at the output of the second stage of the rate matching based on the parity bits combined after a bit collection, Output of the first stage of the rate matching as a function of the rate matching parameter for the parity bit in the second stage of the rate matching and the determined first and last parity one bit at the output of the second stage of the rate matching. Determines the first and last parity one bit in Input into the HARQ block for channel coding based on the determined first and last parity one bit at the output of the first stage of the rate matching and the rate matching parameter for the parity one bit at the first stage of the rate matching By selecting the parity one bit to be Selecting a given parity one bit that will undergo channel coding for final transmission; Data encoding method. The method of claim 5, wherein The selecting step, Determine a first and last parity to bit at the output of the second stage of the rate matching based on the parity bits combined after the collection of bits, The first stage of the rate matching as a function of the rate matching parameter for the parity two bits in the second stage of the rate matching and the determined first and last parity two bits at the output of the second stage of the rate matching. Determine the first and last parity-to-bit at the output, Input into the HARQ block for channel coding based on the determined first and last parity two bits at the output of the first stage of the rate matching and the rate matching parameter for the parity two bits at the first stage of the rate matching. By selecting the parity to bit to be Selecting a given parity to bit that will undergo channel coding for final transmission; Data encoding method. CLAIMS 1. A method of determining which data bits to pass to a rate matching function within a channel element for encoding the bits prior to transmission by the channel element to one or more users. Dividing the transmission block received by the channel element into a full set of system bits, parity one bits and parity two bits; Selecting a given number of system bits, parity one bits, and parity to bits that are less than the entire set, going through the rate matching function in the HARQ block of the channel element for channel coding; Entering only selected bits into the HARQ block for transmission to the one or more users using a given set of channelization codes. How to determine data bits. 10. A method of determining which bits of a received transport block will pass a rate matching function implemented within the channel element to channel code the bits for transmission by the channel element, Determining bits that are to be input and not punctured into the first rate matching stage of the second stage matching function based on the set of bits to be output of the second rate matching stage. How to decide. The method of claim 9, The determining includes determining bits that are not to be punctured and passed to the first rate matching stage of the HARQ block based on output bits from the second rate matching stage of the function, The method, Based on the state variable for the second rate matching stage, forwarding the next bit to the first rate matching stage to obtain an output of the bit from the second stage that satisfies a given criterion. How to decide. The method of claim 9, The channel element has a puncturing rate approaching 1, where most of the bits are punctured. How to decide.

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