KR20080039143A - W-dual poly gate and manufacturing method of the same - Google Patents

W-dual poly gate and manufacturing method of the same Download PDF

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KR20080039143A
KR20080039143A KR1020060106925A KR20060106925A KR20080039143A KR 20080039143 A KR20080039143 A KR 20080039143A KR 1020060106925 A KR1020060106925 A KR 1020060106925A KR 20060106925 A KR20060106925 A KR 20060106925A KR 20080039143 A KR20080039143 A KR 20080039143A
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film
tungsten
layer
gate insulating
forming
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KR1020060106925A
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Korean (ko)
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김영훈
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주식회사 하이닉스반도체
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/28008—Making conductor-insulator-semiconductor electrodes
    • H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H01L21/28026—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
    • H01L21/28035—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823828—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
    • H01L21/823842—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes gate conductors with different gate conductor materials or different gate conductor implants, e.g. dual gate structures

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  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
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Abstract

A tungsten dual poly gate and a forming method thereof are provided to prevent crystal diminution of tungsten caused by Ti to restrict the increase of surface resistance of the tungsten gate by forming a barrier layer as a stacked structure including a titanium layer, a tungsten silicide layer and a tungsten nitride layer. A PMOS region and an NMOS region are formed on a silicon substrate, and a gate insulating layer(102) is formed at each region. A P-type polysilicon layer(106) is formed on the gate insulating layer of the PMOS region, and an N-type polysilicon layer(108) is formed on the gate insulating layer of the NMOS region. A barrier layer(A), which is made of a titanium layer, a first tungsten nitride layer, a tungsten silicide layer and a second tungsten nitride layer, is formed on the P-type and N-type poly silicon layers. The tungsten layer is formed on the barrier layer. A hard mask layer(120) is formed on the tungsten layer.

Description

텅스텐 듀얼 폴리 게이트 및 그의 형성 방법{W―Dual poly gate and manufacturing method of the same}Tungsten dual poly gate and its formation method {W―Dual poly gate and manufacturing method of the same}

도 1은 본 발명의 실시예에 따른 텅스텐 듀얼 폴리 게이트를 도시한 단면도. 1 is a cross-sectional view showing a tungsten dual poly gate according to an embodiment of the present invention.

도 2a 내지 도 2d는 본 발명의 실시예에 따른 텅스텐 듀얼 폴리 게이트의 형성 방법을 설명하기 위한 공정별 단면도.2A through 2D are cross-sectional views illustrating processes for forming a tungsten dual poly gate according to an embodiment of the present invention.

* 도면의 주요 부분에 대한 부호의 설명 *Explanation of symbols on the main parts of the drawings

100 : 실리콘 기판 102 : 게이트절연막100 silicon substrate 102 gate insulating film

106 : P형 불순물이 주입된 폴리실리콘막106: polysilicon film implanted with P-type impurities

108 : N형 불순물이 주입된 폴리실리콘막108: polysilicon film implanted with N-type impurities

110 : 티타늄막 112 : 제1텅스텐질화막110 titanium film 112 first tungsten nitride film

114 : 텅스텐실리사이드막 116 : 제2텅스텐질화막114: tungsten silicide film 116: second tungsten nitride film

118 : 텅스텐막 120 : 하드마스크막118: tungsten film 120: hard mask film

A : 베리어층 B : 게이트A: Barrier layer B: Gate

본 발명은 반도체 소자의 듀얼 폴리 게이트 및 그의 형성 방법에 관한 것으 로, 보다 상세하게는, 듀얼 폴리 게이트 형성시 도핑된 폴리실리콘막과 텅스텐(W)막 사이의 접촉 저항 및 면저항을 감소시킨 텅스텐 듀얼 폴리 게이트 및 그의 형성 방법에 관한 것이다. BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a dual poly gate of a semiconductor device and a method of forming the semiconductor device. More particularly, the present invention relates to a tungsten dual layer having reduced contact resistance and sheet resistance between a doped polysilicon film and a tungsten (W) film during formation of a dual poly gate. A poly gate and a method of forming the same.

반도체 소자가 고집적화, 고속화, 저전력화됨에 따라 소자를 구성하는 트랜지스터들의 크기가 급속도로 줄어들고 있다. 이에 따라, 전계효과 트랜지스터(Field Effect Transistor) 소자의 크기도 점점 더 줄어들고 있는 실정이다. 이에 대응하여, 소자가 최적의 성능을 가지도록 하기 위하여 트랜지스터의 설계를 변경할 필요가 있다.As semiconductor devices become more integrated, faster, and lower power, the transistors constituting the device are rapidly decreasing in size. Accordingly, the size of the field effect transistor (Field Effect Transistor) device is also increasingly reduced. Correspondingly, it is necessary to change the design of the transistor in order for the device to have optimal performance.

현재, 반도체 소자의 집적도 증가에 따른 반도체 소자의 마진 개선을 확보하기 위한 방안 중의 하나로, 미세선폭을 가지는 모스펫(MOSFET) 소자에서 단채널효과(short channel effect)에 관련된 문제를 해결하기 위하여 듀얼 폴리 게이트형 CMOS 소자가 폭넓게 사용되고 있다. Currently, one of the methods for securing the margin improvement of the semiconductor device according to the increase in the integration degree of the semiconductor device, the dual poly gate to solve the problem related to the short channel effect (MOSFET) device having a fine line width Type CMOS devices are widely used.

이와 같은, 듀얼 폴리 게이트형 CMOS 소자는 NMOS 및 PMOS로 구성되며, 상기 NMOS는 N형 분순물이 주입된 N형 폴리실리콘 게이트 전극을 가지고, PMOS는 보론(B)과 같은 P형 불순물이 주입된 P형 폴리실리콘 게이트 전극을 가진다. 그리고, 듀얼 폴리 게이트형 CMOS 소자는 상기 N형 및 P형 불순물이 주입된 폴리실리콘막 상에 베리어층들과 전극계막 및 하드마스크막이 순차적으로 적층된 구조의 게이트로 가진다. Such a dual poly-gate CMOS device is composed of NMOS and PMOS, the NMOS has an N-type polysilicon gate electrode implanted with an N-type impurities, PMOS is a P-type impurity such as boron (B) is injected It has a P-type polysilicon gate electrode. The dual poly-gate CMOS device has a gate structure in which barrier layers, an electrode layer film, and a hard mask film are sequentially stacked on a polysilicon film into which the N-type and P-type impurities are injected.

한편, 최근 전극계막으로 텅스텐(W)이 사용되고 있고, 상기 전극계막과 불순물이 주입된 폴리실리콘막 사이의 접촉 계면 특성을 향상시켜 접촉 저항을 감소시 키기 위하여 사용되는 베리어층은 일반적으로 텅스텐질화막이 사용된다.On the other hand, tungsten (W) has recently been used as an electrode-based film, and a barrier layer used to reduce contact resistance by improving the contact interface property between the electrode-based film and a polysilicon film into which impurities are injected is generally used as a tungsten nitride film. Used.

그러나, 전극계막으로 텅스텐(W)이 사용된 텅스텐 듀얼 폴리 게이트에서 베리어층으로 텅스텐질화막을 사용할 경우 폴리실리콘막과 텅스텐질화막 사이의 계면 접촉저항의 증가로 RC 지연 시간이 증가되어 소자의 속도가 느려진다.However, when the tungsten nitride layer is used as the barrier layer in the tungsten dual poly gate using tungsten (W) as the electrode layer, the RC delay time is increased due to the increase in the interfacial contact resistance between the polysilicon film and the tungsten nitride film, thereby slowing down the device speed. .

따라서, 본 발명은 듀얼 폴리 게이트 형성시 도핑된 폴리실리콘막과 텅스텐막 사이의 접촉 저항 및 면저항을 감소시킨 텅스텐 듀얼 폴리 게이트 및 그의 형성 방법을 제공한다.Accordingly, the present invention provides a tungsten dual poly gate and a method of forming the same, which reduce contact resistance and sheet resistance between the doped polysilicon film and the tungsten film when forming the dual poly gate.

일 실시예에 있어서, 텅스텐 듀얼 폴리 게이트는, PMOS 및 NMOS 영역을 갖는 실리콘기판의 각 영역 상에 형성된 게이트절연막; 상기 PMOS 영역의 게이트절연막 상에 형성된 P형 폴리실리콘막 및 NMOS 영역의 게이트절연막 상에 형성된 N형 폴리실리콘막; 상기 P형 폴리실리콘막 및 N형 폴리실리콘막 상에 형성되고, 티타늄막/제1텅스텐질화막/텅스텐실리사이드막/제2텅스텐질화막으로 이루어진 베리어층; 상기 베리어층 상에 형성된 텅스텐막; 및 상기 텅스텐막 상에 형성된 하드마스크막을 포함한다.In one embodiment, a tungsten dual poly gate comprises: a gate insulating film formed on each region of a silicon substrate having PMOS and NMOS regions; A P-type polysilicon film formed on the gate insulating film in the PMOS region and an N-type polysilicon film formed on the gate insulating film in the NMOS region; A barrier layer formed on the P-type polysilicon film and the N-type polysilicon film and formed of a titanium film / first tungsten nitride film / tungsten silicide film / second tungsten nitride film; A tungsten film formed on the barrier layer; And a hard mask film formed on the tungsten film.

다른 실시예에 있어서, 텅스텐 듀얼 폴리 게이트 형성 방법은, PMOS 및 NMOS 영역을 갖는 실리콘기판 상에 게이트절연막을 형성하는 단계; 상기 PMOS 영역의 게이트절연막 상에 P형 불순물로 도핑된 P형 폴리실리콘막을 형성함과 아울러 상기 NMOS 영역의 게이트절연막 상에 N형 불순물로 도핑된 N형 폴리실리콘막을 형성하는 단계; 상기 P형 및 N형 폴리실리콘막 상에 베리어층으로서 티타늄막/제1텅스텐질화막/텅스텐실리사이드막/제2텅스텐질화막의 베리어층을 형성하는 단계; 상기 티타늄막/제1텅스텐질화막/텅스텐실리사이드막/제2텅스텐질화막의 베리어층 상에 텅스텐막을 형성하는 단계; 상기 텅스텐막 상에 하드마스크막을 형성하는 단계; 및 상기 하드마스크막, 텅스텐막, 티타늄막/제1텅스텐질화막/텅스텐실리사이드막/제2텅스텐질화막의 베리어층, P형 폴리실리콘막과 N형 폴리실리콘막 및 게이트절연막을 식각하는 단계를 포함한다. In another embodiment, a tungsten dual poly gate forming method includes forming a gate insulating film on a silicon substrate having PMOS and NMOS regions; Forming a P-type polysilicon film doped with a P-type impurity on the gate insulating film in the PMOS region and forming an N-type polysilicon film doped with N-type impurity on the gate insulating film in the NMOS region; Forming a barrier layer of a titanium film / first tungsten nitride film / tungsten silicide film / second tungsten nitride film as a barrier layer on the P-type and N-type polysilicon films; Forming a tungsten film on the barrier layer of the titanium film / first tungsten nitride film / tungsten silicide film / second tungsten nitride film; Forming a hard mask film on the tungsten film; And etching the barrier layer, the P-type polysilicon film, the N-type polysilicon film, and the gate insulating film of the hard mask film, the tungsten film, the titanium film, the first tungsten nitride film, the tungsten silicide film, and the second tungsten nitride film. .

상기 티타늄막/제1텅스텐질화막/텅스텐실리사이드막/제2텅스텐질화막의 베리어층을 형성하는 단계 후, 수소(H2) 가스를 이용하여 어닐링하는 단계를 더 포함한다.After forming the barrier layer of the titanium film / first tungsten nitride film / tungsten silicide film / second tungsten nitride film, further comprising the step of annealing using hydrogen (H 2 ) gas.

(실시예)(Example)

이하, 첨부된 도면을 참조하여 본 발명의 바람직한 실시예를 상세하게 설명하도록 한다.Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

도 1은 본 발명의 실시예에 따른 텅스텐 듀얼 폴리 게이트를 도시한 단면도이다.1 is a cross-sectional view illustrating a tungsten dual poly gate according to an embodiment of the present invention.

도시된 바와 같이, 본 발명에 따른 반도체 소자의 듀얼 폴리 게이트는 활성영역(Actrive Area)을 한정하는 소자분리막(미도시)을 구비하고, PMOS 및 NMOS 영역을 갖는 실리콘 기판(100)의 활성영역 상에 게이트절연막(102), N형 및 P형 불순물이 주입된 폴리실리콘막(108, 1006), 베리어층(A), 텅스텐막(118) 및 하드마스크 막(120)이 순차적으로 적층된 게이트(B)가 형성되어 있다.As shown, the dual poly gate of the semiconductor device according to the present invention has an isolation layer (not shown) defining an active area, and is formed on the active area of the silicon substrate 100 having PMOS and NMOS areas. A gate in which the gate insulating film 102, the polysilicon films 108 and 1006 implanted with N-type and P-type impurities, the barrier layer A, the tungsten film 118, and the hard mask film 120 are sequentially stacked. B) is formed.

여기서, 상기 베리어층(A)은 N형 및 P형 불순물이 주입된 폴리실리콘막(108, 106) 상에 티타늄(Ti)막(110), 제1텅스텐질화막(WN)(112), 텡스텐실리사이드막(114), 제2텅스텐질화막(WN)(116)이 순차적으로 적층되어 구성된다.Here, the barrier layer (A) is a titanium (Ti) film 110, the first tungsten nitride film (WN) 112, tungsten on the polysilicon film 108, 106 implanted with N-type and P-type impurities The silicide film 114 and the second tungsten nitride film (WN) 116 are sequentially stacked.

그리고, 상기 적층 구조의 베리어층(A)에서 상기 티타늄막(110)은 P형 폴리실리콘에 포함된 보론(B)의 확산을 막아 폴리실리콘막들(106, 108)과의 계면을 안정시켜 접촉 저항을 감소시키고, 제1텅스텐질화막(112)은 상기 티타늄막(110)과 상부에 형성된 텅스텐실리사이드막(114)과의 접촉 계면을 안정시킨다. 또한, 텅스텐실리사이드막(114)은 상기 티타늄막(110)을 구성하는 티타늄(Ti)의 결정 크기로 인해 게이트의 최상부에 형성되는 텅스턴(W)막(118)의 결정 감소를 막아 결정 감소에 따른 게이트(B)의 면저항을 감소시키고, 제2텅스텐질화막(116)은 텅스텐실리사이드막(114)과 상부에 형성된 텅스텐막(118)과의 계면을 안정시켜 접촉 저항을 감소시키는 접촉 계면을 안정화시킨다. In addition, in the barrier layer A of the laminated structure, the titanium film 110 prevents the diffusion of boron B included in the P-type polysilicon to stabilize the interface with the polysilicon films 106 and 108. The resistance is reduced, and the first tungsten nitride film 112 stabilizes the contact interface between the titanium film 110 and the tungsten silicide film 114 formed thereon. In addition, the tungsten silicide film 114 prevents a decrease in crystallization of the tungsten (W) film 118 formed at the top of the gate due to the crystal size of titanium constituting the titanium film 110. The sheet resistance of the gate B is reduced, and the second tungsten nitride film 116 stabilizes the interface between the tungsten silicide film 114 and the tungsten film 118 formed thereon to stabilize the contact interface that reduces the contact resistance. .

그러나, 전술된 적층 구조와 동일하게 상기 베리어층(A)을 구성하지 않고 텅스텐실리사이드막(114)과 제2텅스텐질화막(116)만의 적층구조로 베리어층을 구성할 경우, P형 폴리실리콘막(106) 내의 보론(B)이 텅스텐실리사이드막(114)으로 확산하여 텅스텐실리사이드막(114)이 불균일해진다. 이에 따라, 국부적으로 텅스텐실리사이드막(114)이 매우 얇아져 상부의 제2텅스텐질화막(116)과 P형 폴리실리콘막(106)이 콘택하게 됨으로써 계면 접촉저항이 증가하고, 회로의 RC 지연 시간이 증가되어 속도가 느려져, 심한 경우, 게이트절연막(102)에서 리키지(Leakage)가 급격히 증가 하게 된다.However, when the barrier layer is formed in the laminated structure of only the tungsten silicide film 114 and the second tungsten nitride film 116 without forming the barrier layer A in the same manner as the stacked structure described above, the P-type polysilicon film ( Boron B in 106 diffuses into the tungsten silicide film 114 and the tungsten silicide film 114 becomes nonuniform. As a result, the tungsten silicide film 114 is locally thinned so that the second tungsten nitride film 116 and the P-type polysilicon film 106 contact each other, thereby increasing the interface contact resistance and increasing the RC delay time of the circuit. As a result, the speed becomes slow, and in severe cases, leakage increases in the gate insulating film 102.

또한, 상기 베리어층이 티타늄막(110)과 제1텅스텐질화막(112)만의 적층구조로 구성할 경우, 티타늄막(110)에 의해 P형 폴리실리콘막(106) 내의 보론(B)이 확산되는 것이 방지되어 계면이 안정되고 계면 접촉저항이 감소되어 게이트절연막(102)의 신뢰성도 개선되지만, 티타늄(Ti)의 결정크기가 작아 후속에 증착되는 제1텅스텐질화막(112)과 텅스텐막(118)의 결정크기도 작아져 텅스텐(W)을 사용한 게이트(B)의 면저항이 증가하게 된다. 이로 인해, 높아진 면저항으로 게이트에 텅스텐(W)을 사용한 이점이 사라지고, 면저항의 증가는 DRAM의 tRCD의 증가로 이어져 소자의 속도를 저하시킨다.In addition, when the barrier layer has a stacked structure of only the titanium film 110 and the first tungsten nitride film 112, the boron B in the P-type polysilicon film 106 is diffused by the titanium film 110. Although the interface is stabilized and the interfacial contact resistance is reduced, the reliability of the gate insulating film 102 is also improved. However, since the crystal size of titanium (Ti) is small, the first tungsten nitride film 112 and the tungsten film 118 which are subsequently deposited are deposited. Also, the crystal size of is decreased, and the sheet resistance of the gate B using tungsten (W) increases. This eliminates the advantage of using tungsten (W) in the gate due to the increased sheet resistance, and increasing the sheet resistance leads to an increase in the tRCD of the DRAM, thereby lowering the speed of the device.

따라서, 베리어층(A)이 티타늄막(110), 제1텅스텐질화막(WN)(112), 텡스텐실리사이드막(114), 제2텅스텐질화막(WN)(116)의 적층 구조를 가짐으로써, P형 폴리실리콘막(106)과 베리어층(A) 간의 접촉저항이 감소되고, 소자의 RC 지연 시간이 감소되어 소자의 속도를 개선할 수 있다. 그리고, 계면특성이 안정되어 게이트절연막(102)의 신뢰성이 개선되고, 게이트 접촉면의 저항 증가를 방지하여 DRAM의 tRCD를 개선하여 소자의 속도를 개선할 수 있다. Therefore, the barrier layer A has a laminated structure of the titanium film 110, the first tungsten nitride film (WN) 112, the tungsten silicide film 114, and the second tungsten nitride film (WN) 116. The contact resistance between the P-type polysilicon film 106 and the barrier layer A is reduced, and the RC delay time of the device is reduced, thereby improving the device speed. In addition, since the interfacial characteristics are stabilized, the reliability of the gate insulating layer 102 is improved, and the resistance of the gate contact surface is prevented from increasing, thereby improving the tRCD of the DRAM to improve the device speed.

자세하게,도 2a 내지 도 2d는 본 발명의 실시예에 따른 텅스텐 듀얼 폴리 게이트의 형성 방법을 설명하기 위한 공정별 단면도로서, 이를 설명하면 다음과 같다. 2A to 2D are cross-sectional views illustrating processes for forming a tungsten dual poly gate according to an exemplary embodiment of the present invention.

도 2a를 참조하면, 주지된 STI(Shallow Trench Isolation) 공정에 따라 활성영역을 한정하는 소자분리막(미도시)이 구비되어 있고, 웰(Well)이 형성된 실리콘 기판(200)을 준비한다. 그런 다음, 상기 실리콘 기판(200)의 전면에 게이트절연막(202)을 형성시킨 후, 상기 활성영역 상에 비도핑된 폴리실리콘막(204)을 형성한다. Referring to FIG. 2A, an isolation layer (not shown) defining an active region is provided according to a well-known shallow trench isolation (STI) process, and a silicon substrate 200 having a well is prepared. After that, a gate insulating film 202 is formed on the entire surface of the silicon substrate 200, and then an undoped polysilicon film 204 is formed on the active region.

이때, 상기 활성영역 상에 형성되는 폴리실리콘막(204)은 N형 불순물이 주입된 폴리실리콘막을 사용할 수도 있다. In this case, the polysilicon film 204 formed on the active region may use a polysilicon film into which N-type impurities are injected.

도 2b를 참조하면, 상기 폴리실리콘막(204)의 NMOS부 및 PMOS부가 형성될 활성 영역 상에 각각 감광막패턴(미도시)을 형성하여, 보론(B)과 같은 P형 불순물의 이온주입을 수행하여 P형 불순물이 주입된 폴리실리콘막(206)을 형성하고, N형 불순물 이온주입을 수행하여 N형 폴리실리콘막(208)을 형성한다.Referring to FIG. 2B, a photoresist pattern (not shown) is formed on the active region where the NMOS portion and the PMOS portion of the polysilicon film 204 are to be formed, and ion implantation of P-type impurities such as boron B is performed. As a result, a polysilicon film 206 implanted with P-type impurities is formed, and an N-type impurity ion implantation is performed to form an N-type polysilicon film 208.

도 2c를 참조하여, 상기 N형 및 P형 폴리실리콘막(208, 206) 상에 티타늄막(210), 제1텅스텐질화막(212), 텅스텐실리사이드막(214), 제2텅스텐질화막(216), 텅스텐막(218) 및 하드마스크막(220)을 순차적으로 증착하여 베리어층(A)을 형성한다. 이때, 필요에 따라 상기 막들의 증착이 끝난 후 계면특성을 위하여 수소(H2) 가스를 이용한 어닐링(Annealing) 공정을 진행할 수 있다.Referring to FIG. 2C, the titanium film 210, the first tungsten nitride film 212, the tungsten silicide film 214, and the second tungsten nitride film 216 are formed on the N-type and P-type polysilicon films 208 and 206. , The tungsten film 218 and the hard mask film 220 are sequentially deposited to form the barrier layer A. FIG. In this case, annealing process using hydrogen (H 2 ) gas may be performed for interfacial properties after the deposition of the films, if necessary.

도 2d를 참조하여, NMOS부와 PMOS부를 구분하기 위하여 식각마스크(미도시)를 형성하고 식각 공정을 진행하여 하드마스크막(220), 텅스텐막(218), 제2텅스텐질화막(216), 텅스텐실리사이드막(214), 제1텅스텐질화막(212), 티타늄막(210), N형 및 P형 폴리실리콘막(208, 206) 및 게이트절연막(202)을 제거하고 NMOS부와 PMOS부로 구분된 텅스텐 듀얼 폴리 게이트(B)의 형성을 완료한다.Referring to FIG. 2D, an etching mask (not shown) is formed to distinguish the NMOS portion from the PMOS portion, and an etching process is performed to hard mask film 220, tungsten film 218, second tungsten nitride film 216, and tungsten. Tungsten divided into an NMOS portion and a PMOS portion by removing the silicide layer 214, the first tungsten nitride layer 212, the titanium layer 210, the N-type and P-type polysilicon layers 208 and 206, and the gate insulating layer 202. The formation of the dual poly gate B is completed.

이후, 도시하지는 않았으나, 공지된 일련의 후속 공정을 차례로 진행하여 본 발명의 실시예에 따른 모스펫 소자를 제조한다. Subsequently, although not shown, a series of subsequent known processes are sequentially performed to manufacture a MOSFET device according to an exemplary embodiment of the present invention.

이상, 본 발명의 특정 실시예에 관련하여 도시하고 설명하였지만, 본 발명이 그에 한정되는 것은 아니며, 이하의 특허청구의 범위는 본 발명의 정신과 분야를 이탈하지 않는 한도 내에서 본 발명이 다양하게 개조 및 변형될 수 있다는 것을 당업계에서 통사의 지식을 가진 자가 용이하게 알 수 있다.As described above and illustrated with respect to specific embodiments of the present invention, the present invention is not limited thereto, and the following claims are variously modified without departing from the spirit and scope of the present invention. And it can be readily appreciated by those skilled in the art that it can be modified.

이상에서와 같이, 본 발명은 텅스텐 듀얼 폴리 게이트에서 폴리실리콘막과 금속계막 사이의 베리어막을 티타늄막, 제1텅스텐질화막, 텅스텐실리사이드막, 제2텅스텐질화막의 적층 구조로 구성함으로써 폴리실리콘막과 텅스텐막 간의 계면을 안정화시키고 접촉저항을 감소시키며 티타늄(Ti)에 의한 텅스텐의 결정 감소를 막아 텅스텐 게이트의 면저항 증가를 막을 수 있다. As described above, the present invention comprises a polysilicon film and tungsten by forming a barrier film between a polysilicon film and a metal-based film in a tungsten dual poly gate in a stacked structure of a titanium film, a first tungsten nitride film, a tungsten silicide film, and a second tungsten nitride film. It is possible to stabilize the interface between the films, reduce the contact resistance, and prevent the decrease of tungsten crystal due to titanium (Ti) to prevent the increase of sheet resistance of the tungsten gate.

따라서, 폴리실리콘막과 텅스텐막 간의 접촉저항 감소로 소자의 RC 지연 시간이 감소해 소자의 속도를 개선할 수 있고, 계면특성이 안정되어 게이트절연막의 신뢰성이 개선되며, 게이트 접촉면의 저항 증가를 방지하여 DRAM의 tRCD를 개선하여 텅스텐 듀얼 폴리 게이트를 가지는 반도체 소자의 속도를 개선할 수 있다. Therefore, the RC delay time of the device can be reduced by reducing the contact resistance between the polysilicon film and the tungsten film, and the device speed can be improved, and the interfacial characteristics are stabilized, thereby improving the reliability of the gate insulating film and preventing the resistance of the gate contact surface from increasing. Accordingly, the speed of a semiconductor device having a tungsten dual poly gate may be improved by improving tRCD of a DRAM.

Claims (3)

PMOS 및 NMOS 영역을 갖는 실리콘기판의 각 영역 상에 형성된 게이트절연막; A gate insulating film formed on each region of the silicon substrate having PMOS and NMOS regions; 상기 PMOS 영역의 게이트절연막 상에 형성된 P형 폴리실리콘막 및 NMOS 영역의 게이트절연막 상에 형성된 N형 폴리실리콘막; A P-type polysilicon film formed on the gate insulating film in the PMOS region and an N-type polysilicon film formed on the gate insulating film in the NMOS region; 상기 P형 폴리실리콘막 및 N형 폴리실리콘막 상에 형성되고, 티타늄막/제1텅스텐질화막/텅스텐실리사이드막/제2텅스텐질화막으로 이루어진 베리어층; A barrier layer formed on the P-type polysilicon film and the N-type polysilicon film and formed of a titanium film / first tungsten nitride film / tungsten silicide film / second tungsten nitride film; 상기 베리어층 상에 형성된 텅스텐막; 및 A tungsten film formed on the barrier layer; And 상기 텅스텐막 상에 형성된 하드마스크막;A hard mask film formed on the tungsten film; 을 포함하는 것을 특징으로 하는 텅스텐 듀얼 폴리 게이트.Tungsten dual poly gate, characterized in that it comprises a. PMOS 및 NMOS 영역을 갖는 실리콘기판 상에 게이트절연막을 형성하는 단계; Forming a gate insulating film on the silicon substrate having the PMOS and NMOS regions; 상기 PMOS 영역의 게이트절연막 상에 P형 불순물로 도핑된 P형 폴리실리콘막을 형성함과 아울러 상기 NMOS 영역의 게이트절연막 상에 N형 불순물로 도핑된 N형 폴리실리콘막을 형성하는 단계; Forming a P-type polysilicon film doped with a P-type impurity on the gate insulating film in the PMOS region and forming an N-type polysilicon film doped with N-type impurity on the gate insulating film in the NMOS region; 상기 P형 및 N형 폴리실리콘막 상에 베리어층으로서 티타늄막/제1텅스텐질화막/텅스텐실리사이드막/제2텅스텐질화막의 베리어층을 형성하는 단계; Forming a barrier layer of a titanium film / first tungsten nitride film / tungsten silicide film / second tungsten nitride film as a barrier layer on the P-type and N-type polysilicon films; 상기 티타늄막/제1텅스텐질화막/텅스텐실리사이드막/제2텅스텐질화막의 베리어층 상에 텅스텐막을 형성하는 단계; Forming a tungsten film on the barrier layer of the titanium film / first tungsten nitride film / tungsten silicide film / second tungsten nitride film; 상기 텅스텐막 상에 하드마스크막을 형성하는 단계; 및 Forming a hard mask film on the tungsten film; And 상기 하드마스크막, 텅스텐막, 티타늄막/제1텅스텐질화막/텅스텐실리사이드막/제2텅스텐질화막의 베리어층, P형 폴리실리콘막과 N형 폴리실리콘막 및 게이트절연막을 식각하는 단계; Etching the barrier layer, the P-type polysilicon layer, the N-type polysilicon layer, and the gate insulating layer of the hard mask layer, the tungsten layer, the titanium layer, the first tungsten nitride layer, the tungsten silicide layer, and the second tungsten nitride layer; 를 포함하는 것을 특징으로 하는 텅스텐 듀얼 폴리 게이트 형성방법. Tungsten dual poly gate forming method comprising a. 제 2 항에 있어서, The method of claim 2, 상기 티타늄막/제1텅스텐질화막/텅스텐실리사이드막/제2텅스텐질화막의 베리어층을 형성하는 단계 후, 수소(H2) 가스를 이용하여 어닐링하는 단계를 더 포함하는 것을 특징으로 하는 텅스텐 듀얼 폴리 게이트 형성방법. After forming the barrier layer of the titanium film / first tungsten nitride film / tungsten silicide film / second tungsten nitride film, an annealing using hydrogen (H 2 ) gas is further included. Formation method.
KR1020060106925A 2006-10-31 2006-10-31 W-dual poly gate and manufacturing method of the same KR20080039143A (en)

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