KR20080034265A - Align circuit for f/f external input signal - Google Patents

Abstract

An align circuit for external input signals of a flip flop is provided to precisely define the state of output signals when input signals supplied to a flip flop circuit are asynchronous with one another by utilizing the align circuit. An align circuit includes a detecting unit and an align unit(200). The detecting unit detects whether or not the transition time of an external input signal is in a dead zone of a flip flop circuit, generates a first detecting signal when the transition time is in the dead zone, and generates a second detecting signal when the transition time is not in the dead zone. The align unit delays the external input signal when the first detecting signal is inputted longer than when the second signal is inputted.

Description

Align circuit for flip-flop external input signal

1 is a conventional domain conversion circuit diagram.

2 and 3 are operation timing diagrams of FIG.

4 is a domain conversion circuit diagram including an alignment circuit according to an embodiment of the present invention.

FIG. 5 is a circuit diagram illustrating an alignment part of the alignment circuit of FIG. 4.

FIG. 6 is a circuit diagram illustrating a detecting unit of the alignment circuit of FIG. 4.

7 and 8 are operation timing diagrams of FIGS. 5 and 6.

* Description of the symbols for the main parts of the drawings *

110: alignment circuit 200: alignment unit

300: detecting unit

The present invention relates to an alignment circuit of an external input signal of a flip flop. More specifically, the flip-flop circuit of the flip-flop circuit is controlled so that a transition time point of an external input signal input to the flip-flop does not exist in a dead zone of the flop flop. An alignment circuit of a flip-flop external input signal for solving instability.

Generally, flip-flop circuits are used in various devices or circuits, but they are frequently used in semiconductor memory devices.

In particular, in the case of DDR SDRAM, the flip-flop circuit is used for a domain change circuit. That is, an internal clock generation circuit called a DLL is used to align the data signals DQ and DQS with the external clock signal ECLK in the read operation.

The DLL clock generated by the internal clock generation circuit is ON / OFF control is performed according to the command (CMD) condition to reduce the current consumption in the DRAM.

In general, such on / off control is performed through a domain conversion circuit using flip-flops.

1 shows a conventional domain conversion circuit.

As shown in FIG. 1, the conventional domain conversion circuit 10 includes a flip-flop 20 and logic gates 12, 14, 16, and 18.

The flip-flop 20 is a d-flip-flop and is controlled by an inverted signal of the internal clock signal pdll_pre as an external input signal dll_on. The external input signal dll_on is a DLL on / off signal generated by an external clock signal, and the internal clock signal pdll_pre is an internal clock generated by the DLL.

Here, the external input signal pdll_on and the internal clock signal pdll_pre belong to different domains, i.e., are asynchronous with each other. Unpredictable

2 and 3 illustrate the operation timing diagrams of the normal case and the glitch generated.

As shown in FIG. 2, in the normal operation of the domain conversion circuit 10, when the external input signal dll_on transitions from a low level to a high level, the output signal en of the flip-flop circuit 20 is increased. The transition time from the high level to the high level is synchronized with the transition time from the high level to the low level of the internal clock signal pdll_pre. The output signal pdll of the domain conversion circuit, which is a DLL control signal, is generated while the output signal en of the flip-flop circuit 20 maintains a high level. The DLL control signal is generated through the same process even when the external input signal dll_on transitions from the high level to the low level.

As shown in FIG. 3, when the rising time point of the external input signal dll_on meets the falling time point of the internal clock signal pdll_pre, the flip-flop circuit 20 It will be in an unstable state. In this case, the output signal en of the flip-flop circuit 20 becomes an unpredictable signal. In this case, glitches may occur in the DLL control signal pdll as shown in the display portion 24. Therefore, in the circuit using the flip-flop, it is necessary to accurately define the state of the output signal when the input signals have a polling time or a rising time in the dead zone of the flip-flop circuit.

Accordingly, it is an object of the present invention to provide an alignment circuit for a flip-flop external input signal that can overcome the above-mentioned conventional problems.

It is another object of the present invention to provide an alignment circuit for an external input signal of a flip-flop that can accurately define a state of an output signal.

It is still another object of the present invention to provide an alignment circuit for a flip-flop external input signal that can prevent or minimize glitches of output signals with respect to input signals that are asynchronous with each other.

It is still another object of the present invention to provide an alignment circuit for an external input signal of a flip flop that can improve instability of an output of a flip flop circuit.

According to an embodiment of the present invention for achieving some of the technical problems described above, an align for aligning the external input signal in a flip-flop circuit having an external input signal and an internal clock signal asynchronous to each other according to the present invention. The circuit detects whether a transition point of the external input signal exists within a dead zone of the flip-flop circuit, and if the transition point of the external input signal falls within a dead zone of the flip-flop circuit, A detecting unit generating a detecting signal and generating a second detecting signal when a transition point of the external input signal does not fall within a dead zone of the flip-flop circuit; In response to the detection signal output from the detecting unit, the external input signal is aligned, and when the first detection signal is input, the external input signal is more predetermined than when the second detection signal is input. And an alignment unit for delaying the delay further and inputting the delay to the flip-flop circuit.

The alignment unit may delay the external input signal by 1/2 clock period of the internal clock signal when the first detecting signal is input than when the second detecting signal is input. The detecting unit may include at least one phase detector circuit that compares the phases of two signals and outputs a phase detecting signal corresponding thereto.

The flip-flop circuit may be a D-flip-flop circuit, and the transition point of the external input signal may be a rising edge point or a falling edge point. The first detecting signal and the second detecting signal may have a complementary relationship with each other.

According to the above configuration, it is possible to solve the instability that may occur when the signals input to the flip-flop circuit is asynchronous with each other.

DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings, without any other intention than to provide a thorough understanding of the present invention to those skilled in the art.

4 illustrates a domain conversion circuit to which an alignment circuit is added according to an embodiment of the present invention.

The domain conversion circuit 100 includes a domain conversion unit 120 and an alignment circuit 110. The domain converter 120 includes a flip-flop 123 and logic gates 122, 124, and 126. The configuration of the domain converter 120 is the same as that of the conventional domain converter. That is, the flip-flop 20 is a d-flip-flop, which is input by the input signal dll_on_a and controlled by the inverted signal of the internal clock signal pdll_pre. The input signal dll_on_a is a DLL on / off signal using the external input signal dll_on generated by the external clock signal as an align input signal, and the internal clock signal pdll_pre is an internal clock generated by the DLL.

The alignment circuit 110 is a circuit for aligning the external input signal dll_on to solve an instability of the flip-flop 123 constituting the domain converter 120. The alignment circuit 110 prevents the external input signal dll_on from overlapping the internal clock signal pdll_pre with a transition time point, thereby solving the instability of the flip-flop 123.

5 and 6 illustrate the alignment circuit 110. The alignment circuit 110 includes an alignment unit 200 and a detecting unit 300. 5 illustrates the alignment unit 200, and FIG. 6 illustrates the detecting unit 300.

The detecting unit 300 detects whether a transition point of the external input signal dll_on exists within a dead zone of the flip-flop circuit 123, and detects a transition point of the external input signal dll_on. In case of falling within the dead zone of the flip-flop circuit 123, a first detecting signal pd180 is generated, and a transition point of the external input signal dll_on is within the dead zone of the flip-flop circuit 123. If not, the second detecting signal pd0 is generated.

The alignment unit 200 aligns the external input signal dll_on in response to the detection signals pd0 and pd180 output from the detecting unit 300, and the first detecting signal pd180 is aligned. When input, the align external input signal dll_on_a is generated by delaying the external input signal dll_on by a predetermined delay than when the second detecting signal pd0 is input. The align external input signal dll_on_a is input to the flip-flop circuit 123.

As shown in FIG. 5, the alignment unit 200 includes flip-flops 112, 114, and 116 and logic circuits 117, 118, and 119, and has a wiring structure as shown in FIG. 5. The flip-flops 112, 114, and 116 may be D-flip flops.

The alignment unit 200 is for aligning the external input signal dll_on. When the first detecting signal pd180 is input from the detecting unit 300, the alignment unit 200 may be configured to adjust the external input signal dll_on. The delay is further delayed by 1/2 the clock period of the internal clock signal pdll_pre than when the 2 detecting signal pd0 is input.

As illustrated in FIG. 5, the first clock signal pclk is a clock signal synchronized with an external clock signal, and the second clock signal pclkb is an inverted signal of the first clock signal pclk.

The operation of the alignment unit 200 will be described with reference to FIGS. 7 and 8.

As illustrated in FIG. 6, the detecting unit 300 includes phase detector circuits 332 and 342 and logic circuits 312, 314, 315, 316, 322, 323, 324, 326, 352, 354, and 356.

The detecting unit 300 includes a clock generator 310, a dead zone setting unit 320, phase detecting units 330 and 340, and a detecting signal generator 350.

The clock generator 310 generates a third clock signal pclk_rep having the same delay as the delay from the rising edge of the first clock signal pclk to the rising edge of the align external input signal dll_on_a. will be. The third clock signal pclk_rep is generated by delaying the first clock signal pclk.

The dead zone setter 320 uses two signals to set the dead zone of the flip-flop circuit 123. That is, the dead zone w is formed by using the first setting signal pdll_w1 having a predetermined delay faster than the internal clock signal pdll_pre and the second setting signal pdll_w2 having a predetermined delay slower than the internal clock signal pdll_pre. Set.

The dead zone w is set to an appropriate area. If the dead zone w is too wide, a high frequency limit may be generated. If the dead zone is too narrow, a malfunction may be caused by DLL jitter, so the range is set to an appropriate range.

 The phase detectors 330 and 340 are configured by at least one phase detector circuit 332 and 342.

The phase detecting unit 330 or 340 compares the phases of the third clock signal pclk_rep and the setting signals pdll_w1 and pdll_w2 for setting the dead zone w, and compares the phase detecting signals det1 and det2 thereof. Generate.

The detecting signal generator 350 includes inverters 352 and 356 and a NAND circuit 354 to generate the first detecting signal pd180 and the second detecting signal pd0. The first detecting signal pd180 and the second detecting signal pd0 have a complementary relationship with each other.

That is, when the rising edge of the third clock signal pclk_rep is faster than the falling edge of the first setting signal pdll_w1 or is slower than the falling edge of the second setting signal pdll_w2 (that is, the dead zone area w). The second detecting signal pd0 is high and the first detecting signal pd180 is generated at a low level.

When the rising edge point of the third clock signal pclk_rep is between the falling edge point of the first setting signal pdll_w1 and the falling edge point of the second setting signal pdll_w2 (that is, the dead zone area w). The second detecting signal pd0 is low and the first detecting signal pd180 is generated at a high level.

Hereinafter, the operation of the alignment circuit 110 will be described with reference to the timing diagrams of FIGS. 7 and 8. FIG. 7 illustrates a case in which the rising edge of the third clock signal pclk_rep is faster than the falling edge of the first setting signal pdll_w1 or slower than the falling edge of the second setting signal pdll_w2, that is, a dead zone. The operation when outside the area w is shown.

As illustrated in FIG. 7, the external clock signal ext.clk is input at a predetermined period. The first clock signal pclk synchronized with this is generated after a predetermined delay td1. The external input signal dll_on is generated by the command CMD. As the first clock signal pclk is generated, the third clock signal pclk_rep is generated by the clock generator 310. The third clock signal pclk_rep is a clock signal obtained by delaying the first clock signal pclk by a predetermined delay td2. The degree of delay has been described above.

Thereafter, the phase detecting units 330 and 340 determine whether a rising edge point of the third clock signal pclk_rep exists in the dead zone region w to generate phase detecting signals det1 and det2.

As illustrated in FIG. 7, since the rising edge point of the third clock signal pclk_rep does not exist in the dead zone region w, the second detecting signal pd0 is high and the first detecting signal ( pd180 is generated at a low level. Accordingly, the alignment external input signal dll_on_a is generated in synchronization with the rising edge of the first clock signal pclk without requiring an additional alignment operation. The align external input signal dll_on_a is generated after a predetermined delay td2 at the rising edge of the first clock signal.

FIG. 8 illustrates a case in which the rising edge point of the third clock signal pclk_rep is between the falling edge point of the first setting signal pdll_w1 and the falling edge point of the second setting signal pdll_w2, that is, a dead zone region ( The operation in the case of w) is shown.

As illustrated in FIG. 8, the external clock signal ext.clk is input at a predetermined period. The first clock signal pclk synchronized with this is generated after a predetermined delay td1. The external input signal dll_on is generated by the command CMD. As the first clock signal pclk is generated, the third clock signal pclk_rep is generated by the clock generator 310. The third clock signal pclk_rep is a clock signal obtained by delaying the first clock signal pclk by a predetermined delay td2. The degree of delay has been described above.

Thereafter, the phase detecting units 330 and 340 determine whether a rising edge point of the third clock signal pclk_rep exists in the dead zone region w to generate phase detecting signals det1 and det2.

As shown in FIG. 7, since the rising edge point of the third clock signal pclk_rep exists in the dead zone area w, the second detecting signal pd0 is low and the first detecting signal pd180 is used. ) Is generated at a high level. In this case, the align external input signal dll_on_a is generated in synchronization with the falling edge of the first clock signal pclk. That is, the rising edge of the third clock signal pclk_rep is delayed by 1/2 clock period more than the case where the rising edge of the third clock signal pclk_rep does not exist in the dead zone region w. The align external input signal dll_on_a is generated after a predetermined delay td2 at the falling edge of the first clock signal.

Accordingly, instability that may occur when signals input to the flip-flop circuit are asynchronous with each other can be eliminated.

The description of the above embodiments is merely given by way of example with reference to the drawings for a more thorough understanding of the present invention, and should not be construed as limiting the present invention. In addition, it will be apparent to those skilled in the art that various changes and modifications can be made without departing from the basic principles of the present invention. For example, it is clear that in other cases, the internal configuration of the circuit may be changed or the internal components of the circuit may be replaced with other equivalent elements.

As described above, according to the present invention, when the input signals provided to the flop-flop circuits are asynchronous with each other, an alignment circuit can be provided to accurately define the state of the output signal. In addition, it is possible to prevent or minimize the glitch of the output signal to the input signals, and to improve the instability of the output of the flip-flop circuit.

Claims (6)

An align circuit for aligning the external input signal in a flip-flop circuit having an external input signal and an internal clock signal which are asynchronous with each other: Detecting whether the transition time point of the external input signal exists within the dead zone section of the flip-flop circuit, and if the transition time point of the external input signal falls within the dead zone section of the flip-flop circuit, the first detecting signal A detecting unit for generating a second detecting signal when the transition point of the external input signal does not belong to a dead zone of the flip-flop circuit; In response to the detection signal output from the detecting unit, the external input signal is aligned, and when the first detection signal is input, the external input signal is more predetermined than when the second detection signal is input. And an alignment unit for delaying the delay further and inputting the input to the flip-flop circuit. The method of claim 1, wherein the alignment unit, And delaying the external input signal by 1/2 clock period of the internal clock signal when the first detecting signal is input than when the second detecting signal is input. The method of claim 2, And the detecting unit includes at least one phase detector circuit for comparing phases of two signals and outputting a phase detection signal corresponding thereto. The method of claim 3, And the flip-flop circuit is a D-flip flop circuit. The method of claim 4, wherein And a transition edge point of the external input signal is a rising edge point or a falling edge point. The method of claim 5, And the first detecting signal and the second detecting signal are complementary to each other.

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