KR20080030903A - Oled display apparatus and drive method thereof - Google Patents

Abstract

An OLED(Organic Light Emitting Diode) display device and a driving method thereof are provided to prevent the reduction of brightness of an OLED by adjusting a data voltage supplied to data lines. A display panel(110) includes first and second scan lines, data lines, pixels, and feedback lines. A timing controller(150) controls the supply of first and second scan pulses supplied to the first and second scan lines, and the supply of data voltages supplied to the data lines. First and second gate drivers(130,140) sequentially supply the first and second scan pulses to the first and second scan lines, respectively, under the control of the timing controller. A data driver(120) generates reference data voltages having levels in proportion to a gray scale levels of digital data, supplies the data voltages to the data lines, and compensates for the reference data voltages according to the magnitude of feedback voltages fed back through the feedback lines, under the control of the timing controller.

Description

Organic light emitting diode display device and driving method thereof

1 is a block diagram of a conventional organic light emitting diode display device.

2 is an equivalent circuit diagram of pixels constituting a conventional organic light emitting diode display.

3 is a configuration diagram of an organic light emitting diode display device according to an exemplary embodiment of the present invention.

4 is a detailed configuration diagram of the data driver of FIG. 3.

FIG. 5 is a circuit diagram of the display panel of FIG. 3 and the first and second switching units and the reset unit of FIG. 4.

6A and 6B are flowcharts illustrating a method of driving an organic light emitting diode display device according to an exemplary embodiment of the present invention.

7 is a timing diagram illustrating a driving process of an organic light emitting diode display device according to an exemplary embodiment of the present invention.

8A and 8B are equivalent circuit diagrams of a display panel and a data driver of an organic light emitting diode display device according to an exemplary embodiment of the present invention.

Explanation of symbols on the main parts of the drawings

100: organic light emitting diode display element 110: display panel

120: data driver 130: first gate driver

140: second gate driver 150: timing controller

The present invention relates to an organic light emitting diode display device, and more particularly, to an organic light emitting diode display device and a driving method thereof capable of automatically compensating a driving voltage of an organic light emitting diode according to a magnitude of a feedback voltage from pixels.

Recently, various flat panel display devices that can reduce weight and volume, which are disadvantages of cathode ray tubes, have emerged. Such flat panel displays include a liquid crystal display, a field emission display, a plasma display panel, and an electro-luminescence (hereinafter, referred to as "EL"). Display elements).

Among them, the EL display element is a self-luminous element that emits a phosphor by recombination of electrons and holes, and is classified roughly into an inorganic EL using an inorganic compound and an organic EL using an organic compound as the phosphor. Such EL display elements have many advantages such as low voltage driving, self-luminous, thin film type, wide viewing angle, fast response speed and high contrast, and are expected to be the next generation display devices.

The organic EL display element is usually composed of an electron injection layer, an electron transport layer, a light emitting layer, a hole transport layer, and a hole injection layer stacked between a cathode and an anode. In the organic EL display device, when a predetermined voltage is applied between the anode and the cathode, electrons generated from the cathode move to the light emitting layer through the electron injection layer and the electron transport layer, and holes generated from the anode are transferred to the hole injection layer and the hole transport layer. It moves to the light emitting layer through. Accordingly, the light emitting layer emits light by recombination of electrons and holes supplied from the electron transporting layer and the hole transporting layer.

The driving apparatus of an active matrix EL display element using such an organic EL display element has pixels 28 arranged in regions defined by intersections of scan lines SL and data lines DL, as shown in FIG. The EL panel 20, the scan driver 22 for driving the scan lines SL of the EL panel 20, and the data driver 24 for driving the data lines DL of the EL panel 20. And a gamma voltage generator 26 supplying a plurality of gamma voltages to the data driver 24, a timing controller 27 and pixels 28 for controlling the data driver 24 and the scan driver 22. A power supply unit 15 for supplying power to each is provided.

In the EL panel 20, pixels 28 are arranged in a matrix form. The EL panel 20 is provided with a supply pad 10 that receives the supply voltage VDD from the power supply section 15 and a base pad 12 that receives the ground voltage GND from the power supply section 15. The supply voltage VDD supplied to the supply pad 10 is supplied to the respective pixels 28. In addition, the base voltage GND supplied to the base pad 12 is also supplied to the respective pixels 28.

The scan driver 22 sequentially drives the scan lines SL by supplying scan pulses to the scan lines SL.

The gamma voltage generator 26 supplies a gamma voltage having various voltage values to the data driver 24.

The data driver 24 converts the digital data signal input from the timing controller 27 into an analog data signal using the gamma voltage from the gamma voltage generator 26. The data driver 24 supplies the analog data signal to the data lines DL every time a scan pulse is supplied.

The timing controller 27 supplies a data control signal for controlling the data driver 24 and a scan control signal for controlling the scan driver 22 using synchronization signals supplied from an external system (eg, a graphics card). Create The data control signal generated by the timing controller 27 is supplied to the data driver 24 to control the data driver 24. The scan control signal generated by the timing controller 27 is supplied to the scan driver 22 to control the scan driver 22. In addition, the timing controller 27 supplies a digital data signal supplied from an external system to the data driver 24.

When the scan pulses are supplied to the scan lines SL, the pixels 28 receive data signals from the data lines DL and generate light corresponding to the data signals.

The configuration of the pixel 28 is illustrated in detail in FIG. 2, and the configuration of the pixel 280 will be described in detail as follows.

As shown in FIG. 2, the pixel 28 drives the organic light emitting diode OLED and the organic light emitting diode OLED, which are driven and emitted by a driving current generated by the high potential power voltage VDD. And a cell driver 28-1 for the purpose. Here, in the organic light emitting diode OLED, an anode is connected to the power supply voltage VDD and a cathode is connected to the cell driver 28-1.

The cell driver 28-1 includes a thin film transistor T1 for switching and a thin film transistor for switching a data voltage supplied to the data line DL by being turned on by a scan pulse supplied to the scan line SL. Driving to drive the organic light emitting diode OLED by being turned on by the capacitor Cst for charging the data voltage supplied through the T1 and the voltage supplied from the switching thin film transistor T1 or the capacitor Cst. A thin film transistor T2.

The driving thin film transistor T2 is supplied to the drain through the organic light emitting diode OLED in a turned-on state by the data voltage supplied through the switching thin film transistor T1 or the voltage supplied from the capacitor Cst. The organic light emitting diode (OLED) is driven by passing voltage and current to ground connected to the source. Accordingly, the brightness, that is, the brightness, of the organic light emitting diode OLED is proportional to the amount of current passing through the driving thin film transistor T2 to the ground.

As described above, the driving thin film transistor T2 that adjusts the luminance of the organic light emitting diode OLED is made of amorphous silicon, which is degraded by the voltage applied to the gate, thereby increasing the threshold voltage and surrounding high temperature environment. This has the characteristic of increasing the threshold voltage. In this case, when the threshold voltage is increased, the luminance of the organic light emitting diode OLED is lowered because the amount of current passed to the ground through the driving thin film transistor T2 decreases in proportion to the increased threshold.

The present invention has been made to solve the above problems, and an object of the present invention is to provide an organic light emitting diode display device capable of automatically compensating the driving voltage of the organic light emitting diode according to the magnitude of the feedback voltage from the pixels and its It is to provide a driving method.

SUMMARY OF THE INVENTION An object of the present invention is to provide an organic light emitting diode display device and a driving method thereof, by automatically compensating a driving voltage of an organic light emitting diode reduced by deterioration of a display panel or a high temperature environment. To provide.

In order to achieve the above object, the present invention provides a plurality of first and second scan lines and a plurality of data lines, and a plurality of first and second scan lines and intersections of the plurality of data lines. A display panel in which a plurality of pixels are formed and a plurality of feedback lines connected to the plurality of pixels are formed; A timing controller for controlling the supply of first and second scan pulses supplied to the plurality of first and second scan lines, respectively, and the supply of data voltages supplied to the plurality of data lines; A first gate driver sequentially supplying the first scan pulse to the plurality of first scan lines in response to the control of the timing controller; A second gate driver sequentially supplying the second scan pulse to the plurality of second scan lines for controlling the voltage feedback from the plurality of pixels in response to the control of the timing controller; And in response to the control of the timing controller, generating a plurality of reference data voltages having a level proportional to the gradation level of the digital data supplied from the timing controller, and supplying data voltages to the plurality of data lines. And a data driver compensating for the data voltage using the reference data voltages according to the magnitude of the feedback voltage from the plurality of pixels fed back through the plurality of feedback lines.

Each of the plurality of pixels may include: a first switch element for switching on a data voltage turned on by the first scan pulse and supplied to a data line; A storage capacitor for charging the voltage supplied by the first switch element; An organic light emitting diode for emitting organic light by receiving a driving current generated by a high potential power voltage; A second switch element turned on by a voltage applied through the first switch element or a voltage supplied from the storage capacitor to drive the organic light emitting diode; And a third switch device turned on by the second scan pulse to switch the driving voltage of the organic light emitting diode to the feedback line. The third switch element is a thin film transistor having a gate connected to a second scan line, a drain connected to the second switch element and an organic light emitting diode in common, and a source connected to a feedback line.

The data driver may include: a plurality of reference data generators for generating a reference data voltage having a level proportional to a gradation level of digital data supplied from the timing controller; And supplying a data voltage to a data line connected to itself among the plurality of data lines under the control of the timing controller, and referring to a feedback voltage fed back through a feedback line connected to itself among the plurality of feedback lines. And a plurality of data compensators for differentially amplifying the reference data voltages applied thereto among the reference data voltages from the plurality of reference data generators and supplying them to the data lines.

The plurality of data compensators may include: a first switching unit for selectively switching the reference data voltage and the data voltage applied to the self according to the first and second control signals supplied from the timing controller; A second switching unit for selectively switching a feedback voltage from a pixel connected with itself and a negative feedback voltage from an output side according to the first and second control signals; A reset unit for resetting a feedback line connected to the self according to the second control signal; And a differential amplifier for differentially amplifying the voltage switched by the first switching unit and the voltage switched by the second switching unit and supplying the voltage to the data line. The first switching unit includes first and second transmission gates formed by a combination of a PMOS transistor and an NMOS transistor, wherein a common output terminal of the first and second transmission gates is a non-inverting unit of the differential amplifier. A reference data voltage from a reference data generator corresponding to one of the plurality of reference data generators is applied to an input terminal of the first transmission gate, and a data voltage is applied to an input terminal of the second transmission gate. It is characterized by. The second switching unit includes third and fourth transmission gates formed by a combination of a PMOS transistor and an NMOS transistor, wherein a common output terminal of the third and fourth transmission gates is connected to an inverting input terminal of the differential amplifier. The input terminal of the first transmission gate is connected to a feedback line, and the input terminal of the second transmission gate is connected to the output side of the differential amplifier. The reset unit includes an NMOS transistor to which a second control signal is applied to a gate, a drain is connected to a feedback line, and a source is connected to ground.

According to the present invention, a plurality of first and second scan lines and a plurality of data lines are formed, and a plurality of pixels are formed at intersections of the plurality of first and second scan lines and a plurality of data lines, And a display panel having a plurality of feedback lines connected to the plurality of pixels, wherein each of the plurality of pixels is turned on by a first scan pulse supplied to a first scan line and supplied to a data line. A first switch element for switching the switch; A storage capacitor for charging the voltage supplied by the first switch element; An organic light emitting diode for emitting organic light by receiving a driving current generated by a high potential power supply voltage; A second switch element turned on by a voltage applied through the first switch element or a voltage supplied from the storage capacitor to drive the organic light emitting diode; And a third switch device turned on by a second scan pulse supplied to a second scan line to switch the driving voltage of the organic light emitting diode to a feedback line.

The present invention provides a plurality of data compensations, in response to control of a timing controller, to supply a data voltage to a data line to which a pixel is connected, and to compensate for a data voltage according to a magnitude of a feedback voltage from the pixel fed back through a feedback line. And a data driver having parts, wherein each of the plurality of data compensators comprises: a first switching part for selectively switching a reference data voltage and a data voltage according to first and second control signals from the timing controller; A second switching unit for selectively switching the feedback voltage and the negative feedback voltage from the output side according to the first and second control signals; And a differential amplifier for differentially amplifying the voltage switched by the first switching unit and the voltage switched by the second switching unit and supplying the voltage to the data line. The present invention further includes a reset unit for resetting the feedback line according to the second control signal.

The present invention provides a method comprising: generating a first scan pulse and supplying a first scan line to which a pixel is connected; Supplying a data voltage to a data line connected to the pixel selected by the first scan pulse; Generating a second scan pulse and supplying a second scan pulse to a second scan line connected to the pixel; Generating a reference data voltage having a level proportional to a gradation level of the input digital data; Feeding back the voltage of the pixel through a feedback line while the second scan pulse is supplied; And compensating for the data voltage supplied to the data line according to the magnitude of the fed back voltage using the reference data voltage.

Hereinafter, with reference to the accompanying drawings will be described in detail a preferred embodiment of the present invention.

3 is a configuration diagram of an organic light emitting diode display device according to an exemplary embodiment of the present invention.

Referring to FIG. 3, the organic light emitting diode display device 100 of the present invention includes m data lines DL1 to DLm and n scan lines SL1-1 to SL1-n and SL2-1 to SL2-. a display panel 110 in which m x n pixels are formed and m-by-n pixels are formed at the intersections thereof, and m feedback lines FL1 to FLm connected to the pixels are formed; The data driver 120 for supplying data to the DL1 through DLm and the first gate driver 130 for sequentially supplying the first scan pulse to the pixel selection scan lines SL1-1 through SL1-n. ), A second gate driver 140 for sequentially supplying the second scan pulse to the voltage feedback scan lines SL2-1 to SL2-n, the data driver 120, and the first and second gates. A timing controller 150 is provided to control the drivers 130 and 140.

The display panel 110 is selected by the first scan pulses supplied to the pixel selection scan lines SL1-1 through SL1-n and then driven by the data voltages supplied to the data lines DL1 through DLm. A plurality of pixels that emit light, and the driving voltages of the pixels selected by the second scan pulses supplied to the voltage feedback scan lines SL2-1 to SL2-n are a plurality of feedback lines FL1 to FLm. Among them, the feedback is fed back to the data driver 120 through the corresponding feedback line. A more detailed description thereof will be described with reference to the accompanying drawings.

The data driver 120 converts the digital video data RGB into analog video data in response to the control signal DDC from the timing controller 110 and supplies the analog video data to the data lines DL1 to DLm of the display panel 110. In addition, the data voltages supplied to the data lines DL1 to DLm are compensated for according to the magnitude of the feedback voltages from the pixels of the display panel 110. The detailed configuration and operation of the data driver 120 will be described with reference to FIG. 4.

The first gate driver 130 generates a first scan pulse for pixel selection in response to the control signal GDC supplied from the timing controller 150, and converts the first scan pulse into pixel selection scan lines SL1 -1. The pixels of the display panel 90 to which the data voltage is supplied are sequentially supplied to the first through SL1-n.

In response to the feedback control signal FCS supplied from the timing controller 150, the second gate driver 140 sequentially processes the second scan pulse for the feedback control to the scan lines SL2-1 to SL2-n for the voltage feedback. Selects the pixel to feed the voltage to.

The timing controller 150 receives the digital video data RGB and supplies the digital video data RGB to the data driver 120 and uses the vertical synchronization signal Vsync and the horizontal synchronization signal Hsync that are input according to the main clock CLK. The control signals DDC and GDC are generated and supplied to the data driver 120 and the first gate driver 130. Here, the control signal DDC of the data driver 120 includes a source start pulse (GSP), a source shift clock (SSC), and a line voltage / data output control signal (Cpvp, / Cpvp). The control signal GDC of the first gate driver 130 may include a gate start pulse (GSP), a gate shift clock (GSC), and a gate output signal (GOE). ), And the like.

In addition, the timing controller 150 may include a compensation control signal CCS and an inversion compensation control signal / CCS for controlling the data driver 120 compensating for the data voltage according to the feedback voltage from the pixel. ) And a feedback control signal FCS for controlling the feedback of the voltage of the pixels constituting the display panel 110 to the second gate driver 140.

A circuit configuration of the display panel 110 and the data driver 120 constituting the organic light emitting diode display device having the above configuration and function will be described below.

4 is a detailed configuration diagram of the data driver of FIG. 3.

Referring to FIG. 4, the data driver 120 may include a decoder 121 for decoding input digital data, and data for dividing the decoded digital data into m pieces of digital data (m being two or more natural numbers). A divider 122, a latch 123 for latching the divided m digital data, and a D / A converter 124 for converting the latched m digital data into m analog data. do.

The data driver 120 generates first to mth reference data for generating an analog reference data voltage proportional to the gradation level of the digital data input to the m digital data output from the latch unit 123. In response to the control of the sections 125-1 to 125-m and the timing controller 150, the data voltage converted by the D / A converter 124 is supplied to the data line connected with the self, and connected with the self. And first to m th data compensators 126-1 to 126-m for compensating the data voltage supplied to the data line according to the magnitude of the feedback voltage fed back through the feedback line.

The decoder 121 decodes the digital data input from the timing controller 150 to make a signal system suitable for the D / A converter 124. For example, when six digital data are input from the timing controller 150, the decoder 121 selects only one digital data among the 64 digital data combining the six digital data and outputs the digital data to the data divider 122. do.

The data division unit 122 divides the digital data decoded according to the division control signals DCS1 to DCSm of the timing controller 150 into m pieces of digital data (m is a natural number of two or more), and the latch unit 123. Will output

The latch unit 123 latches m digital data divided by the divider 122 and outputs the digital data to the D / A converter 124.

The D / A converter 124 converts m digital data input through the latch unit 123 into m analog data voltages using a gamma reference voltage generated from a gamma reference voltage generator (not shown). Is output to the first to m th data compensators 126-1 to 126-m.

The first to m th reference data generating units 125-1 to 125-m generate reference data voltages proportional to the gradation level of digital data input to the m digital data output from the latch unit 123. The first to m th data compensators 126-1 to 126-m are output to the data compensator connected to the output terminal of the first to m th data compensators. Here, since the first to m th reference data generators 125-1 to 125-m and the first to m th data compensators 126-1 to 126-m are connected in a one-to-one correspondence, for example, The first reference data generator 125-1 outputs the generated reference data voltage to the first data compensator 126-1, and the m-th reference data generator 125-m outputs the generated reference data voltage to the m-th data. Output to the compensator 126-m. Meanwhile, the first to m th reference data generators 125-1 to 125-m are implemented to receive digital data output from the latch unit 123 to generate a reference data voltage, but is not limited thereto. . As another example, the first to m th reference data generators 125-1 to 125-m may be digital data decoded by the decoder 121 or digital data or D / A converters divided by the divider 122. The data voltage output from 124 may be input to generate a reference data voltage.

The first to m th data compensators 126-1 to 126-m are input terminals connected in one-to-one correspondence with one output terminal among the output terminals of the D / A converter 124, and the first to m th reference data. An input terminal connected to the output terminal of the reference data generator corresponding to the generator 125-1 to 125-m and a feedback terminal connected to one feedback line corresponding to the one of the feedback lines FL1 to FLm are provided. Have In addition, the first to m th data compensators 126-1 to 126-m have an output terminal connected to one data line corresponding to the first to m th data compensators 126-1 to 126-m. The first to m th data compensators 126-1 to 126-m having such a connection structure share the data voltage converted by the D / A converter 124 with itself in response to the control of the timing controller 150. Generation of reference data corresponding to itself among the first to m th reference data generators 125-1 to 125-m according to the magnitude of the feedback voltage fed back to the connected data line and fed back through the feedback line connected thereto. The data voltage supplied to the data line is compensated for using the reference data supplied from the unit. Here, the first to m th data compensators 126-1 to 126-m are data converted by the D / A converter 124 during the half period of the scan pulse supplied from the first gate driver 130 to the gate line. After the voltage is supplied to the data line, the data voltage supplied to the data line is compensated according to the feedback voltage or maintained at the data voltage level output from the D / A converter 124 for the remaining half period of the scan pulse.

The first to m th data compensators 126-1 to 126-m respectively correspond to the first to m th times according to the compensation control signal CCS and the inversion compensation control signal / CCS supplied from the timing controller 150. A first switching unit for selectively switching the reference data voltage from the reference data generator connected to itself among the reference data generators 125-1 to 125-m and the data voltage from the D / A converter 124 ( 126-a) and the feedback voltage from the pixel corresponding to itself among the pixels and the negative feedback voltage from the output side according to the compensation control signal CCS and the inversion compensation control signal / CCS supplied from the timing controller 150. Second switching unit 126-b for selectively switching the signal and feedback lines FL1 to FLm connected corresponding to the pixels according to the inversion compensation control signal / CCS supplied from the timing controller 150. Resets the feedback line connected to itself A reset amplifier 126-c for turning on the power amplifier, a differential amplifier 126- for differentially amplifying the voltage switched by the first switch 126-a and the voltage switched by the second switch 126-b. d).

The circuit configuration and operation of such components 126-a, 126-b, 126-c, and 126-d will be described with reference to FIG. 5.

FIG. 5 is a circuit diagram of the display panel of FIG. 3 and the first and second switching units and the reset unit of FIG. 4. However, the pixels of the display panel 110 all have the same circuit configuration and operation, and also elements 126-a and 126-b of the first to m th data compensators 126-1 to 126-m. Since 126-c and 126-d have the same circuit configuration and operation, the scan lines SL1-1 and SL2-1 and the data line DL1 among the plurality of pixels are illustrated in FIG. 5 for convenience of description. And a circuit configuration of a pixel commonly connected to the feedback line FL1 and a circuit configuration of a first data compensator 126-1 for supplying a data voltage to the pixel and compensating for the voltage.

Referring to FIG. 5, a pixel of the display panel 110 is turned on by a first scan pulse supplied to the scan line SL1-1 to switch the thin film for switching the data voltage supplied to the data line DL1. A storage capacitor Cst for charging the data voltage supplied through the transistor SW_TFT, the switch thin film transistor SW_TFT, and a driving current generated by the high potential power voltage VDD when a current path is formed in the pixel. A thin film transistor for driving an organic light emitting diode OLED, which is turned on by an organic light emitting diode OLED driven by an organic light emitting diode and a voltage supplied from a switch thin film transistor SW_TFT or a storage capacitor Cst. (DRV_TFT) and the second scan pulse supplied to the scan line SL2-1 are turned on to feed back the driving voltage of the organic light emitting diode OLED to the feedback line FL1. And a thin film transistor (FB_TFT) for feedback.

The switch thin film transistor SW_TFT has a gate connected to the scan line SL1-1, a drain connected to the data line DL1, a source connected to the storage capacitor Cst, and a gate of the driving thin film transistor DRV_TFT. Common connection to The switch thin film transistor SW_TFT is turned on when the first scan pulse output from the first gate driver 130 is supplied to the gate through the scan line SL1-1, and in this state, the data compensator 126-1. When the data voltage supplied from the N / A is supplied to the drain through the data line DL1, the data voltage is switched in the source direction to the gate of the capacitor Cst and the driving thin film transistor DRV_TFT.

One side of the storage capacitor Cst is commonly connected to the source of the switch thin film transistor SW_TFT and the gate of the driving thin film transistor DRV_TFT, and the other side thereof is connected to the ground VSS. The storage capacitor Cst is charged by the data voltage supplied through the switch thin film transistor SW_TFT, and when the voltage supply from the switch thin film transistor SW_TFT is stopped, the charging voltage is discharged to discharge the driving thin film transistor ( DRV_TFT).

In the organic light emitting diode OLED, an anode is connected to the power supply voltage VDD and a cathode is connected to the drain of the driving thin film transistor DRV_TFT. Since the organic light emitting diode OLED is formed by the connection structure, when the current path is formed by the driving thin film transistor DRV_TFT connected to the cathode, the organic light emitting diode OLED is driven by the driving current applied to the anode to emit organic light.

In the driving thin film transistor DRV_TFT, a gate is commonly connected to the source of the switching thin film transistor SW_TFT and the storage capacitor Cst, the drain is connected to the cathode of the organic light emitting diode OLED, and the source is grounded VSS. ) Is connected. The driving thin film transistor DRV_TFT is supplied to the drain through the organic light emitting diode OLED while turned on by the data voltage supplied through the switching thin film transistor SW_TFT or the voltage supplied from the storage capacitor Cst. The organic light emitting diode (OLED) is driven by passing voltage and current to ground connected to the source. Here, the amount of current passing through the driving thin film transistor DRV_TFT increases or decreases in proportion to the magnitude of the threshold voltage of the driving thin film transistor DRV_TFT, thereby determining the luminance of the organic light emitting diode OLED. That is, when the threshold voltage is increased due to deterioration of the driving thin film transistor DRV_TFT or the surrounding high temperature environment, the luminance of the organic light emitting diode OLED is decreased in proportion to the increased threshold voltage. Accordingly, the present invention compensates the magnitude of the data voltage applied to the gate of the driving thin film transistor DRV_TFT in proportion to the increased threshold voltage, thereby deteriorating the driving thin film transistor DRV_TFT or emitting light due to the surrounding high temperature environment. This prevents the luminance of the diode from being lowered.

The feedback thin film transistor FB_TFT has a gate connected to the scan line SL2-1, a drain connected to a cathode of the organic light emitting diode OLED, and a drain of the driving thin film transistor DRV_TFT, and a source fed back. It is connected to the line FL1. The feedback thin film transistor FB_TFT is turned on when the second scan pulse output from the second gate driver 130 is supplied to the gate through the scan line SL2-1, and in this state of the organic light emitting diode OLED The voltage applied to the cathode and the drain of the driving thin film transistor DRV_TFT is fed back to the feedback line FL1 connected to the first data compensator 126-1.

Meanwhile, the present invention implements a switch thin film transistor (SW_TFT), a driving thin film transistor (DRV_TFT) and a feedback thin film transistor (FB_TFT) as an N type MOS-FET, but is not limited thereto and may be implemented as a P type MOS-FET. It may be.

The first switching unit 126-a includes first and second transmission gates TRG1 and TRG2 formed by the combination of the PMOS transistor and the NMOS transistor, but includes the first and second transmission gates TRG1 and TRG2. Is connected to the non-inverting input terminal (+) of the differential amplifier 126-d, and the reference data voltage from the first reference data generator 125-1 is connected to the input terminal of the first transmission gate TRG1. Is applied, and the data voltage from the D / A converter 124 is applied to the input terminal of the second transmission gate TRG2.

In the case of the first switching unit 126-a having such a configuration, when the high level compensation control signal CCS and the low level inversion compensation control signal / CCS are supplied from the timing controller 150, The NMOS transistor of the first transmission gate TRG1 is turned on by the compensation control signal CCS, the PMOS transistor of the second transmission gate TRG2 is turned off, and the low level inversion compensation control signal / CCS is turned on. The PMOS transistor of the first transmission gate TRG1 is turned on, and the NMOS transistor of the second transmission gate TRG2 is turned off, thereby turning on the first transmission gate TRG1 and the second transmission gate TRG2. ) Is turned off. Accordingly, the reference data voltage from the first reference data generator 125-1 applied to the first transmission gate TRG1 is switched and supplied to the non-inverting input terminal (+) of the differential amplifier 120-1d. The data voltage from the D / A converter 124 applied to the second transmission gate TRG2 is cut off.

On the contrary, when the low level compensation control signal CCS and the high level inversion compensation control signal / CCS are supplied from the timing controller 150, the first transmission gate may be set by the low level compensation control signal CCS. At the same time as the NMOS transistor of TRG1 is turned off, the PMOS transistor of the second transmission gate TRG2 is turned on, and the PMOS of the first transmission gate TRG1 is turned on by the high level inversion compensation control signal / CCS. As the transistor is turned off, the NMOS transistor of the second transmission gate TRG2 is turned on, so that the first transmission gate TRG1 is turned off and the second transmission gate TRG2 is turned on. Accordingly, the D / A converter 124 applied to the second transmission gate TRG2 while the reference data voltage from the first reference data generator 125-1 applied to the first transmission gate TRG1 is blocked. The data voltage from is switched and supplied to the non-inverting input terminal (+) of the differential amplifier 120-1d.

The second switching unit 126-b includes third and fourth transmission gates TRG1 and TRG2 formed by the combination of the PMOS transistor and the NMOS transistor, but includes the third and fourth transmission gates TRG3 and TRG4. Is connected to the inverting input terminal (-) of the differential amplifier 126-d, and the input side of the first transmission gate TRG1 is connected to the feedback line FL1 and the input of the second transmission gate TRG2 is connected. The side is connected to the output side of the differential amplifier 126-d.

In the case of the second switching unit 126-b having such a configuration, when the high level compensation control signal CCS and the low level inversion compensation control signal / CCS are supplied from the timing controller 150, the high switching level is performed. The NMOS transistor of the third transmission gate TRG3 is turned on by the compensation control signal CCS, and the PMOS transistor of the fourth transmission gate TRG4 is turned off, and the low level inversion compensation control signal (/ The P-MOS transistor of the third transmission gate TRG3 is turned on by the CCS and the N-MOS transistor of the fourth transmission gate TRG4 is turned off, so that the third transmission gate TRG3 is turned on and the fourth transmission gate TRG4) is turned off. Accordingly, the feedback voltage fed back through the feedback line FL1 is switched by the third transmission gate TRG3 to be supplied to the inverting input terminal (-) of the differential amplifier 126-d and at the same time, the differential amplifier 126-d. The switching of the negative feedback voltage negatively feedback from the output side of the circuit is cut off by the fourth transmission gate TRG4.

However, when the low level compensation control signal CCS and the high level inversion compensation control signal / CCS are supplied from the timing controller 150, the third transmission gate TRG3 is applied by the low level compensation control signal CCS. At the same time, the N-MOS transistor of) is turned off and the P-MOS transistor of the fourth transmission gate TRG4 is turned on and the P-MOS transistor of the third transmission gate TRG3 is turned on by the high level inversion compensation control signal / CCS. Is turned off and the NMOS transistor of the fourth transmission gate TRG4 is turned on, so that the third transmission gate TRG3 is turned off and the fourth transmission gate TRG4 is turned on. As a result, the switching of the feedback voltage applied to the third transmission gate TRG3 is interrupted, and the negative feedback voltage negatively fed from the output side of the differential amplifier 126-d is switched by the fourth transmission gate TRG4 to perform differential operation. The inverting input terminal (-) of the amplifier 126-d is supplied.

The reset unit 126-c has a reset N for which the inversion compensation control signal / CCS from the timing controller 150 is applied to the gate, the drain is connected to the feedback line FL1, and the source is connected to ground. It consists of a MOS transistor RS_TR. In the case of the reset unit 126-c, when the low level inversion compensation control signal / CCS is applied from the timing controller 150, the reset NMOS transistor RS_TR is turned off to perform a reset function. On the contrary, when the high level inversion compensation control signal / CCS is applied from the timing controller 150, the reset NMOS transistor RS_TR is turned on to switch the voltage flowing through the feedback line FL1 connected to the drain to ground. Reset the feedback line FL1. By resetting all voltages flowing through the feedback line FL1 before detecting the feedback voltage, the present invention can more accurately adjust the driving voltage of the organic light emitting diode OLED using the feedback voltage.

In the differential amplifier 126-d, the non-inverting input terminal (+) is connected to the output side of the first switching 126-a, and the inverting input terminal (-) is connected to the output side of the second switching unit 126-b. The output terminal is connected to the data line DL1, but the output side is negative feedback to the input side of the second switching unit 126-b. The differential amplifier 126-d is a data voltage or reference switched by the first switching 126-a when a negative feedback is made between the output side and the inverting input terminal (−) through the second switching unit 126-b. The data voltage is output to the data line DL1. If the negative feedback is interrupted between the output side and the inverting input terminal (-) and the feedback voltage fed back through the feedback line FL1 is switched by the second switching unit 126-b, the differential amplifier 126-d may be used. When applied to the inverting input terminal (-), the differential amplifier 126-d is applied to the first switching 120-1a based on the feedback voltage input to the inverting input terminal (-) through the second switching unit 126-b. The differentially amplified data voltage or reference data voltage is output to the data line DL1.

The driving process of the organic light emitting diode display device of the present invention having the configuration as described above will be described in more detail with reference to a flowchart.

6A and 6B are flowcharts illustrating a method of driving an organic light emitting diode display device according to an exemplary embodiment of the present invention, and include scan lines SL1-1 and SL2-1, data lines DL1, and feedback among a plurality of pixels. A driving process of a pixel commonly connected to the line FL1 and the first data compensator 126-1 for supplying a data voltage to the pixel is illustrated.

6A and 6B, while the first data driver 126-1 is supplying a data voltage from the D / A converter 124 to a pixel connected to the data line DL1 (S501). In response to the control of the timing controller 150, the first gate driver 130 supplies the first scan pulse to the scan line SL1-1 for a T time period as shown in FIG. 7 (S502). The thin film transistor SW_TFT is turned on for the first time by a first scan pulse and switches the data voltage supplied to the data line DL1 to the gate of the storage capacitor Cst and the driving thin film transistor DRV_TFT ( S503).

At this time, the storage capacitor Cst is charged by the voltage supplied through the switch thin film transistor SW_TFT and the driving thin film transistor DRV_TFT is turned on by the voltage to drive the organic light emitting diode OLED. S504).

As described above, in the state in which the first scan pulse is supplied to the scan line SL1-1 for T time, the second gate driver (t1) corresponding to 1/2 time of T time as shown in FIG. In response to the control of the timing controller 150, the 130 supplies a low signal to the scan line SL2-1 (S505), and the timing controller 150 supplies the low level compensation control signal CCS to the first and second signals. The first and second switching units 126-a and 126-b and the reset unit 126-are supplied to the second switching units 126-a and 126-b and the high level inversion compensation control signal / CCS is supplied. c) (S506). Accordingly, the feedback thin film transistor FB_TFT is turned off for t1 hours by the low signal supplied from the second gate driver 140 to block the feedback of the driving voltage of the organic light emitting diode OLED (S507). In the state where the feedback is cut off, the reset TMOS transistor RS_TR of the reset unit 126-c is turned on by the high level inversion compensation control signal / CCS supplied from the timing controller 150 and t1. The feedback line FL1 is reset by switching the voltage flowing through the feedback line FL1 to ground for a time (S508). At this time, the first transmission of the first switching unit 126-a by the low level compensation control signal CCS and the high level inversion compensation control signal / CCS supplied from the timing controller 150 for t1 time. The gate TRG1 is turned off and the second transmission gate TRG2 is turned on to switch the data voltage to the non-inverting input terminal (+) of the differential amplifier 126-d (S509), and the second switching unit 126-b. The third transmission gate TRG3 is turned off and the fourth transmission gate TRG4 is turned on to perform negative feedback between the output side of the differential amplifier 126-d and the inverting input terminal (−) (S510).

That is, during the t1 time in FIG. 7, the timing controller 150 supplies the low level compensation control signal CCS and the high level inversion compensation control signal / CCS, thereby providing the first data driver 126-1. An equivalent circuit diagram as shown in FIG. 8A is formed therein. When such an equivalent circuit is formed, the differential amplifier 120-1d supplies the data line DL1 with the data voltage input to the non-inverting input terminal (+) by a negative feedback formed between the output side and the inverting input terminal (-). (S511). In this case, the differential amplifier 120-1d performs an output buffer function.

As shown in FIG. 7, the second gate driver 130 transmits the second scan pulse to the scan line SL2-1 in response to the control of the timing controller 150 for t2 hours after the t1 time has elapsed. In operation S512, the timing controller 150 supplies the high level compensation control signal CCS to the first and second switching units 126-a and 126-b and at the same time the low level inversion compensation control signal ( / CCS) is supplied to the first and second switching units 126-a and 126-b and the reset unit 126-c (S513). Accordingly, the feedback thin film transistor FB_TFT is turned on for t2 hours by the second scan pulse supplied from the second gate driver 140 to feed back the driving voltage of the organic light emitting diode OLED through the feedback line FL1. (S514). In the state where the voltage is fed back, the reset TMOS transistor RS_TR of the reset unit 126-c is turned off by the low level inversion compensation control signal / CCS supplied from the timing controller 150 to feed back. The reset of the line FL1 is blocked (S515). At this time, the first transmission of the first switching unit 126-a is performed by the high level compensation control signal CCS and the low level inversion compensation control signal / CCS supplied from the timing controller 150 for t2 hours. The gate TRG1 is turned on and the second transmission gate TRG2 is turned off to transfer the reference data voltage from the first reference data generator 125-1 to the non-inverting input terminal (+) of the differential amplifier 126-d. In operation S516, the third transmission gate TRG3 of the second switching unit 126-b is turned on to feed back the feedback voltage fed back through the feedback line FL1 to the inverting input terminal of the differential amplifier 120-1d (−). In addition, the fourth transmission gate TRG4 is turned off to block the negative feedback between the output side of the differential amplifier 120-1d and the inverting input terminal (-) (S517).

That is, during the t2 time in FIG. 7, the timing controller 150 supplies the high level compensation control signal CCS and the low level inversion compensation control signal / CCS to thereby provide the first data compensation unit 126-1. In FIG. 8B, the reference data voltages from the first reference data generator 125-1 and the non-inverting input terminal (+) and the inverting input terminal (-) of the differential amplifier 126-d are respectively shown in FIG. 8B. An equivalent circuit diagram to which the feedback voltage is applied is formed. When such an equivalent circuit is formed, the differential amplifier 120-1d differentially amplifies the reference data voltage input to the non-inverting input terminal (+) based on the feedback voltage input to the inverting input terminal (−) to form the data line DL1. It supplies to (S518).

As described above, when the driving voltage of the organic light emitting diode OLED is reduced because the threshold of the driving thin film transistor DRV_TFT is increased, the present invention feeds back the driving voltage and the organic light emission according to the feedback voltage. The driving voltage of the diode is automatically compensated for.

On the other hand, when the feedback thin film transistor FB_TFT is added to the pixel as in the present invention, the size of the pixel may be increased and the aperture ratio may be reduced. However, by forming a transparent electrode on the upper side and an opaque electrode on the symmetrical lower part, and forming an organic light emitting layer between the upper transparent electrode and the lower opaque electrode, the tower emits light to the transparent electrode positioned on the upper side. When the present invention is implemented with a top emission structure, even if the feedback thin film transistor FB_TFT is added in the pixel, the size and aperture ratio of the pixel are not changed.

As described above, according to the present invention, when the driving voltage of the organic light emitting diode is reduced because the threshold of the driving thin film transistor is degraded by the DC voltage or is increased by the surrounding high temperature environment, the driving voltage of the organic light emitting diode is fed back. By adjusting the data voltage supplied to the data lines according to the magnitude of the feedback voltage, the voltage supplied to the gate of the driving thin film transistor is increased in proportion to the increased threshold to automatically compensate the driving voltage of the organic light emitting diode. This prevents the luminance of the organic light emitting diode from being reduced due to deterioration of the driving thin film transistor or the surrounding high temperature environment.

Although the technical spirit of the present invention has been described in detail according to the above-described preferred embodiment, it should be noted that the above-described embodiment is for the purpose of description and not of limitation. In addition, those skilled in the art will understand that various embodiments are possible within the scope of the technical idea of the present invention.

Claims (17)

A plurality of first and second scan lines and a plurality of data lines are formed, a plurality of pixels are formed at intersections of the plurality of first and second scan lines and a plurality of data lines, and the plurality of pixels. A display panel in which a plurality of feedback lines connected to the display panels are formed; A timing controller for controlling the supply of first and second scan pulses supplied to the plurality of first and second scan lines, respectively, and the supply of data voltages supplied to the plurality of data lines; A first gate driver sequentially supplying the first scan pulse to the plurality of first scan lines in response to the control of the timing controller; A second gate driver sequentially supplying the second scan pulse to the plurality of second scan lines for controlling the voltage feedback from the plurality of pixels in response to the control of the timing controller; And In response to the control of the timing controller, a plurality of reference data voltages having a level proportional to the gradation level of the digital data supplied from the timing controller are generated, and the data voltage is supplied to the plurality of data lines. A data driver for compensating a data voltage using the reference data voltages according to a magnitude of a feedback voltage from the plurality of pixels fed back through feedback lines of An organic light emitting diode display device comprising a. The method of claim 1, The plurality of pixels are each, A first switch element for switching on a data voltage supplied to the data line by being turned on by the first scan pulse; A storage capacitor for charging the voltage supplied by the first switch element; An organic light emitting diode for emitting organic light by receiving a driving current generated by a high potential power voltage; A second switch element turned on by a voltage applied through the first switch element or a voltage supplied from the storage capacitor to drive the organic light emitting diode; And A third switch device turned on by the second scan pulse to switch the driving voltage of the organic light emitting diode to the feedback line An organic light emitting diode display device comprising a. The method of claim 2, The third switch element is an organic light emitting diode comprising a thin film transistor having a gate connected to a second scan line, a drain connected to the second switch element and an organic light emitting diode in common, and a source connected to a feedback line. Diode display element. The method of claim 1, The data driver, A plurality of reference data generators for generating a reference data voltage having a level proportional to a gradation level of the digital data supplied from the timing controller; And Under the control of the timing controller, the data voltage is supplied to a data line connected to the one of the plurality of data lines, and based on a feedback voltage fed back through the feedback line connected to the one among the plurality of feedback lines. And a plurality of data compensators for differentially amplifying the reference data voltages applied thereto among the reference data voltages from the plurality of reference data generators and supplying them to the data lines. The method of claim 4, wherein The plurality of data compensation units, respectively, A first switching unit for selectively switching the reference data voltage and the data voltage applied to the self according to the first and second control signals supplied from the timing controller; A second switching unit for selectively switching a feedback voltage from a pixel connected with itself and a negative feedback voltage from an output side according to the first and second control signals; A reset unit for resetting a feedback line connected to the self according to the second control signal; And A differential amplifier for differentially amplifying the voltage switched by the first switching unit and the voltage switched by the second switching unit to supply a data line An organic light emitting diode display device comprising a. The method of claim 5, wherein The first switching unit, A first transmission gate and a second transmission gate formed by a combination of a P-MOS transistor and an N-MOS transistor, A common output terminal of the first and second transmission gates is connected to a non-inverting input terminal of the differential amplifier, and an input terminal of the first transmission gate has a reference from a reference data generator corresponding to one of the plurality of reference data generators. And a data voltage is applied to an input terminal of the second transmission gate. The method of claim 6, The second switching unit, And third and fourth transmission gates formed by the combination of the P-MOS transistor and the N-MOS transistor, The common output terminal of the third and fourth transmission gates is connected to an inverting input terminal of the differential amplifier, the input terminal of the first transmission gate is connected to a feedback line, and the input terminal of the second transmission gate is connected to an output side of the differential amplifier. An organic light emitting diode display device, characterized in that connected. The method of claim 7, wherein The reset unit, An N-MOS transistor having a second control signal applied to a gate, a drain connected to a feedback line, and a source connected to ground An organic light emitting diode display device comprising a. A plurality of first and second scan lines and a plurality of data lines are formed, a plurality of pixels are formed at intersections of the plurality of first and second scan lines and a plurality of data lines, and the plurality of pixels. The display panel is formed with a plurality of feedback lines connected to the The plurality of pixels are each, A first switch element turned on by a first scan pulse supplied to the first scan line to switch a data voltage supplied to the data line; A storage capacitor for charging the voltage supplied by the first switch element; An organic light emitting diode for emitting organic light by receiving a driving current generated by a high potential power voltage; A second switch element turned on by a voltage applied through the first switch element or a voltage supplied from the storage capacitor to drive the organic light emitting diode; And A third switch element turned on by a second scan pulse supplied to a second scan line to switch the driving voltage of the organic light emitting diode to a feedback line An organic light emitting diode display device comprising a. The method of claim 9, The third switch element is a thin film transistor having a gate connected to the second scan line, a drain connected to the second switch element and the organic light emitting diode in common, and a source connected to the feedback line. Display element. In response to the control of the timing controller, data having a plurality of data compensators for supplying a data voltage to a data line to which a pixel is connected and compensating the data voltage according to a magnitude of a feedback voltage from the pixel fed back through a feedback line. Provided with a driving unit, The plurality of data compensation units, respectively, A first switching unit for selectively switching a reference data voltage and a data voltage according to first and second control signals from the timing controller; A second switching unit for selectively switching the feedback voltage and the negative feedback voltage from the output side according to the first and second control signals; And A differential amplifier for differentially amplifying a voltage switched by the first switching unit and a voltage switched by the second switching unit to supply the data line. An organic light emitting diode display device comprising a. The method of claim 11, The first switching unit, A first transmission gate and a second transmission gate formed by a combination of a P-MOS transistor and an N-MOS transistor, The common output terminal of the first and second transmission gates is connected to the non-inverting input terminal of the differential amplifier, the reference data voltage is applied to the input terminal of the first transmission gate, and the data voltage is applied to the input terminal of the second transmission gate. An organic light emitting diode display device, characterized in that applied. The method of claim 12, The second switching unit, And third and fourth transmission gates formed by the combination of the P-MOS transistor and the N-MOS transistor, The common output terminal of the third and fourth transmission gates is connected to an inverting input terminal of the differential amplifier, the input terminal of the first transmission gate is connected to the feedback line, and the input terminal of the second transmission gate is an output side of the differential amplifier. An organic light emitting diode display device, characterized in that connected to. The method according to any one of claims 11 to 13, A reset unit for resetting the feedback line according to the second control signal An organic light emitting diode display device further comprising. The method of claim 14, An N-MOS transistor having a second control signal applied to a gate, a drain connected to a feedback line, and a source connected to ground An organic light emitting diode display device comprising a. Generating a first scan pulse and supplying the first scan line to which the pixel is connected; Supplying a data voltage to a data line connected to the pixel selected by the first scan pulse; Generating a second scan pulse and supplying a second scan pulse to a second scan line connected to the pixel; Generating a reference data voltage having a level proportional to a gradation level of the input digital data; Feeding back the voltage of the pixel through a feedback line while the second scan pulse is supplied; And Compensating for the data voltage supplied to the data line according to the magnitude of the feedback voltage using the reference data voltage A method of driving an organic light emitting diode display device comprising a. The method of claim 16, Resetting the feedback line before the second scan pulse is supplied. A method of driving an organic light emitting diode display device further comprising.

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