KR20080029652A - Column address enable signal generation circuit - Google Patents

Abstract

A column address enable signal generation circuit is provided to have flexibility in using test operation of a semiconductor memory device. When read operation is selected, a read operation unit(120) changes generation time of a column address enable signal in a test mode according to the read operation. When write operation is selected, a write operation unit(140) changes generation time of the column address enable signal in a test mode according to the write operation. A column address enable signal driving unit(160) drives the column address enable signal in response to an output signal of the read operation unit and an output signal of the write operation unit.

Description

Column address enable signal generation circuit {COLUMN ADDRESS ENABLE SIGNAL GENERATION CIRCUIT}

1 is a circuit diagram showing in detail a column address enable signal (YAE) generation circuit according to the prior art.

FIG. 2 is a timing diagram showing the generation timing of the column address enable signal YAE in the test mode operation of the column address enable signal YAE generation circuit according to the related art shown in FIG.

3 is a circuit diagram illustrating in detail a column address enable signal (YAE) generation circuit according to an embodiment of the present invention;

4 is a timing diagram illustrating generation timing of a column address enable signal YAE in a test mode operation of the column address enable signal YAE generation circuit according to the embodiment of the present invention shown in FIG.

* Explanation of symbols for the main parts of the drawings.

100: column address enable signal (YAE) generation circuit.

120: lead operation unit.

140: light operation unit.

160: column address enable signal (YAE) driving unit.

122: read operation selection unit.

124: lead generation time reduction unit.

126: lead generation time increasing unit.

142: light generation time reduction unit.

144: light generation time increasing unit.

The present invention relates to a circuit for generating a column address enable signal (YAE) of a semiconductor memory device, and more particularly to a circuit for generating a column address enable signal (YAE) having flexibility in a test operation of a semiconductor memory device. .

DRAM has a switch structure for opening and closing between a data bus and a bit line, and is typically connected between a data bus pair and a bit line pair. Switching MOS transistors play a role.

It is connected to the gate of the switching MOS transistor and used as a control signal for controlling the connection of a data bus pair and a bit line pair. The column address enable signal is a column address enable signal. YAE).

That is, the column enable signal YAE transfers data carried on the data bus to the bit line in the write operation, or is loaded on the bit line in the read operation. It serves to transfer data to the data bus.

1 is a circuit diagram showing in detail a column address enable signal (YAE) generation circuit according to the prior art.

Referring to FIG. 1, the column address enable signal YAE generation circuit 10 according to the related art has the following components.

First, the operation selector 11 generates a column address enable signal YAE according to a read operation of the semiconductor memory device, or generates a column address enable signal YAE according to a write operation. Choose what to do.

This is because the time at which the column address enable signal YAE is generated when the read operation is performed on the cell of the semiconductor memory device is different from when the write operation is performed.

That is, when the read operation of the semiconductor memory device passes through the first delay unit DELAY1, the generation time of the column address enable signal YAE is delayed for a predetermined time.

In addition, the generation time of the column address enable signal YEA is not changed during the write operation of the semiconductor memory device.

The column address enable signal YAE generation time reduction unit 12 is a portion that reduces the generation time of the column address enable signal YAE using the first test mode TM <1>.

The reason is that when the first test mode TM <1> is disabled, the generation time of the column address enable signal YAE is delayed for a predetermined time, and the first test mode TM <1> is set to When enabled, the generation time of the column address enable signal YAE is not changed, so that the state in which the entry to the first test mode TM <1> is entered is greater than the state in which the exit is enabled. This is because the generation time of the signal YAE is reduced.

That is, when the first test mode TM <1> is enabled and enters the first test mode TM <1>, the generation time of the column address enable signal YAE is changed. Don't let that happen.

In addition, when the first test mode TM <1> is disabled and exits from the first test mode TM <1>, the first test mode TM <1> passes through the second delay unit DELAY2, thereby allowing the column address to be entered. The generation time of the enable signal YAE is delayed for a predetermined time.

The column address enable signal YAE generation time increasing unit 13 is a portion for increasing the generation time of the column address enable signal YAE using the second test mode TM <2>.

The reason is that when the second test mode TM <2> is disabled, the generation time of the column address enable signal YAE is not changed, and the second test mode TM <2> is enabled. When enabled, the generation time of the column address enable signal YAE is delayed for a predetermined time, so that the state in which the entry into the second test mode (TM <2>) enters the address rather than the exit state is performed. This is because the generation time of the enable signal YAE is increased.

That is, when the second test mode TM <2> is enabled and enters the second test mode TM <2>, the second test mode TM <2> enters the column address by passing through the third delay unit DELAY3. The generation time of the enable signal YAE is increased for a predetermined time.

In addition, when the second test mode TM <2> is disabled and exits from the second test mode TM <2>, the generation time of the column address enable signal YAE is changed. I never do that.

The column address enable signal YAE driving unit 14 is a portion for driving and outputting the column address enable signal YAE.

FIG. 2 is a timing diagram illustrating generation timing of a column address enable signal YAE in a test mode operation of the column address enable signal YAE generation circuit according to the related art illustrated in FIG. 1.

Referring to FIG. 2, the column address enable signal in the test mode TM <1> and TM <2> of the column address enable signal YAE generation circuit 10 according to the related art shown in FIG. 1 is operated. The generation timing of (YAE) can be seen.

First, when the first test mode TM <1> is enabled, the generation time of the column address enable signal YAE is reduced in the read operation and the write operation of the semiconductor memory device. It can be seen that.

In addition, when the second test mode TM <2> is enabled, the generation time of the column address enable signal YAE is increased in the read operation and the write operation of the semiconductor memory device. It can be seen that.

However, as described above, when the first test mode TM <1> is entered, the generation time of the column address enable signal YAE during the write operation of the semiconductor memory device decreases, thereby reducing tWR ( Write recovery time is improved.

In addition, when the first test mode TM <1> is entered, the generation time of the column address enable signal YAE is reduced during a read operation of the semiconductor memory device, thereby access time from column tAA. The time characteristic of the address is improved.

However, when the first test mode TM <1> is entered, it is involved in the generation time of the column address enable signal YAE in the write operation and the read operation of the semiconductor memory device. The time characteristic of tRCD (RAS to CAS Delay) becomes worse.

As described above, when the second test mode TM <2> is entered, the generation time of the column address enable signal YAE increases during a read operation of the semiconductor memory device, thereby increasing tAA ( Access time from column address) gets worse.

In addition, when the second test mode TM <2> is entered, the generation time of the column address enable signal YAE increases during a write operation of the semiconductor memory device, thereby writing a write recovery time (tWR). The time characteristic of becomes worse.

However, when the second test mode TM <2> is entered, the second test mode TM <2> is involved in the generation time of the column address enable signal YAE in the write and read operations of the semiconductor memory device. The time characteristic of tRCD (RAS to CAS Delay) is improved.

However, the generation circuit of the column address enable signal YAE according to the related art is the column address regardless of the read operation or the write operation of the semiconductor memory device in the first test mode TM <1>. The time characteristic of reducing the generation time of the enable signal YAE is reduced.

Similarly, the generation circuit of the column address enable signal YAE according to the related art is a column address regardless of a read operation or a write operation of the semiconductor memory device in the second test mode TM <2>. The time characteristic of increasing the generation time of the enable signal YAE is increased.

The following problem occurs due to the time characteristic of the column address enable signal (YAE) generation circuit according to the related art described above.

Even when the write recovery time (tWR) time characteristic of the semiconductor memory device is degraded, it may be necessary to delay the generation time of the column address enable signal YAE.

Therefore, when the first test mode TM <1> is enabled, the time characteristic of the write recovery time (tWR) deteriorates during write operation of the semiconductor memory device as intended, but it does not matter. A problem arises in that the time characteristic of an access time from column address (tAA) is also deteriorated due to a read operation of a semiconductor device.

Similarly, even when the generation time of the column address enable signal YAE according to the read operation of the semiconductor memory device must be changed through the test modes TM <1> and TM <2>, write is performed. There arises a structural problem that the generation time of the column address enable signal YAE varies at the same time according to the operation.

That is, the column address enable signal YAE generation circuit according to the related art has a problem of low flexibility in using the test modes TM <1> and TM <2>.

The present invention has been proposed to solve the above problems of the prior art, and provides a circuit for generating a column address enable signal (YAE) having flexibility in using a test operation of a semiconductor memory device. There is this.

According to an aspect of the present invention for achieving the above technical problem, a read operation of varying the generation time of the column address enable signal in a plurality of test modes according to the read operation during the read operation selected in response to the operation selection signal Way; Write operation means for varying a generation time of the column address enable signal in a plurality of test modes according to the write operation during a write operation selected in response to an operation selection signal; And a column address enable signal driving means for driving the column address enable signal in response to an output signal of the read operation means and an output signal of the write operation means.

Hereinafter, with reference to the accompanying drawings will be described a preferred embodiment of the present invention. However, the present invention is not limited to the embodiments disclosed below, but may be configured in various different forms, only the present embodiments to make the disclosure of the present invention complete and to those skilled in the art the scope of the invention It is provided for complete information.

3 is a circuit diagram showing in detail a column address enable signal (YAE) generation circuit according to an embodiment of the present invention.

Referring to FIG. 3, the column address enable signal (YAE) generation circuit 100 according to the embodiment of the present invention has the following structure.

First, when the read operation of the semiconductor memory device is selected, the read operation unit 120 may perform the column address enable signal in the test modes TM <1> and TM <2> according to the selected read operation. Change the generation time of (YAE).

Here, the read operation unit 120 selects the read operation in response to the operation selection signal WTL_RDH, receives the read command RD, and synchronizes with the clock signal CLK to read operation signal RD_ACT. The read operation selector 122 outputting the read operation time and the read generation time for controlling to generate the column address enable signal YAE faster in response to the read operation signal RD_ACT in the read test mode TM <1> are reduced. The read generation time increasing unit controlling to generate the column address enable signal YAE more slowly in response to an output signal of the read generation time reduction unit 122 in the readout mode 124 and the read test mode TM <2>. 126.

In addition, even if the positions of the lead generation time reducing unit 124 and the lead generation time increasing unit 126 are changed in the above-described lead operation unit 120, the overall operation of the read operation unit 120 may not be affected.

That is, the read operation signal RD_ACT is input from the read generation time increasing unit 126 to control an increase in the generation time of the column address enable signal YAE according to the read operation, and the read generation time increasing unit The output operation of the read operation unit 120 may be controlled by reducing the generation time of the column address enable signal YAE according to the read operation. It does not affect the overall operation.

3, the read operation unit 120 may be divided into two parts as follows.

First, the read operation selector selects the read operation in response to the operation selection signal WTL_RDH, receives the read command RD, and outputs the read operation signal as the read operation signal RD_ACT in synchronization with the clock signal CLK. 122) and a read generation time reduction unit 124 controlling to generate the column address enable signal YAE faster in response to the read operation signal RD_ACT in the read test mode TM <1>. 1 lead moving part.

Second, a read operation selector for selecting a read operation in response to the operation selection signal WTL_RDH, receiving a read command RD and synchronizing with the clock signal CLK to output the read operation signal RD_ACT. 122) and a read generation time increasing unit 126 controlling to generate the column address enable signal YAE more slowly in response to the output signal of the read operation signal RD_ACT in the read test mode TM <2>. Second lead operation unit comprising a.

As described above, even if the read operation unit 120 shown in FIG. 3 is divided into two parts, the overall operation of the read operation unit 120 is not affected.

Among the components of the read operation unit 120, the read operation selection unit 122 receives the read command RD as one input, receives the clock signal CLK through this input, and receives the operation selection signal WTL_RDH. ) Is input to the NAND gate NAND1 for inputting and outputting three inputs, the delay unit DELAY1 for delaying the output signal of the NAND gate NAND1 for a predetermined time, and the output signal of the delay unit DELAY1 is read and read. An inverter INV1 output as the operation signal RD_ACT is provided.

In addition, the lead generation time reduction unit 124 of the components of the read operation unit 120 receives a signal inverting the phase of the read test mode signal TM <1> as one input, and the read operation signal RD_ACT ) Is a first NAND gate NAND2 that receives and outputs this input and a read test mode signal TM <1> as one input, and receives and outputs the read operation signal RD_ACT through this input. 2 NAND gate NAND3, a delay unit DELAY2 for outputting a delayed output signal of the first NAND gate NAND2 by a predetermined time, and an output signal of the delay unit DELAY2 are input as one input, and the second NAND And a third NAND gate NAND4 that receives an output signal of the gate NAND3 through the input and outputs the same.

In addition, the operation of the lead generation time reducing unit 124 is as follows.

When the read operation is activated, the read operation signal RD_ACT has a logic level of logic 'high'.

When the read test mode signal TM <1> is enabled and becomes logic 'high', the output signal of the first NAND gate NAND2 has a logic level of logic 'high'. The output signal of the second NAND gate NAND3 has a logic level of logic 'low'.

At this time, the third NAND gate NAND4 receives the output signal of the second NAND gate NAND3 and does not wait for the output signal of the first NAND gate NAND2 to be input through the delay unit DELAY2. Outputs a high signal.

When the read test mode signal TM <1> is disabled to become logic 'low', the output signal of the first NAND gate NAND2 has a logic level of logic 'low'. The output signal of the second NAND3 has a logic level of logic 'high'.

At this time, the third NAND gate NAND4 receives the output signal of the second NAND gate NAND3, waits for the output signal of the first NAND gate NAND2 to be input through the delay unit DELAY2, and then generates a logic 'high'. Outputs a high signal.

That is, the read generation time reducer 124 outputs the output signal of the read operation selector 122 as it is during entry of the read test mode TM <1>, and then read test mode TM <2>. At the time of escape, the output signal of the read operation selector 122 is delayed and output.

In addition, the lead generation time increasing unit 126 of the components of the read operation unit 120 receives a signal inverting the phase of the read test mode signal TM <2> as one input and read operation signal RD_ACT. ) Is a first NAND gate NAND5 that receives and outputs this input and a read test mode signal TM <2> as one input, and receives and outputs a read operation signal RD_ACT through this input. 2 NAND gate NAND6, a delay unit DELAY3 for delaying the output signal of the second NAND gate NAND6 for a predetermined time, and an output signal of the first NAND gate NAND5 are input as one input and delayed. And a third NAND gate NAND7 configured to receive the output signal of the negative DELAY3 through the input and output the same.

In addition, the operation of the lead generation time increasing unit 126 is as follows.

When the read operation is activated, the read operation signal RD_ACT has a logic level of logic 'high'.

When the read test mode signal TM <2> is enabled and becomes logic 'high', the output signal of the first NAND gate NAND5 has a logic level of logic 'high'. The output signal of the second NAND gate NAND6 has a logic level of logic 'low'.

At this time, the third NAND gate NAND7 receives the output signal of the first NAND gate NAND5, waits for the output signal of the second NAND gate NAND6 to be input through the delay unit DELAY3, and then logic 'high'. Outputs a high signal.

When the read test mode signal TM <2> is disabled and becomes logic 'low', the output signal of the first NAND gate NAND5 has a logic level of logic 'low'. The output signal of the second NAND gate NAND6 has a logic level of logic 'high'.

At this time, the third NAND gate NAND7 receives the output signal of the first NAND gate NAND5 and does not wait for the output signal of the second NAND gate NAND6 to be input through the delay unit DELAY2. Outputs a high signal.

That is, the read generation time increasing unit 126 delays the output signal of the read generation time decreasing unit 124 for a predetermined time and enters the read test mode TM when the read test mode TM <2> is entered. <2>) At the time of exit, the output signal of the lead generation time reduction unit 124 is output as it is.

When the write operation WRITE of the semiconductor memory device is selected, the write operation unit 140 enables the column address in the test modes TM <3> and TM <4> according to the selected write WRITE operation. The generation time of the signal YAE is varied.

Here, the write operation unit 140 selects the write operation in response to the operation selection signal WTL_RDH, receives the write command WT, and synchronizes the clock operation CLK with the write operation signal WD_ACT. The write operation selector 142 outputting the output signal and the write generation time for controlling to generate the column address enable signal YaE faster in response to the write operation signal WD_ACT in the write test mode TM <3>. And a write generation time increaser 146 which controls to generate the column address enable signal YaE more slowly in response to the write operation signal WD_ACT in the write test mode TM <4>. do.

In addition, even if the positions of the light generation time reduction unit 144 and the light generation time increasing unit 146 are changed in the above-described light operation unit 140, the overall operation of the light operation unit 140 is not affected.

That is, the write operation signal WD_ACT is input from the write generation time increasing unit 146 to control an increase in the generation time of the column address enable signal YAE according to the write operation, and the write generation time increasing unit The output operation of the write operation unit 140 may be controlled by reducing the generation time of the column address enable signal YAE according to the write operation. It does not affect the overall operation.

3, the write operation unit 140 may be divided into two parts as follows.

First, a write operation selector for selecting a write operation in response to the operation selection signal WTL_RDH, receiving a write command WD, and synchronizing with the clock signal CLK to output the write operation signal WD_ACT. 142, and a write generation time reduction unit 144 controlling to generate the column address enable signal YaE faster in response to the write operation signal WD_ACT in the write test mode TM <3>. 1 light operation unit.

Second, the write operation selector for selecting the write operation WRITE in response to the operation selection signal WTL_RDH, receiving the write command WD and synchronizing with the clock signal CLK to output the write operation signal WD_ACT. 142 and a write generation time increasing unit 146 controlling to generate the column address enable signal YAE more slowly in response to the output signal of the write operation signal WD_ACT in the write test mode TM <4>. Second light operation unit comprising.

As described above, even if the light operation unit 140 shown in FIG. 3 is divided into two parts, the overall operation of the light operation unit 140 is not affected.

Among the components of the write operation unit 140, the write operation selecting unit 142 receives the write command WT as one input, receives the clock signal CLK as this input, and receives the operation selection signal ( And a NAND gate NAND8 for receiving and outputting WTL_RDH as three inputs, and an inverter INV5 for receiving and outputting an output signal of the NAND gate NAND8.

In addition, the light generation time reduction unit 144 of the components of the write operation unit 140 receives a signal inverting the phase of the write test mode signal TM <3> as one input and writes the write operation signal WD_ACT. ) Is a first NAND gate NAND9 for receiving and outputting this input and a write test mode signal TM <3> as one input, and a write operation signal WD_ACT is input and outputted as this input. 2NAND gate NAND10, a delay unit DELAY4 for outputting a delayed output signal of the first NAND gate NAND9 by a predetermined time, and an output signal of the delay unit DELAY4 are input as one input, and the second NAND And a third NAND gate NAND11 that receives the output signal of the gate NAND10 as the input and outputs the same.

In addition, the operation of the light generation time reducer 144 is as follows.

When the write operation is activated, the write operation signal WD_ACT has a logic level of logic 'high'.

When the write test mode signal TM <3> is enabled and becomes logic 'high', the output signal of the first NAND gate NAND9 has a logic level of logic 'high'. The output signal of the second NAND gate NAND10 has a logic level of logic 'low'.

At this time, the third NAND gate NAND11 receives the output signal of the second NAND gate NAND10 and does not wait for the output signal of the first NAND gate NAND9 to be input through the delay unit DELAY4. Outputs a high signal.

When the write test mode signal TM <3> is disabled to become logic 'low', the output signal of the first NAND gate NAND9 resets the logic level of logic 'low'. In addition, the output signal of the second NAND gate NAND10 has a logic level of logic 'high'.

At this time, the third NAND gate NAND11 receives the output signal of the second NAND gate NAND10 and waits for the output signal of the first NAND gate NAND9 to be input through the delay unit DELAY4, and then logic 'high'. Outputs a high signal.

That is, the write generation time reducer 144 outputs the output signal of the write operation selector 142 as it is when entering the write test mode TM <3>, and writes the write test mode TM <3>. When exiting, the output signal of the write operation selection unit 142 is delayed for a predetermined time and output.

In addition, the light generation time increasing unit 146 of the components of the write operation unit 140 receives a signal inverting the phase of the write test mode signal TM <4> as one input and writes the write operation signal WD_ACT. ) Is a first NAND gate (NAND12) for receiving and outputting this input and a write test mode signal (TM <4>) as one input, and a write operation signal (WD_ACT) for receiving and outputting this input. The NAND13, the delay unit DELAY5 for delaying the output signal of the second NAND13 for a predetermined time, and the output signal of the first NAND gate NAND12 are input as one input and are delayed. And a third NAND gate NAND14 which receives the output signal of the negative DELAY5 through this input and outputs the same.

In addition, the operation of the light generation time increasing unit 146 is as follows.

When the write operation is activated, the write operation signal WD_ACT has a logic level of logic 'high'.

When the write test mode signal TM <4> is enabled and becomes logic 'high', the output signal of the first NAND gate NAND12 has a logic level of logic 'high'. The output signal of the second NAND gate NAND13 has a logic level of logic 'low'.

At this time, the third NAND gate NAND14 receives the output signal of the first NAND gate NAND12, waits for the output signal of the second NAND gate NAND13 to be input through the delay unit DELAY5, and then logic 'high'. Outputs a high signal.

When the write test mode signal TM <4> is disabled to become logic 'low', the output signal of the first NAND gate NAND12 has a logic level of logic 'low'. The output signal of the second NAND gate NAND13 has a logic level of logic 'High'.

At this time, the third NAND gate NAND14 receives the output signal of the first NAND gate NAND12 and does not wait for the output signal of the second NAND gate NAND13 to be input through the delay unit DELAY4. Outputs a high signal.

That is, the light generation time increasing unit 146 delays the output signal of the light generation time reducing unit 144 for a predetermined time and enters the light test mode TM when the light test mode TM <4> is entered. <4>) The output signal of the light generation time reducer 144 is output as it is during exit.

The column address enable signal driving unit 160 drives the column address enable signal YAE in response to the output signal of the read operation unit 120 and the output signal of the write operation unit 140.

Here, the column address enable signal driving unit 160 receives an output signal of the read operation unit 120 as one input and a NAND gate that receives an output signal of the write operation unit 140 as this input and outputs the input signal. NAND15 and an inverter INV8 for receiving the output signal of the NAND gate NAND15 and driving the same as the column address enable signal YAE.

FIG. 4 is a timing diagram illustrating generation timing of the column address enable signal YAE in the test mode operation of the column address enable signal YAE generation circuit according to the embodiment of FIG. 3.

Referring to FIG. 4, the test modes TM <1>, TM <2>, TM <3>, of the column address enable signal YAE generation circuit 100 according to the embodiment of the present invention shown in FIG. It is possible to know the generation timing of the column address enable signal YAE during the TM <4>) operation.

First, when the first read test mode TM <1> is enabled, the generation time of the column address enable signal YAE is reduced in the read operation of the semiconductor memory device.

In addition, when the second read test mode TM <2> is enabled, the generation time of the column address enable signal YAE may be increased in the read operation of the semiconductor memory device.

In addition, when the first write test mode TM <3> is enabled, the generation time of the column address enable signal YAE may be reduced in the write operation of the semiconductor memory device.

In addition, when the second write test mode TM <4> is enabled, the generation time of the column address enable signal YAE in the write operation of the semiconductor memory device is increased.

As described above, when the embodiment of the present invention is applied, the read operation of the semiconductor memory device according to each test mode TM <1>, TM <2>, TM <3>, and TM <4> is performed. And the generation time of the column address enable signal YAE according to the write operation may be independently tested.

That is, in each of the read test modes TM <1> and TM <2>, the generation time of the column address enable signal YAE according to the read operation of the semiconductor memory device may be recorded in the write of the semiconductor memory device. The independent control is possible regardless of the generation time of the column address enable signal YAE according to the operation.

Similarly, in each of the write test modes TM <3> and TM <4>, the generation time of the column address enable signal YAE according to the write operation of the semiconductor memory device is read out of the semiconductor memory device. The independent control is possible regardless of the generation time of the column address enable signal YAE according to the operation.

The present invention described above is not limited to the above-described embodiments and the accompanying drawings, and various substitutions, modifications, and changes are possible in the art without departing from the technical spirit of the present invention. It will be apparent to those of ordinary skill.

For example, the logic gate and the transistor illustrated in the above-described embodiment should be implemented differently in position and type depending on the polarity of the input signal.

The present invention described above is a column according to the read operation and the write operation of the semiconductor memory device according to each test mode TM <1>, TM <2>, TM <3>, TM <4>. The generation time of the address enable signal YAE can be tested independently.

Claims (16)

Read operation means for changing a generation time of a column address enable signal in a test mode according to the read operation when a read operation is selected; Write operation means for changing a generation time of the column address enable signal in a test mode according to the write operation, when a write operation is selected; And Column address enable signal driving means for driving the column address enable signal in response to an output signal of the read operation means and an output signal of the write operation means; Semiconductor memory device comprising a. The method of claim 1, The read operation means, A read operation selector which selects the read operation in response to an operation selection signal, receives a read command, and outputs the read command as a read operation signal in synchronization with a clock signal; And A read generation time reducer configured to generate the column address enable signal faster in response to the read operation signal in a read test mode. A semiconductor memory device comprising a. The method of claim 1, The read operation means, A read operation selector which selects the read operation in response to an operation selection signal, receives a read command, and outputs the read command as a read operation signal in synchronization with a clock signal; And A read generation time increasing unit controlling to generate the column address enable signal more slowly in response to the read operation signal in a read test mode. A semiconductor memory device comprising a. The method according to claim 2 or 3, The read operation selector, A NAND gate configured to receive the read command as one input, receive the clock signal as this input, and receive and output the operation selection signal as three inputs; A delay unit configured to delay and output the output signal of the NAND gate for a predetermined time; And An inverter that receives an output signal of the delay unit and outputs the read signal as the read operation signal And a semiconductor memory device. The method of claim 2, The lead generation time reduction unit, And outputting the read operation signal as it is when entering the read test mode and delaying the read operation signal for a predetermined time when outputting the read test mode. The method of claim 5, The lead generation time reduction unit, A first NAND gate that receives a signal inverting the phase of the read test mode signal as one input and receives the read operation signal through the input; A second NAND gate receiving the read test mode signal as one input and receiving the read operation signal as the input; A delay unit configured to delay and output the output signal of the first NAND gate for a predetermined time; And A third NAND gate that receives an output signal of the delay unit as an input and receives an output signal of the second NAND gate as an input; And a semiconductor memory device. The method of claim 3, The lead generation time increasing unit, And outputting the read operation signal by delaying the read operation signal for a predetermined time when entering the read test mode, and outputting the read operation signal as it is when exiting the read test mode. The method of claim 7, wherein The lead generation time increasing unit, A first NAND gate that receives a signal inverting the phase of the read test mode signal as one input and receives the read operation signal through the input; A second NAND gate receiving the read test mode signal as one input and receiving the read operation signal as the input; A delay unit configured to delay and output the output signal of the second NAND gate for a predetermined time; And A third NAND gate that receives an output signal of the first NAND gate as one input and receives an output signal of the delay unit as an input; And a semiconductor memory device. The method of claim 1, The light operation means, A write operation selector which selects the write operation in response to an operation selection signal, receives a write command, and outputs a write command in synchronization with a clock signal; And A write generation time reduction unit controlling to generate the column address enable signal faster in response to the write operation signal in a write test mode. A semiconductor memory device comprising a. The method of claim 1, The light operation means, A write operation selector which selects the write operation in response to an operation selection signal, receives a write command, and outputs a write command in synchronization with a clock signal; And The write generation time increasing unit controlling to generate the column address enable signal more slowly in response to the write operation signal in the write test mode. A semiconductor memory device comprising a. The method of claim 9 or 10, The write operation selection unit, A first inverter configured to receive and output a phase of the operation selection signal; A NAND gate that receives the write command as one input, receives a clock signal as the input, and receives and outputs the output signal of the first inverter as three inputs; And A second inverter which receives an output signal of the NAND gate and outputs it as a write operation signal And a semiconductor memory device. The method of claim 9, The light generation time reduction unit, And outputting the write operation signal as it is when entering the write test mode and delaying the write operation signal for a predetermined time when outputting the write test mode. The method of claim 12, The light generation time reduction unit, A first NAND gate configured to receive a signal inverting the phase of the write test mode signal as one input, and receive and output the write operation signal to the input; A second NAND gate receiving the write test mode signal as one input and receiving the write operation signal as the input; A delay unit configured to delay and output the output signal of the first NAND gate for a predetermined time; And A third NAND gate that receives an output signal of the delay unit as an input and receives an output signal of the second NAND gate as an input; And a semiconductor memory device. The method of claim 10, The light generation time increasing unit, And outputting the write operation signal by a delay for a predetermined time when entering the write test mode, and outputting the write operation signal as it is when exiting the write test mode. The method of claim 14, The light generation time increasing unit, A first NAND gate configured to receive a signal inverting the phase of the write test mode signal as one input, and receive and output the write operation signal to the input; A second NAND gate receiving the write test mode signal as one input and receiving the write operation signal as the input; A delay unit configured to delay and output the output signal of the second NAND gate for a predetermined time; And A third NAND gate that receives an output signal of the first NAND gate as one input and receives an output signal of the delay unit as an input; And a semiconductor memory device. The method of claim 1, The column address enable signal driving unit, A NAND gate which receives an output signal of the read operation means as one input and receives an output signal of the write operation means as the input; And An inverter receiving the output signal of the NAND gate and driving the same as the column address enable signal And a semiconductor memory device.

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