KR20080023441A - System in package embeded flip chip - Google Patents

System in package embeded flip chip Download PDF

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Publication number
KR20080023441A
KR20080023441A KR1020060087345A KR20060087345A KR20080023441A KR 20080023441 A KR20080023441 A KR 20080023441A KR 1020060087345 A KR1020060087345 A KR 1020060087345A KR 20060087345 A KR20060087345 A KR 20060087345A KR 20080023441 A KR20080023441 A KR 20080023441A
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South Korea
Prior art keywords
circuit board
printed circuit
package
flip chip
cavity
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KR1020060087345A
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Korean (ko)
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임주행
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엘지이노텍 주식회사
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Priority to KR1020060087345A priority Critical patent/KR20080023441A/en
Publication of KR20080023441A publication Critical patent/KR20080023441A/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/12—Mountings, e.g. non-detachable insulating substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32135—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/32145—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73253—Bump and layer connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/1515—Shape
    • H01L2924/15153—Shape the die mounting substrate comprising a recess for hosting the device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

Abstract

A system in package having a flip chip therein is provided to make the package slim and compact with high integration, by lowering the height of a semiconductor chip mounted in a printed circuit board as high as a depth of a cavity, and mounting more flip chips with different sizes between conductive balls on a lower side of the printed circuit board. A system in package having a plurality of circuit patterns on upper and lower sides, comprises a cavity(34), a flip chip(40), a bare die(50), and a molding part(60). The cavity having predetermined width and depth, is formed on an upper center portion of a printed circuit board(30) that has a plurality of circuit patterns(32) on upper and lower sides, and a plurality of conductive balls welded to a lower side of the circuit pattern. The flip chip is mounted within the cavity by a solder bump. The bare die is layered onto the flip chip. The molding part molds the entire upper surface of the printed circuit board. The printed circuit board comprises more flip chips(70) between the conductive balls that are welded on the lower side.

Description

플립칩 내장 시스템 인 패키지{SYSTEM IN PACKAGE EMBEDED FLIP CHIP}Flip-chip Embedded System-in-Package {SYSTEM IN PACKAGE EMBEDED FLIP CHIP}

도 1A는 종래 플립칩 내장 시스템 인 패키지의 단면도Figure 1A is a cross-sectional view of a package in a conventional flip chip embedded system

도 1B는 종래 베어 다이 적층 멀티 칩 패키지의 단면도1B is a cross-sectional view of a conventional bare die stacked multichip package.

도 2는 본 발명의 일 실시예에 따른 플립칩 내장 시스템 인 패키지의 단면도2 is a cross-sectional view of a flip chip embedded system in a package according to an embodiment of the present invention.

도 3은 도 2의 다른 실시예에 따른 플립칩 내장 시스템 인 패키지의 단면도3 is a cross-sectional view of a flip chip embedded system in a package according to another exemplary embodiment of FIG. 2.

*도면의 주요부분에 대한 부호의 설명** Description of the symbols for the main parts of the drawings *

30; 인쇄회로기판 31; 비어홀30; A printed circuit board 31; Beer Hall

32; 회로패턴 33; 도전성 볼32; Circuit pattern 33; Conductive ball

34; 캐비티 40; 플립칩34; Cavity 40; Flip chip

50; 베어 다이 60; 몰딩부50; Bare die 60; Molding part

70; 다른 플립칩70; Other flip chip

본 발명은 플립칩 내장 시스템 인 패키지에 관한 것이다.The present invention relates to a package that is a flip chip embedded system.

최근 점점 소형화 및 다기능화되고, 복잡성이 더 해가는 이동 기기 및 고밀도 고집적 복합제품(MCM; 멀티 칩 모듈 / SIP; 시스템 인 패키키)이 개발되면서 초 소형 크기의 패키지 모듈화 추세로 가고 있는 실정이다.Recently, as the miniaturization, multi-functionality, and complexity of mobile devices and high-density high-density complex products (MCM; multi-chip module / SIP; system-in-package) have been developed, there is a trend toward package modularization of ultra-small size.

통상 상기 시스템 인 패키지는 능동소자인 트랜지스터 또는 집적회로와 같은 반도체 칩과, 수동소자인 저항, 콘덴서 또는 인덕터 등이 하나의 패키지에 형성된 것을 말한다.In general, the system-in-package refers to a semiconductor chip such as a transistor or an integrated circuit, which is an active element, and a resistor, a capacitor, or an inductor, which is a passive element, in one package.

이러한 시스템 인 패키지는 상기 수동소자에 의해 능동소자인 반도체칩의 신호 처리 속도를 높이거나, 필터링(Filtering)기능 등을 수행하여 그 패키지의 전기적 성능을 향상시킬 뿐만 아니라 상기 시스템 인 패키지가 하나의 독립된 전기적 기능을 수행하도록 하는 역할을 한다.Such a system-in-package improves the electrical performance of the package by increasing the signal processing speed or filtering function of the semiconductor chip, which is an active element, by the passive element, and the system-in-package is one independent. It serves to perform electrical functions.

상기와 같은 시스템 인 패키지는 상기 수동소자 및 능동소자가 동일한 인쇄회로기판에 위치됨으로써, 인쇄회로기판에 실장 밀도를 증대시키는 장점이 있어 최근 많이 제조되고 있다.Such a system-in-package has been manufactured in recent years because the passive element and the active element are located on the same printed circuit board, thereby increasing the mounting density on the printed circuit board.

이러한 종래의 시스템 인 패키지는 상,하면에 다수의 회로패턴(11)이 형성되고 상기 회로패턴(11)의 하면에 다수의 도전성 볼(12)이 융착된 인쇄회로기판(10)의 상면 중앙에는 도 1A에 도시한 바와 같이, 하면에 리드없이 솔더범프(Solder Bump)로 실장되는 플립칩(FLIP CHIP; 20)과 베어 다이(BARE DIE)(21)가 적층되거나, 도 1B에 도시한 바와 같이, 베어 다이(BARE DIE)(21)가 적층되며, 상기 베어 다이(21)와 상기 인쇄회로기판(10)의 회로패턴(11)은 도전성 와이어(14)에 의해 접속한 후, 상기 인쇄회로기판(10)의 상면 전체를 외부환경으로부터 보호하기 위하여 몰딩재로 몰딩부(13)를 형성하게 된다. In the conventional system-in-package, a plurality of circuit patterns 11 are formed on upper and lower surfaces, and a plurality of conductive balls 12 are fused to the lower surface of the circuit pattern 11 at the center of the upper surface of the printed circuit board 10. As shown in FIG. 1A, a flip chip 20 and a bare die 21, which are mounted as solder bumps without a lead on the bottom surface, are stacked, or as shown in FIG. 1B. The bare die 21 is stacked, and the bare die 21 and the circuit pattern 11 of the printed circuit board 10 are connected by a conductive wire 14, and then the printed circuit board is formed. In order to protect the entire upper surface of the (10) from the external environment, the molding part 13 is formed of a molding material.

그러나 상기 시스템 인 패키지는 인쇄회로기판(10)의 두께가 한정되어 있고, 상기 인쇄회로기판(10)의 상면에 반도체 칩들이 그대로 적층되어 실장되게 되므로 두께를 소형화하는 데 한계가 있고, 또한 상기 인쇄회로기판(10)과 적층된 반도체 칩간에 도전성 와이어(14)를 그대로 노출되지 않도록 전체적으로 본딩되게 되므로 패키지의 전체적인 두께가 커지게 되어 슬림화 및 초소형화하는데 문제점이 있다.However, the system-in-package has a limited thickness of the printed circuit board 10, and the semiconductor chips are stacked and mounted on the upper surface of the printed circuit board 10 as it is. Since the conductive wire 14 is entirely bonded between the circuit board 10 and the stacked semiconductor chips as it is, the overall thickness of the package is increased, resulting in a problem of slimming and miniaturization.

본 발명은 시스템 인 패키지를 슬림화 및 초소형한다.The present invention makes the system in a package slim and compact.

본 발명의 플립칩 내장 시스템 인 패키지는 상,하면에 다수의 회로패턴이 형성되고 상기 회로패턴의 하면에 다수의 도전성 볼이 융착된 인쇄회로기판의 상면 중앙에 소정의 폭과 깊이로 형성되는 캐비티와; 상기 캐비티 내에는 솔더범프로 실장되는 플립칩과 상기 플립칩의 상부에 적층되는 베어 다이 및 인쇄회로기판의 상부 전체를 몰딩하는 몰딩부를 포함한다.. In the flip-chip embedded system package of the present invention, a plurality of circuit patterns are formed on upper and lower surfaces, and a cavity is formed at a predetermined width and depth in the center of an upper surface of a printed circuit board in which a plurality of conductive balls are fused to the lower surface of the circuit pattern. Wow; The cavity includes a flip chip mounted with solder bumps, a bare die stacked on top of the flip chip, and a molding part for molding the entire upper part of the printed circuit board.

또한 본 발명은 상기 인쇄회로기판의 하면에 융착된 다수의 도전성 볼과 볼사이에 플립칩을 몰딩재로 장착한 것을 더 포함한다.In addition, the present invention further includes mounting a flip chip as a molding material between the plurality of conductive balls and the balls fused to the lower surface of the printed circuit board.

이하 첨부되는 도면에 의거 본 발명을 상세히 설명하면 다음과 같다.Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.

도 2는 본 발명의 일 실시예에 따른 플립칩 내장 시스템 인 패키지의 단면도이다.2 is a cross-sectional view of a package containing a flip chip system according to an embodiment of the present invention.

인쇄회로기판(30)은 판상의 상,하 표면에 수지층이 형성되고, 상기 수지층이 형성된 판상에는 다수의 비어홀(31)과 회로패턴(32)이 형성되며, 상기 회로패턴(32)의 하면에 다수의 도전성 볼(33)이 융착되게 된다. The printed circuit board 30 has resin layers formed on upper and lower surfaces of a plate, and a plurality of via holes 31 and circuit patterns 32 are formed on the plate on which the resin layers are formed. A plurality of conductive balls 33 are fused to the lower surface.

상기 인쇄회로기판(30)의 상면 중앙에는 소정의 폭과 깊이의 캐비티(34)를 형성하게 되고, 상기 캐비티(34)의 깊이는 표면의 수지층으로부터 판상까지 형성되게 된다.A cavity 34 having a predetermined width and depth is formed in the center of the upper surface of the printed circuit board 30, and the depth of the cavity 34 is formed from the resin layer on the surface to the plate shape.

상기 플립칩(40)은 하면에 리드선 없이 솔더범프(41)가 융착된 반도체 칩으로, 상기 플립칩(40)은 솔더범프(41)로 인쇄회로기판(30)의 상면 중앙에 형성된 캐비티(34)에 장착되게 된다.The flip chip 40 is a semiconductor chip in which a solder bump 41 is fused without a lead wire on a lower surface thereof, and the flip chip 40 is a solder bump 41 formed in a center of an upper surface of a printed circuit board 30. ) Will be mounted.

상기 베어 다이(50)는 패키징 직전에 웨이퍼에서 잘라낸 집적회로 칩으로, 상기 플립칩(40)의 상부에 장착되고, 상기 베어 다이(50)는 상기 인쇄회로기판(30)의 회로패턴(32)과 도전성 와이어(35)로 본딩되게 된다.The bare die 50 is an integrated circuit chip cut from a wafer immediately before packaging, and is mounted on the flip chip 40, and the bare die 50 is a circuit pattern 32 of the printed circuit board 30. And the conductive wire 35 to be bonded.

상기 몰딩부(60)는 상기 인쇄회로기판(30)에 실장된 플립칩(40)과 상기 플립칩(40)에 적층되는 베어 다이(50) 및 도전성 와이어(35)를 외부의 영향으로부터 보호하기 위한 몰딩재로 전체적으로 몰딩하게 된다.The molding part 60 protects the flip chip 40 mounted on the printed circuit board 30 and the bare die 50 and the conductive wire 35 stacked on the flip chip 40 from external influences. The molding material for the molding as a whole.

도 3은 도 2의 다른 실시예에 따른 플립칩 내장 시스템 인 패키지의 단면도로서, 도 2의 구성과 전체적으로 동일하고, 다만, 도 3에서는 인쇄회로기판(30)의 하면에 융착되는 도전성 볼(33)들 사이에 솔더범프(71)를 갖는 다른 플립칩(70)을 몰딩재로 장착하게 된다.3 is a cross-sectional view of a flip chip embedded system in a package according to another exemplary embodiment of FIG. 2, which is generally the same as the configuration of FIG. 2, except that in FIG. 3, the conductive balls 33 are fused to the bottom surface of the printed circuit board 30. The other flip chip 70 having the solder bumps 71 between them is mounted as a molding material.

상기 다른 플립칩(70)은 인쇄회로기판(30)의 도전성 볼(33)의 크기보다 작은 크기의 칩으로 장착하게 된다.The other flip chip 70 is mounted as a chip having a size smaller than that of the conductive balls 33 of the printed circuit board 30.

상기와 같이 구성된 본 발명은 상,하면에 다수의 회로패턴(32)이 형성되고, 하면에 다수의 도전성 볼(33)이 융착되며, 상면 중앙에 소정의 폭과 깊이로 캐비 티(34)가 형성된 인쇄회로기판(30)에 솔더범프(41)가 융착된 플립칩(40)을 실장하게 되는데, 이때 상기 플립칩(40)은 인쇄회로기판(30)의 캐비티(34) 내에 실장하고 상기 플립칩(40)의 상부에 베어 다이(50)를 적층한 후, 상기 베어 다이(50)와 인쇄회로기판(30)의 회로패턴(32)과 도전성 와이어(35)로 본딩하고, 이어서 상기 인쇄회로기판(30)의 상부 전체를 몰딩재로 몰딩하여 패키지를 형성하게 된다.In the present invention configured as described above, a plurality of circuit patterns 32 are formed on upper and lower surfaces, a plurality of conductive balls 33 are fused on the lower surface, and the cavity 34 is formed at a predetermined width and depth at the center of the upper surface. The flip chip 40 in which the solder bumps 41 are fused to the printed circuit board 30 is mounted. In this case, the flip chip 40 is mounted in the cavity 34 of the printed circuit board 30. After stacking the bare die 50 on top of the chip 40, the bare die 50 is bonded with the circuit pattern 32 and the conductive wire 35 of the printed circuit board 30, and then the printed circuit. The entire upper portion of the substrate 30 is molded with a molding material to form a package.

또한 본 발명은 상기 캐비티(34) 내에 플립칩(40)이 실장한 인쇄회로기판(30)의 하면에 다수의 도전성 볼(33)과 볼(33) 사이에 다른 크기의 플립칩(70)을 몰딩재로 장착하여 패키지를 형성하게 된다.In addition, the present invention provides a flip chip 70 having a different size between the plurality of conductive balls 33 and the balls 33 on the lower surface of the printed circuit board 30 in which the flip chips 40 are mounted in the cavity 34. It is mounted with a molding material to form a package.

그러므로 본 발명은 인쇄회로기판(30)의 상면에 형성된 캐비티(34)의 깊이만큼 인쇄회로기판(30)에 실장되는 반도체 칩의 높이를 낮출 수 있고, 또한 상기 인쇄회로기판(30)의 하면 도전성 볼(33)들 사이에 다른 크기의 플립칩(70)을 장착함으로써, 패키지 전체를 슬림화 및 고집적화할 수 있게 되는 것이다.Therefore, the present invention can lower the height of the semiconductor chip mounted on the printed circuit board 30 by the depth of the cavity 34 formed on the upper surface of the printed circuit board 30, and also the lower surface conductivity of the printed circuit board 30 By mounting flip chips 70 of different sizes between the balls 33, the entire package can be made slim and highly integrated.

이상에서 설명한 바와 같이 본 발명은 상부에 반도체 칩이 실장되는 인쇄회로기판에 캐비티를 형성하여 상기 캐비티의 내에 플립 칩을 실장하고, 또한 상기 인쇄회로기판의 하면에 다른 크기의 플립칩을 몰딩하여 장착하도록 함으로써, 패키지의 전체 높이를 캐비티 만큼 낮출 수 있어 슬림화 및 고집적화를 할 수 있는 효과를 제공하게 되는 것이다.As described above, the present invention forms a cavity in a printed circuit board on which a semiconductor chip is mounted, and mounts a flip chip in the cavity, and molds and mounts flip chips of different sizes on the bottom surface of the printed circuit board. By doing so, the overall height of the package can be lowered by the cavity, thereby providing the effect of slimming and high integration.

Claims (3)

상,하면에 다수의 회로패턴이 형성되고 상기 회로패턴의 하면에 다수의 도전성 볼이 융착된 인쇄회로기판의 상면 중앙에 소정의 폭과 깊이로 형성되는 캐비티와; 상기 캐비티 내에 솔더범프로 실장되는 플립칩과, 상기 플립칩의 상부에 적층되는 베어 다이; 및 상기 인쇄회로기판의 상면 전체를 몰딩하는 몰딩부를 포함하는 플립칩 내장 시스템 인 패키지.A cavity formed on a center of an upper surface of a printed circuit board having a plurality of circuit patterns formed on upper and lower surfaces and a plurality of conductive balls fused to a lower surface of the circuit pattern; A flip chip mounted as solder bumps in the cavity, and a bare die stacked on top of the flip chip; And a molding part molding the entire upper surface of the printed circuit board. 제 1 항에 있어서, 상기 캐비티는 상기 인쇄회로기판 표면의 수지층으로부터 판상까지 형성한 것을 특징으로 하는 플립칩 내장 시스템 인 패키지.The package of claim 1, wherein the cavity is formed from a resin layer on a surface of the printed circuit board to a plate shape. 제 1 항에 있어서, 상기 인쇄회로기판은 하면에 융착된 도전성 볼들 사이에 플립칩을 더 포함하는 것을 특징으로 하는 플립칩 내장 시스템 인 패키지.The package of claim 1, wherein the printed circuit board further comprises a flip chip between conductive balls fused to a bottom surface thereof.
KR1020060087345A 2006-09-11 2006-09-11 System in package embeded flip chip KR20080023441A (en)

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