KR20080023194A - Clock recovery method for tdm service using packet switched networks - Google Patents

Abstract

A clock restoration method in a TDM(Time Division Multiplexing) service using a packet network is provided to solve signal loss and delay due to a timing distortion state which can occur when TDM signals are transmitted through a packet network. In a method for restoring an output clock through clock information received from a network, the local DCOs(Digitally Controlled Oscillators)(421-423) of a clock restorer(420) are driven on the basis of on clock information generated from a result of the packet synchronization of a CET(Circuit Emulation Timing) algorithm. As a result, a TDM output clock is obtained. A reference clock source(410), which provides exquisite clocks from the external, is connected to a TDM clock input port(TDM_CLKIP), and the reference clock source(410) is used in differential mode only.

Description

Clock recovery method in time division multiplexing service via packet network {Clock recovery method for TDM service using Packet Switched Networks}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a clock recovery method in a time division multiplexing service via a packet network. The present invention relates to a clock recovery method in a time division multiplexing service through a packet network so that timing distortion of a time division multiplexing signal due to various surroundings can be recovered at a packet side.

As is generally known, the traditional time division multiplexing (TDM) based circuit switched service is a service in which all connection circuits between transmitting and receiving terminals pass through the time division multiplexing circuit to guarantee a certain level of quality of service between ends. On the other hand, the time-division multiplexing dedicated line cost is very expensive compared to the packet network, and additional costs and additional scalability due to capacity expansion are lacking.

In order to solve the above problems, a method of restoring after transmitting a TDM signal through a packet network has recently been actively progressed, and a method and a standard for this have been proposed. However, in the process of transmitting / receiving TDM signals through the packet network, timing distortion such as jitter or delay may occur due to the surrounding environment, electrical signals, or aging of each equipment, which may cause continuous errors. There is no way to solve this problem.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned problems, and is a method for time-division multiplexed signals reproduced through a packet network regardless of the time-division multiplexed circuit connection type that can be variously provided in a system that reproduces time-division multiplexed signals through a packet network. It is an object of the present invention to provide a clock recovery method in a time division multiplexing service through a packet switching network that can recover timing distortion caused by a surrounding environment at a packet side.

A clock recovery method in a time division multiplexing service through a packet network according to the present invention for achieving the above object is a form in a process of converting a packet from a packet to a TDM frame in a system for transmitting a TDM signal through a packet network regardless of a circuit connection. And adaptive and differential in the atypical mode.

In the configuration of the present invention as described above, in the adaptive mode of the structured and unstructured mode, the picket is stored in the queue, and the time stamp and payload information of the stored packet, the packet arrival rate, the filling degree of the packet reception buffer, the packet reception statistics, The clock may be restored by the parameter information, but the clock may be restored by the buffer fill level and the arrival time.

Meanwhile, the technique according to the present invention uses the control packet in the differential mode of the atypical mode to pass time information from the master node to the slave node, such as the master TDM clock counter and the common clock timestamp, such as the common clock counter and the slave RDM clock counter. The clock may be restored by an out-of-band method of restoring the clock by maintaining the relation of the clock.

The technique of a clock recovery method in a time division multiplexing service via a packet network according to the present invention is directed to a signal loss and delay that may occur due to timing distortion that may occur when a TDM signal is transmitted through a packet network in FIG. You can solve the problem.

In addition, the technique according to the present invention proposes a clock recovery method for a variety of circuit connections by applying the present invention regardless of the service signal loss and delay that can occur due to timing distortion that can occur when transmitting the TDM signal over the packet network Can solve the problem.

In addition, the technology according to the present invention can be applied to various communication protocols such as MPLS, Pseudo-Wire as well as IP in the process of reproducing the TDM signal in the packet network and its effect Is the same as above.

Furthermore, through the present invention, the service quality that can be provided in the TDM network can be provided through the IP network, thereby greatly contributing to future network communication, as well as the expansion and cost reduction by using the TDM network through the Ethernet network. Can contribute significantly.

Hereinafter, a clock recovery method in a time division multiplexing service via a packet network according to an embodiment of the present invention will be described in detail with reference to the accompanying drawings.

1 is a TDMoP (TDM over Packet) network configuration for applying a clock recovery method according to the present invention, which shows a private dedicated line connected between two public switched telephone networks, which are representative circuit switching networks, by an emulated link through a packet network.

As shown in FIG. 1, the TDM data of the public switched telephone network is transmitted through the packet network after being encapsulated (encapsulated) through the TDM assembler 110 inside the gateway interposed between the public switched telephone network and the packet network. It is delivered to the TDM granulator 120. At this time, the TDM service frequency (f _service ) must be reproduced correctly by the packet output unit 120. The discrepancy in frequency means that the packetized data is reproduced slower or faster than the inherent clock, and the data accumulated in the queue 121 of the packet output unit 120 may overflow or fall, causing data loss. This means that the packet transmission is interrupted and the connection between the two ends is lost.

Therefore, if there is no clock distribution means from the outside, the clock recovery method of the present invention is required. The clock recovery is performed through the clock recoverer 122 of the packet output unit 120. The recovered TDM service frequency F _service is transmitted through the TDM configurator, that is, the framer 124. 130, and then the end device 130 extracts the clock through the internal clock extractor 132 to provide a TDM frequency clock (F _service ) and transmits data through the TDM processor 131.

2 is a block diagram of a clock recovery system for processing a TDM over packet (TDMoP) according to the present invention.

As shown in FIG. 2, the clock recovery system configuration of the present invention is largely a circuit emulation service over a packet network, that is, a circuit emulation service over Packet Switched Network (CESoPSN) that converts line data into packet data or packet data into line data. 200), Digital Phase Locked Loop (DPLL) (210) for digitally correcting the phase shift of the system clock, Framer (211) for TDM frame processing, LIU (Line Interface Unit) for TDM flow control Unit, 212), TCXO (Temperature Compensated Crystal Oscillator) to reduce frequency shift due to external temperature, CPLD (Complex Programmable Logic Device, 220) for circuit control as a programmable complex logic device. And the external clock 222 and the LIU 223 for external clock processing when using an external clock.

In the above-described configuration, the packet transmitted through the packet tunnel of the packet network is converted into a TDM signal through the CESoPSN 200, and the framer 211 is used for processing the frame in the structured mode and the unstructured mode. In normalization mode, DPLL 210 is used to give clock information. The framer 211 and TXCO 221 represent the reference clock source in the differential mode and are controlled by the CPLD 220. This figure is a block diagram of the exchange relationship between the packet network and the circuit network, and is intended to help the understanding of CESoPSN before describing the clock recovery.

3 is an overall flowchart of a clock recovery method according to the present invention.

As shown in FIG. 3, when the TDM signal and the clock are transmitted (S100), the previous shaping or atypical mode is distinguished (S110). If the shaping mode, the loopback determination step (S120) is performed. Proceed to the internal, external or adaptive selection step (S130). Next, when the decision result in the loopback determination step (S120) is atypical and in the loopback mode, the received clock is directly transmitted to the clock output (S122), and when it is not the loopback mode, the differential and adaptive mode determination steps (S124) are performed again. Proceed to As a result of the determination in step S124, the differential mode is transmitted to the reference clock (S128), and the TDM system refers to the clock (S135). When the determination result in step S124 is the adaptive mode, the clock is restored by the DCO (Digitally Controlled Oscillator) through a Circuit Emulation Timing (CET) algorithm (S126).

On the other hand, when the determination result in step S130 is the internal mode signal transmitted through the framer (S140) is output to the TDM system as a reference clock source through the DCO, and in the external mode is transmitted through the framer (S150) The clock and the frame are transferred to the TDM system as reference clocks and reference frames, respectively (S152). Finally, in the case of the adaptive, the input clock is transferred to the DCO through the framer (S131), and the DCO extracts the clock through the CET algorithm (S133). Then, the extracted clock is transferred to the TDM clock input (S133), and is corrected to the reference clock through the DPLL (S134) and then transferred to the TDM system (S135).

Hereinafter, the clock recovery configuration in each mode will be described in detail.

4 is a diagram illustrating a clock recovery method in the loopback clock mode according to the present invention, and illustrates a clock recovery method in the TDM LIUs 300, 301, and 302 in the atypical and loopback clock mode.

As shown in FIG. 4, each LIU 300, 301, and 302 includes a clock input RCLK, a clock output TCLK, a data input RDATA, and a data output RDATA to configure the TDM assembly 110. do. Reference numeral 310 denotes a clock recoverer. At this time, the polarity is set to (+) and the DCO bypasses and does not affect clock recovery. The polarity of the input and output clocks can be changed, and the clock frequency must match the speed of the data.

5 is a view for explaining a clock recovery method in the non-standard adaptive clock mode according to the present invention.

As shown in FIG. 5, as an adaptive clock recovery method using an RTP, an adaptive ALTP (buffer fill level) is recovered by extracting clock information from an ALTP time stamp of an incoming packet. The adaptive average rate is a method of restoring the TDM clock with the recovered clock by extracting the clock recovery information from the average of incoming packets. Rate is used in the same way as the higher adaptive average rate or for specific applications such as wireless backhauling.

In other words, as a method of restoring the output clock using the clock information received from the network, the local DCO 421 to the clock recoverer 420 to the clock information generated from the result of synchronizing the packet through the Citi algorithm. Drive 423 and result in a TDM output clock. The reference clock source 410, which provides a sophisticated clock from the outside, is connected to the TDM clock input (TDM_CLKiP) and is used only in differential mode. In FIG. 5, reference numerals 400, 410, and 420 denote LIUs, respectively.

On the other hand, adaptive clock recovery as described above does not use a common clock and is more affected by packet network characteristics. There are two methods for adaptive clock recovery using buffer fill level and arrival time. Adaptive clock recovery should only be restored to the time information obtained from the packet that the master TDM clock arrived.

6 is a basic conceptual diagram of an adaptive clock recovery method according to the present invention, and shows a basic concept of adaptive clock recovery.

As shown in FIG. 6, the jitter buffer fill level method is a simple concept. The master node inserts an ALTP sequence number into every time-division multiplexed data packet to be sent to the slave node and is used by the slave for re-order, out of order, and lost packet discovery. The clock recovery mechanism of the slave node monitors the buffer fill level and operates based on that information. If the buffer starts above the intermediate fill level, this indicates that the slave TDM clock frequency is slower than the master TDM clock frequency and the slave TDM clock frequency should be increased.

Buffer fill level Act Fill level Medium fill level Fill level 90 100 110 none 95 105 115 Increasing Slave TDM Clock Frequency 95 100 105 none 90 95 105 Slave TDM Clock Frequency Reduction 95 100 110 none

Table 1 above shows an example of a slave node with an intermediate value of 100 packets in the buffer range of 0 to 200 packets. The second column in Table 1 above is the average fill level, which shows the average fill level of the jitter buffer. The minimum fill level represents the lowest fill level of the buffer for the same time, and the maximum fill level represents the highest fill level for the same period. Subtracting the minimum fill level from the maximum fill level provides a change in packet delay in the packet network.

The first column in Table 1 above shows that the host processor reads the node's average buffer fill level as 100 packets, which is the median of the jitter buffer. The minimum fill level is 90 packets and the maximum fill level is 110 packets. The packet delay variation of the packet network is approximately 20 packets. No action takes place at this time. The second column shows the slave buffer starting with fill and you can see that the slave clock frequency has increased. The third column shows that the buffer fill level is medium and no action has taken place. The fourth column indicates that the buffer is below the requested level and the slave TDM clock frequency has decreased. The fifth column is the requested buffer fill level and no action has taken place.

On the other hand, the arrival time method for adaptive clock recovery, which is more complex than the buffer fill level, is similar to PLL. In other words, when the arrival time clock recovery is configured, the master node inserts an ALTP timestamp and a sequence number into the header of every TDM data packet. The ALTP time stamp specifically counts the number of bits in the TDM packet and increments it to the same value for all packets. Slave nodes that receive time information in the form of ALTP timestamps sample their TDM clock counters. Both values of the master TDM clock counter and the slave TDM clock counter are used by the clock recovery mechanism to calculate the slave TDM clock frequency.

Timestamp on Packet Arrival Act Master timestamp Slave counter Difference 256 256 0 none 512 509 -3 Increasing Slave TDM Clock Frequency 768 769 +1 Slave TDM Clock Frequency Reduction 1024 1024 0 none

Table 2 above shows an example in which an E1 circuit is packetized and sent to a slave node. One frame or 256 bits of 32 channels are included in the packet, and the ALTP timestamp is used to transfer time information about the master TDM clock to the slave node.

The master timestamp of the first row in Table 2 as described above shows the ALTP timestamp value inserted into the TDM data packet. As programmed, the timestamp is incremented by 256 for each packet. The slave counter shows the counter value of the slave node when the slave node receives a packet from the master node. The first column shows that the slave TDM clock counter is 256 when the first packet arrives from the master node. There is no action because the TDM counters of the master and slave are the same. The second column shows that when the second packet arrives from the master node, the slave TDM clock counter is 509 and three clock cycles are delayed. If so, increase the slave clock frequency. The third column shows that the slave TDM clock counter is 769 when the third packet arrives from the master node. The slave TDM clock frequency should be reduced. The fourth column is the slave TDM clock counter expected when the fourth packet arrives at the slave node and no action is taken.

On the other hand, the out of band differential clock recovery method uses a control packet to pass time information from the master node to the slave node so that the master time division TDM clock counter and the common clock, such as the common clock counter and the slave TDM clock counter, are used. Maintain the relationship of timestamps.

The master node samples the master clock counter at regular intervals of the common clock, and the master node host processor reads the sampled master TDM clock value from the master node and puts this value in the ALTP timestamp of the control packet to the slave node. Send timing information. The control packet received from the slave node contains an RTP sequence number to ensure that it is processed in the correct order, and the slave node samples the slave TDM clock counter at regular intervals of the common clock. The slave node host processor reads a sampled slave time division multiplexed clock value from the slave node and the slave host processor generates a table to compare the master TDM clock counter value received from the master node with the slave clock counter value.

Master information Slave information Act Master TDM Clock Counter (Packet) Common Clock Timestamp Slave TDM Clock Counter Common clock counter 256 1000 255 1000 Increasing Slave TDM Clock Frequency 511 2000 511 2000 none 768 3000 768 3000 none 1022 4000 1024 4000 Slave TDM Clock Frequency Reduction

Table 3 above is an example of a particular table that may be generated by the host processor by implementing a clock recovery mechanism. In Table 3 above, the first column shows the master nodes recorded as 256, 511, 768, and 1022 when the common clock period is 1000 clocks, and the third column shows the slave nodes recorded as 255, 511, 768, and 1024.

On the other hand, the first row of data indicated that the slave clock was slower than the master clock using the CET algorithm when the period of the common clock was 1000 clocks, and the slave TDM clock frequency was increased. In the second and third rows, the master and slave TDM clocks each have the same number of elapsed clock periods, and no change occurs. The fourth row shows that when the slave TDM clock period is 4000, it has more clock cycles than the master TDM clock has and the slave TDM clock frequency is reduced.

The upper clock recovery mechanism is an illustrative example, where the actual control packets are sent at a rate per second rather than TDM frames and the slave TDM frequency is updated less than once per frame.

In the above-described configuration, the packet is stored in the queue (reference numeral 121 of FIG. 1) in the adaptive mode of the structured and unstructured mode to store the time stamp and payload information of the stored packet, the packet arrival rate, the filling degree of the packet reception buffer, and the packet. The clock is stored by the buffer fill level and the arrival time in the process of restoring the clock in the clock recoverer (refer to reference numeral 122 of FIG. 1) with the reception statistics and the parameter information.

7 is a view for explaining a clock recovery method in the external clock mode according to the present invention.

In this mode, as shown in FIG. 7, the clock received through the external clock port is supplied to the clock CLK and the frame pulse FRM of the framers 510 and 520 in a manner of synchronizing with reference to the external clock. The clock is supplied to the clock input reference unit TDM_CLKI_REF and the frame input reference unit TDM_FRMI_REF of the clock recoverer 520 to synchronize the clocks. In normal mode, the DPLL operates, so the DPLL must be enabled. In the drawings, reference numerals 500 and 501 denote LIUs.

8 is a view for explaining a clock recovery method in the internal clock mode of the shaping according to the present invention.

As shown in Fig. 8, in this mode, the TDM clock operates as a reference source clock. The operation is as follows. That is, the data RDATA received from the respective LIUs 600 and 601 is transferred to the TDM standard input TDM_STI of the clock restorer 620 through the framers 610 and 611 and the LIUs 600 and 601. The clock RCLK received from the VRC is transmitted to the DPLL 622 through the TDM clock receiver TDM_CLKI through the framers 610 and 611. Next, the reference clock TDM_CLKO_REF and the frame pulse TDM_FRMO_REF generated through the DPLL 622 are output to the external device. In the drawing, reference numeral 621 denotes an integrator.

9 is a view for explaining a clock recovery method in the standard adaptive clock mode according to the present invention.

As shown in Figure 9, this mode also has three adaptive methods as described above and the content is the same. When the adaptive method is determined, the clock recovered from the packet network by the Citi algorithm is transferred to the TDM clock input through the TDM output clock, and then integrated to the integrator 724 and then to the DPLL 725 to transmit the reference clock (TDM_CLKO_REF). And frame pulses (TDM_FRMO_REF) are sent to external devices.

In the drawings, reference numerals 700 and 701 denote LIUs, 710 and 711 denote framers, and 721 to 723 denote DCOs.

The clock recovery method in the time division multiplexing service through the packet network of the present invention is not limited to the above-described embodiments, and various modifications can be made within the range allowed by the technical idea of the present invention.

1 is a configuration diagram of a TDMoP (TDM over Packet) network for applying a clock recovery method according to the present invention.

2 is a block diagram of a clock recovery system for processing TDM over Packet (TDMoP) according to the present invention.

3 is an overall flowchart of a clock recovery method according to the present invention;

4 is a diagram for explaining a clock recovery method in a loopback clock mode according to the present invention;

5 is a diagram for explaining a clock recovery method in an amorphous adaptive clock mode according to the present invention;

6 is a basic conceptual diagram of an adaptive clock recovery method according to the present invention.

7 is a view for explaining a clock recovery method in the external clock mode according to the present invention.

8 is a view for explaining a clock recovery method in the internal clock mode according to the present invention.

9 is a view for explaining a clock recovery method in the standard adaptive clock mode according to the present invention.

Claims (3)

Clock in time division multiplexing service using adaptive and differential modes in adaptive and atypical modes in the process of converting a packet from a packet to a TDM frame in a system transmitting a TDM signal through a packet network regardless of a circuit connection part Restore method. The method of claim 1, wherein the packet is stored in a queue in the adaptive mode of the atypical and atypical modes, the timestamp and payload information of the stored packet, the packet arrival rate, the degree of filling of the packet reception buffer, the packet reception statistics and the parameter information. A clock recovery method in a time division multiplexing service using a packet network, wherein the clock is restored by using the buffer fill level and the arrival time. 2. The method of claim 1, wherein in a differential mode of the atypical mode, time information is passed from a master node to a slave node using a control packet so that a master TDM clock counter and a common clock timestamp, such as a common clock counter and a slave RDM clock counter, are used. 2. A clock recovery method in a time division multiplexing service via a packet network, wherein the clock is restored by an out of band method of restoring a clock by maintaining a relationship.

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