KR20080022451A - Circuit of multi phase clock generator minimizing jitter in source synchronous interface and a method thereof - Google Patents

Abstract

A method and a circuit for minimizing a jitter in a source synchronous interface are provided to minimize the jitter by changing characteristics of output signals from a PLL and a DLL according to system characteristics. A PLL(Phase Locked Loop)(310) generates plural first multi-phase clock signals in response to a reference clock signal and outputs the first multi-phase clock signals. A DLL(Delay Locked Loop)(320) generates plural second multi-phase clock signals in response to the reference clock signal and outputs the second multi-phase clock signals. The numbers of the first and second multi-phase clock signals are the same. Plural phase interpolators(330) receive the first and second multi-phase clock signals and output interpolated signals. A controller(340) controls the interpolators, so that the first and second multi-phase clock signals are interpolated to minimize jitters.

Description

Multi-phase clock generator minimizing interface and method for minimizing jitter in a source synchronous interface (minimizing jitter and multi-phase clock method minimizing interface)

BRIEF DESCRIPTION OF THE DRAWINGS In order to better understand the drawings cited in the detailed description of the invention, a brief description of each drawing is provided.

1 is a conventional Quad Data Rate (QDR) interface system.

FIG. 2 is a graph illustrating jitter characteristics of an output signal according to jitter frequencies of a phase locked loop (PLL) and a delay locked loop (DLL).

3 is a block diagram illustrating a multi phase clock generator 300 according to an embodiment of the present invention.

FIG. 4 is a circuit diagram illustrating a structure of a phase interpolator of FIG. 3.

5 is a block diagram illustrating a multi-phase clock generation circuit according to another embodiment of the present invention.

6 is a flowchart of a multi-phase clock generation method for jitter minimization according to an embodiment of the present invention.

Figure 7 shows the magnitude of the jitter component at the receiving end according to the frequency.

TECHNICAL FIELD The present invention relates to a multi phase clock generator and a method thereof, and more particularly, to a multi phase clock generator circuit and a method for minimizing jitter in a source synchronous interface.

Conventional Dole Data Rate (DDR) and Graphic Double Data Rate (GDDR) DRAMs use strobe signals for data transfer. The DDR interface uses the rising and falling edges of the data strobe signal (DQS) when transferring data from a controller or DRAM, and also determines the rising and falling edges when determining data. use. This method has the advantage of transmitting data twice as fast as the data strobe signal (DQS) frequency and phase noise is commonly applied because data DQ and data strobe signal (DQS) are transmitted in the same path. It has the advantage of being removable. It also has the advantage of not requiring a separate delay locked loop (DLL) or phase locked loop (PLL) on the receiving chip. However, there is a disadvantage that the higher the data transmission rate, the higher the frequency of the data strobe signal DQS. For example, in a memory system having a data transfer rate of more than Gb / s (giga bit / sec), the frequency of the data strobe signal (DQS) should also be greater than or equal to GHz (giga hertz). DQS) is difficult to distribute and difficult to determine data DQ.

In order to solve this problem, a quad data rate (QDR) method has been introduced. The QDR method is a method of transmitting data using rising edges of clocks having phases of 0 degrees, 90 degrees, 180 degrees, and 270 degrees. The QDR method can achieve data transfer rates four times faster than the clock frequency.

1 is a conventional Quad Data Rate (QDR) interface system 100.

Referring to FIG. 1, the receiving end (RX) 110 of the QDR interface system 100 needs a PLL (RX_PLL) or a DLL (RX_DLL) to generate a multi phase clock. The transmitting end TX 150 transmits the data signal DQ to the receiving end 110 and simultaneously transmits an external clock signal Ext_clk to the receiving end 110. At the receiving end 110, the PLL (RX_PLL) or the DLL (RX_DLL) generates an internal clock signal Int_clk by inputting an external clock signal Ext_clk and determines data. In this case, since the jitter generated while passing through the PLL TX_PLL in the transmitter 150 is equally applied to the data signal DQ and the external clock signal Ext_clk, the jitter may be removed from the receiver 110. .

However, when the jitter is removed as described above, a different state is displayed depending on whether the jitter is a high frequency or a low frequency.

2 is a graph showing jitter characteristics of an output signal according to jitter frequencies of the PLL and the DLL.

2 (a) is a graph showing the jitter characteristic of the output signal according to the jitter frequency of the PLL. Referring to FIG. 2A, the PLL filters a signal having a frequency higher than the PLL bandwidth. When the receiver 110 of FIG. 2 is a PLL (RX_PLL), jitter having a frequency component higher than the PLL bandwidth is blocked at the PLL (RX_PLL), so that there is a jitter component in the data signal DQ, but not in the internal clock signal Int-clk. Jitter component is blocked. Therefore, when jitter having a frequency component higher than the PLL bandwidth, the jitter is not removed at the receiving end 110.

Figure 2 (b) is a graph showing the jitter characteristics of the output signal according to the jitter frequency of the DLL. Referring to FIG. 2 (b), the DLL exhibits a property of passing jitter of the input signal. However, when the jitter frequency is a high frequency, the DLL generates a delay in itself, so that the high frequency jitter applied by the transmitting end 150 causes a phase difference between the data signal DQ and the DLL output, thereby causing jitter components to be summed. do. Therefore, when the DLL delay time becomes a high frequency above the influence, the jitter of the data signal DQ and the jitter component of the internal clock signal Int_clk is generated.

As a result, within the PLL bandwidth, both the PLL and the DLL have the same effect of removing jitter, and the DLL has better jitter rejection in the frequency range above the PLL bandwidth and below the frequency at which the DLL latency affects. In addition, at frequencies above the frequency at which the DLL delay affects, the PLL again has better jitter rejection.

However, in actual systems, it is difficult to predict what happens to the jitter component before its implementation, and there is a problem in the efficiency of removing the jitter component when only one of the PLL and the DLL is used to remove the jitter.

An object of the present invention is to provide a multi-phase clock generation circuit having both characteristics of a PLL and a DLL, and minimizing jitter by changing characteristics of an output signal of the PLL and a DLL according to characteristics of a system.

Another technical problem to be achieved by the present invention is to provide a multi-phase clock generation method having both characteristics of the PLL and DLL and minimizing jitter by changing the characteristics of the output signal of the PLL and DLL according to the characteristics of the system. .

According to an aspect of the present invention, a multi-phase clock generator (PLL) generates and outputs a plurality of first multi-phase clock signals in response to a reference clock signal. ); A delay locked loop (DLL) for generating and outputting the same number of second multi-phase clock signals as the first multi-phase clock signal in response to the reference clock signal; A plurality of phase interpolators configured to output an interpolated signal by inputting the first multi-phase clock signal and the second multi-phase clock signal; And a controller configured to control the first interpolator to interpolate the first multi-phase clock signal and the second multi-phase clock signal at a rate of minimizing jitter.

The controller may be configured to control the interpolation at a rate of minimizing the jitter by the jitter measurement value measured by the jitter measurement circuit embedded in the chip including the multi-phase clock generation circuit, or the chip including the multi-phase clock generation circuit. It is desirable to control such that the jitter is externally interpolated at a rate that is minimized.

The multi-phase clock generation circuit is preferably used in a quad data rate (QDR) interface system.

According to another aspect of the present invention, a multi phase clock generator generates and outputs a control voltage signal and a plurality of first multi-phase clock signals in response to a reference clock signal. Phase Locked Loop (PLL); A voltage controlled delay circuit configured to generate and output the same number of second multi-phase clock signals as the first multi-phase clock signal in response to the reference clock signal and the control voltage signal output from the PLL; A plurality of phase interpolators configured to output interpolated signals by inputting the first multi-phase clock signal and the second multi-phase clock signal; And a controller configured to control the first interpolator to interpolate the first multi-phase clock signal and the second multi-phase clock signal at a rate of minimizing jitter.

The PLL includes: a phase frequency detector for comparing the reference clock signal and an internal clock signal to detect and output a phase difference thereof; A charge pump converting the output signal of the phase frequency detector into a voltage signal; A loop filter outputting the control voltage signal for varying a delay time from the voltage signal; And a voltage controlled oscillator for adjusting the delay time of the reference clock signal according to the control voltage signal and outputting the delayed clock signal as the internal clock signal.

According to another aspect of the present invention, there is provided a method of generating a multi-phase clock according to an embodiment of the present invention. The method includes generating and outputting a plurality of first multi-phase clock signals in response to a reference clock signal using a phase locked loop (PLL). ; Generating and outputting the same number of second multi-phase clock signals as the first multi-phase clock signal in response to the reference clock signal using a delay locked loop (DLL); And interpolating and outputting the first multi-phase clock signal and the second multi-phase clock signal at a rate where jitter is minimized.

According to another aspect of the present invention, there is provided a method of generating a multi-phase clock according to a control voltage signal and a plurality of first multi-phase clock signals in response to a reference clock signal using a phase locked loop (PLL). Generating and outputting; Generate and output the same number of second multi-phase clock signals as the first multi-phase clock signal in response to the reference clock signal and the control voltage signal output from the PLL using a voltage controlled delay circuit. Making; And interpolating and outputting the first multi-phase clock signal and the second multi-phase clock signal at a rate where jitter is minimized.

DETAILED DESCRIPTION In order to fully understand the present invention, the operational advantages of the present invention, and the objects achieved by the practice of the present invention, reference should be made to the accompanying drawings which illustrate preferred embodiments of the present invention and the contents described in the drawings.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. Like reference numerals in the drawings denote like elements.

3 is a block diagram illustrating a multi phase clock generator 300 according to an embodiment of the present invention.

Referring to FIG. 3, the multi-phase clock generation circuit of the present invention has both characteristics of a phase locked loop (PLL) and a delay locked loop (DLL), and may change characteristics of the PLL and the DLL according to characteristics of a system. have. The multi-phase clock generation circuit 300 according to the embodiment of the present invention includes a PLL 310, a DLL 320, a phase interpolator (PI) 330, and a controller 340.

The PLL 310 has the same structure as a general PLL. That is, a phase frequency detector (PFD) for comparing the reference clock signal Ref_clk and the internal clock signal of the PLL 310 to detect and output the phase difference, and outputs the output signal of the phase frequency detector PFD. A charge pump (CP) for converting into a signal, a loop filter (LP) for outputting a control voltage signal for varying a delay time from the voltage signal, and the reference clock signal according to the control voltage signal ( A voltage controlled oscillator (VCO) for adjusting the delay time of Ref_clk and outputting the internal clock signal of the PLL 310 is provided. The PLL 310 of the present invention generates and outputs a plurality of first multi-phase clock signals PP0, PP90, PP180, and PP270, which will be described with reference to FIG. 5.

The DLL 320 also has the same structure as a general DLL. The configuration of the DLL 320 includes a voltage controlled delay line (VCDL) instead of the voltage controlled oscillator (VCO) of the PLL 310 and does not feed back an internal clock signal. Different from 310. Except for the above, since it is the same as the PLL 310, a detailed description of the DLL 320 is omitted. The DLL 320 of the present invention generates and outputs the same number of second multi-phase clock signals PD0, PD90, PD180, and PD270 as the first multi-phase clock signal, which will be described with reference to FIG. 5.

A phase interpolator (PI) 330 interpolates the first multi-phase clock signals PP0, PP90, PP180, and PP270 and the second multi-phase clock signals PD0, PD90, PD180, and PD270 as inputs. ) And outputs the P0, P90, P180, and P270 signals. Interpolate means averaging two signals having different phases by weighting them at a constant ratio. In detail, a method of interpolating will be described with reference to FIG. 5. The structure of the phase interpolator 330 also has the same structure as the general phase interpolator. The structure of the phase interpolator 330 will be described with reference to FIG. 4.

The controller 340 jitters the first multi-phase clock signals PP0, PP90, PP180, and PP270 and the second multi-phase clock signals PD0, PD90, PD180, and PD270 in the phase interpolator 330. Controls to interpolate at a rate that minimizes. That is, the controller 340 determines whether to weight the first multi-phase clock signals PP0, PP90, PP180, and PP270 and the second multi-phase clock signals PD0, PD90, PD180, and PD270 at a ratio. Control to minimize jitter in the system.

The controller 340 may control the interpolation at a rate where the jitter is minimized by the jitter measurement value measured by the jitter measurement circuit included in the chip including the multi-phase clock generation circuit 300, or the jitter outside the chip. May be controlled to be interpolated at a rate that is minimized.

4 is a circuit diagram illustrating a structure of the phase interpolator (PI) 330 of FIG. 3.

4 (a) illustrates the structure of the phase interpolator 330 implemented with inverters. The output signals PP0 of the PLL 310 are input to the plurality of inverters 410 and 420 connected in parallel, and the output signals PD0 of the DLL 320 are input to the plurality of inverters 430 and 440 connected in parallel. The inverters 410, 420, 430, 440 are controlled by the control signals SW1, / SW1,... SW4, / SW4 of the controller 340, and the inverters 410, 420, 430, 440. ) Is output to the output signal P0 of the phase interpolator 330 again through the inverter 450.

FIG. 4B is a circuit diagram of the inverters 410 and 420 of FIG. 4A. In FIG. 4B, only the inverters 410 and 420 to which the PLL 310 output signal PP0 is input are illustrated, but the inverters 430 and 440 to which the DLL 320 output signal PD0 is input. Also has the same structure. By turning on or off the PMOS transistors and the NMOS transistors in the inverters 410 and 420 according to the control signals SW1, / SW1, SW2, and / SW2, the PLL 310 is turned on. Adjust the weight of the output signal PP0. In the same manner, the output signal P0 is generated by interpolating the two output signals PP0 and PD0 by adjusting the weight of the output signal PD0 of the DLL 320.

4 (a) and 4 (b), the case where two inverters are connected in parallel has been described as an example. However, the number of the inverters connected in parallel may be arbitrarily changed. In addition, the case where the control signal is implemented as an inverter for controlling the transistor serving as an example, but may be implemented as a differential amplifier (Differential Amplifier) for controlling the current by the control signal.

5 is a block diagram illustrating a multi-phase clock generation circuit 500 according to another embodiment of the present invention.

Referring to FIG. 5, the multi-phase clock generation circuit 500 according to the embodiment of FIG. 5 replaces the voltage control delay circuit (VCDL) 520 included in the DLL instead of the DLL 320 in the embodiment of FIG. 3. I use it. The voltage controlled oscillator VCO of the PLL 510 is controlled by a control voltage signal Vctl, and the voltage control delay circuit VCDL 520 is also generated and output from the PLL 510. Can be controlled by Accordingly, the voltage control delay circuit (VCDL) 520 may generate a plurality of first multi-phase clock signals PP0 and PP90 generated by the PLL 510 in response to the reference clock signal Ref_clk and the control voltage signal Vctl. And generate and output the same number of second multi-phase clock signals PD0, PD90, PD180, and PD270 as PP180 and PP270. The configuration of the PLL 510, the phase interpolator 530, and the controller 540 is the same as that of FIG. 3. The multi-phase clock generation circuit 500 according to the embodiment of FIG. 5 may reduce the size of the circuit by using the voltage controlled delay circuit (VCDL) 520 instead of the DLL.

6 is a flowchart of a multi-phase clock generation method for jitter minimization according to an embodiment of the present invention.

3 and 6, a method of using the multi-phase clock generation circuit 300 in a quad data rate (QDR) interface system will be described. The QDR interface system generates four clocks with a phase difference of 90 degrees. Accordingly, the PLL 310 generates four first multi-phase clock signals PP0, PP90, PP180, and PP270 having a phase difference of 90 degrees and outputs them to the phase interpolator 330 (S610). The DLL 320 also generates four second multi-phase clock signals PD0, PD90, PD180, and PD270 having a phase difference of 90 degrees and outputs them to the phase interpolator 330 (S620). In the phase interpolator 330, the first multi-phase clock signals PP0, PP90, PP180, and PP270 and the second multi-phase clock signals PD0, PD90, PD180, and PD270 according to a ratio of weights controlled by the controller 340. ) Are interpolated to output output signals P0, P90, P180, and P270 (S630). Since the controller 340 controls the phase interpolator 330 to minimize jitter in the system, the signal interpolated and output from the phase interpolator 330 has a minimum jitter component.

Figure 7 shows the magnitude of the jitter component at the receiving end according to the frequency. FIG. 7A is an output signal of the PLL, and FIG. 7B is an output signal of the DLL.

3 and 7 (a), the output signal of the PLL 310 cancels the jitter component of the data signal DQ and the jitter component of the output signal of the PLL 310 in the x section, which is the PLL bandwidth. The jitter component disappears. However, since the jitter component of the PLL 310 output signal is blocked in the y and z sections having a frequency higher than the PLL bandwidth, the jitter component of the data signal DQ remains at the receiving end.

3 and 7 (b), the output signal of the DLL 320 includes the jitter component of the data signal DQ and the DLL ( The jitter components of the output signal of 320 cancel each other out so that the jitter components disappear. However, in the z section above the frequency at which the DLL 320 delay time affects, the delay occurs in the DLL 320 itself, and the jitter component of the data signal DQ and the jitter component of the DLL 320 output signal are combined. The jitter component will appear.

Therefore, the controller 340 controls the ratio of the weights of the PLL 310 output signal and the DLL 320 output signal so that the jitter component according to the frequency is checked after the system is implemented. 7 (a) and 7 (b), the phase interpolator 330 may output the PLL 310 output signal or the DLL 320 output signal in the x section, but in the y section, the PLL 310 outputs the PLL 310 output signal or the DLL 320 output signal. The 310 output signal may be blocked and only the output signal of the DLL 320 may be output from the phase interpolator 330 to block the jitter component. In addition, since the jitter component of the DLL 320 output signal is very large in the z section, the jitter component may be minimized by blocking the DLL 320 output signal and outputting only the PLL 310 output signal from the phase interpolator 330. . In the above example, the weight of only one of the PLL 310 output signal and the DLL 320 output signal is extremely weighted and output from the phase interpolator 330 as an example. However, if necessary, the ratio of the weight is adjusted. You can also output

FIG. 7C illustrates an output signal of the phase interpolator 330 when the output signals of FIGS. 7A and 7B are interpolated with a weight of 50%. In this way, the ratio of the PLL 310 output signal and the DLL 320 output signal may be interpolated at a ratio of 1: 1, or may be interpolated at a different ratio. The ratio of the weight may be changed by the controller 340 to suit the characteristics of the implemented system.

As described above, optimal embodiments have been disclosed in the drawings and the specification. Although specific terms have been used herein, they are used only for the purpose of describing the present invention and are not intended to limit the scope of the present invention as defined in the claims or the claims. Therefore, those skilled in the art will understand that various modifications and equivalent other embodiments are possible therefrom. Therefore, the true technical protection scope of the present invention will be defined by the technical spirit of the appended claims.

As described above, a multi phase clock generator and a method for minimizing jitter in a source synchronous interface according to the present invention have both characteristics of a PLL and a DLL. By changing the characteristics of the output signal of the PLL and DLL according to the characteristics there is an advantage that can minimize the jitter.

Claims (13)

A phase locked loop (PLL) for generating and outputting a plurality of first multi-phase clock signals in response to a reference clock signal; A delay locked loop (DLL) for generating and outputting the same number of second multi-phase clock signals as the first multi-phase clock signal in response to the reference clock signal; A plurality of phase interpolators configured to output an interpolated signal by inputting the first multi-phase clock signal and the second multi-phase clock signal; And And a control unit configured to control the first interpolator to interpolate the first multi-phase clock signal and the second multi-phase clock signal at a rate at which jitter is minimized. phase clock generator). The method of claim 1, wherein the control unit, And controlling the interpolation at a rate that minimizes the jitter by the jitter measurement value measured by the jitter measurement circuit embedded in the chip including the multiphase clock generation circuit. The method of claim 1, wherein the control unit, And controlling the interpolation at a rate at which the jitter is minimized outside the chip including the multi-phase clock generation circuit. The circuit of claim 1, wherein the multi-phase clock generation circuit comprises: A multi-phase clock generation circuit characterized by being used in a QDR (Quad Data Rate) interface system. A phase locked loop (PLL) for generating and outputting a control voltage signal and a plurality of first multi-phase clock signals in response to a reference clock signal;  A voltage controlled delay circuit configured to generate and output the same number of second multi-phase clock signals as the first multi-phase clock signal in response to the reference clock signal and the control voltage signal output from the PLL; A plurality of phase interpolators configured to output interpolated signals by inputting the first multi-phase clock signal and the second multi-phase clock signal; And And a control unit configured to control the first interpolator to interpolate the first multi-phase clock signal and the second multi-phase clock signal at a rate at which jitter is minimized. phase clock generator). The method of claim 5, wherein the control unit, And controlling the interpolation at a rate that minimizes the jitter by the jitter measurement value measured by the jitter measurement circuit embedded in the chip including the multiphase clock generation circuit. The method of claim 5, wherein the control unit, And controlling the interpolation at a rate at which the jitter is minimized outside the chip including the multi-phase clock generation circuit. The method of claim 5, wherein the PLL is, A phase frequency detector for comparing the reference clock signal and the internal clock signal to detect and output a phase difference thereof; A charge pump converting the output signal of the phase frequency detector into a voltage signal; A loop filter outputting the control voltage signal for varying a delay time from the voltage signal; And And a voltage controlled oscillator for adjusting the delay time of the reference clock signal according to the control voltage signal and outputting the delayed clock signal as the internal clock signal. The circuit of claim 5, wherein the multi-phase clock generation circuit comprises: A multi-phase clock generation circuit characterized by being used in a QDR (Quad Data Rate) interface system. Generating and outputting a plurality of first multi-phase clock signals in response to a reference clock signal using a phase locked loop (PLL); Generating and outputting the same number of second multi-phase clock signals as the first multi-phase clock signal in response to the reference clock signal using a delay locked loop (DLL); And And interpolating and outputting the first multi-phase clock signal and the second multi-phase clock signal at a rate at which jitter is minimized. The method of claim 10, wherein the multi-phase clock generation method, A method of generating a multi-phase clock which is used in a quad data rate (QDR) interface system. Generating and outputting a control voltage signal and a plurality of first multi-phase clock signals in response to a reference clock signal using a phase locked loop (PLL); Generate and output the same number of second multi-phase clock signals as the first multi-phase clock signal in response to the reference clock signal and the control voltage signal output from the PLL using a voltage controlled delay circuit. Making; And And interpolating and outputting the first multi-phase clock signal and the second multi-phase clock signal at a rate at which jitter is minimized. The method of claim 12, wherein the multi-phase clock generation method, A method of generating a multi-phase clock which is used in a quad data rate (QDR) interface system.

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