KR20080022394A - Program method of a flash memory device having multi-level cell - Google Patents

Abstract

A program method of a flash memory device having a multi-level cell is provided to reduce interference between memory cells by changing the sequence of data corresponding to each threshold voltage and then performing program operation along the direction of a word line. A flash memory device including a multi-level cell comprises two memory cell arrays having a plurality of strings. The string is constituted with a plurality of memory cells sharing drains and sources through a drain selection transistor and a source selection transistor. According to a program method of the flash memory device, the program operation is performed along the direction of a word line. Program verify and read operation are performed along the direction of a page.

Description

Program method of a flash memory device having a multi-level cell

1 is a diagram illustrating a program method of a conventional flash memory device.

2 to 3 are diagrams illustrating a memory cell array of a flash memory device according to the present invention.

4 is a diagram illustrating a program method of a flash memory device according to the present invention.

<Explanation of symbols for the main parts of the drawings>

100: memory cell array 101, 102: memory cell string

110: page buffer section BLe, BLo: bit line

WL0 to WLn: Word line F0 to Fn: Memory cell

The present invention relates to a method of programming a flash memory, and more particularly, to a method of programming a flash memory device having a multi-level cell.

Semiconductor memory devices are classified into volatile memory and non-volatile memory devices depending on whether data is preserved when a power supply is interrupted. Among them, nonvolatile memory devices are memory that can continuously maintain data even when power supply is interrupted. In recent years, flash memories have been in the spotlight. Flash memory devices are classified into NOR type and NAND type. Since NOR flash memory has a structure in which memory cells are independently connected to bit lines and word lines, random access time characteristics are reduced. The NAND flash memory has excellent characteristics in terms of integration since a plurality of memory cells are connected in series and require one contact film per cell string. Therefore, in recent years, NAND flash memories have been in the spotlight due to high integration of flash memory devices.

If a conventional single bit memory cell is referred to as a single-level cell (SLC), research on a multi-level cell (MLC) has recently been actively conducted. Such multi-level cells are driven by storing a plurality of data in one memory cell to increase the degree of integration of the device.

Multi-level cells typically have more than one threshold voltage. And, it has two or more data storage states corresponding thereto. Recent multi-level cells typically have four data storage states of '11', '10', '00' and '01'. The four data states are defined as threshold voltage distributions. That is, when the threshold voltage of the multi-level cell corresponds to any one of the four threshold voltage voltage distributions defined above, 2-bit data corresponding thereto is stored in the memory cell. The program operation of the multi-level setup will be described in detail as follows.

The program operation of the multi-level cell is programmed in selected memory cells using F-N tunneling phenomenon. A predetermined program voltage is applied to the gates of the selected cells, respectively, and a ground voltage Vss or a predetermined voltage is applied to the channels of the selected cells. Thus, a high electric field is formed between the floating gate and the channel of the cell being programmed. The program is made by accumulating electrons of the channel in the electric field in the floating gate of the selected cell.

1 is a diagram illustrating a program method of a conventional flash memory device. The multi-level cell array stores at least two bits of data. The data bits are divided into upper data bits and lower data bits. In this case, the upper data bit is defined as MSB and the lower bit is defined as LSB. In the above description, for example, '10' out of four data storage states '11', '10', '00', and '01', '1' is an MSB corresponding to an upper data bit, and '0' is a lower level. LSB corresponding to the data bit.

Therefore, when the LSB is programmed in '11', it becomes '10'. The MSB program operation detects the LSB program result and makes the MSB program according to the result. If '1' is detected by the LSB, the data storage state is '11' and if the MSB program is operated here, it is '01'. In addition, if '0' is detected by the LSB, the data storage state is '10', so when the MSB program operates, the value is '00'.

However, since a multilevel cell has a larger number of threshold voltage distributions than a single level cell, a sufficient read margin of each threshold voltage distribution is required. Interference between adjacent cells among the factors that change the threshold voltage is mostly present in the NAND flash memory. As the integration of the device increases, the threshold voltage change due to the interference increases, which may degrade the device characteristics. have.

Accordingly, the present invention is to reduce the interference between the memory cells by changing the order of the data corresponding to each of the threshold voltages, and performing the program operation in the word line direction.

The present invention relates to a method of programming a flash memory device having a multi-level cell, wherein a plurality of memory cells are connected in series, and the memory cells connected in series share a drain and a source through a drain select transistor and a source select transistor. In the method of programming a flash memory device comprising a plurality of strings, the plurality of strings as a memory cell array, and a multi-level cell including two memory cell arrays, the upper and lower data bits Flash memory having a multi-level cell comprising the step of performing a program operation on the memory cell divided into four program intervals, the program operation in the word line direction, the program verification and read operation in the page unit Contains program method of device The.

Hereinafter, with reference to the accompanying drawings will be described a preferred embodiment of the present invention. However, the present invention is not limited to the embodiments disclosed below, but can be implemented in various forms, and only the present embodiments are intended to complete the disclosure of the present invention and to those skilled in the art. It is provided for complete information.

2 to 3 are diagrams illustrating a memory cell array of a flash memory device according to the present invention.

Referring to FIG. 2, the memory cell array 100 includes a plurality of cell strings 101. The cell string 101 includes a drain select element DST, a plurality of memory cells F0 to Fn, and a source select element SST, which are connected to the bit line 101. The cell string 101 includes a plurality of elements, and the elements constituting each cell string are connected to the plurality of word lines WL0 to WLn. In addition, the plurality of bit lines BLe and BLo are connected to the page buffer unit 110 including a plurality of page buffers (not shown).

Referring to FIG. 3, a multilevel cell using a plurality of memory cell arrays of FIG. 2 is schematically illustrated. Each of F0 to Fn represents a memory cell. The program operation is performed in the word lines WL0, WL1, ... WLn directions (B direction), not in the bit lines (BLe, BLo) directions (A direction). That is, when programming, any one of the word lines WL0 to WLn is selected to be programmed. In the program operation, neighboring cells of the programmed cell are subjected to interference (A, B, C). However, if the program is executed in the word line direction (B direction), interference (B) with at least neighboring cells of the string can be prevented. Since adjacent cells share a common word line, even if a program voltage is applied to the word line, neighboring cells are all applied with the same voltage, so that the cells in the x-axis direction B do not interfere with each other.

4 is a diagram illustrating a program method of a flash memory device according to the present invention. The data storage states of two bits are set to '11', '01', '10', and '00', and each of them is sequentially defined in the threshold voltage distribution. That is, the data storage state of the lowest threshold voltage distribution is set to '11', and then '01', '10' and '00' are defined in order. Then, when the LSB is programmed, it is changed from '11' to '10', and when the MSB is programmed, it is changed from '11' to '01' or from '10' to '00'. When the program is executed in the above operation, the interference between cells in the y direction A and the diagonal direction C in FIG. 3 is reduced.

In addition, the program operation is performed in the word line direction, and the program verify and read operations are performed in a page buffer unit. This is to prevent readout malfunction due to cross talk. Crosstalk is a phenomenon in which a malfunction occurs when a signal (voltage) is applied to a desired metal wiring and another metal wiring adjacent is affected and the voltage is shaken. Therefore, in order to reduce the interference shape, the program is performed in the word line direction while verification or read is performed in units of pages to prevent cross talk. This requires a page buffer for each bit line.

Although the technical spirit of the present invention described above has been described in detail in a preferred embodiment, it should be noted that the above-described embodiment is for the purpose of description and not of limitation. In addition, the present invention will be understood by those skilled in the art that various embodiments are possible within the scope of the technical idea of the present invention.

As described above, according to the present invention, the interference between memory cells can be reduced by changing the program operation, thereby securing the threshold voltage distribution margin of the multi-level cell, and the speed of the program operation is improved, thereby increasing the data throughput. Can be increased.

Claims (6)

A plurality of memory cells are connected in series, the memory cells connected in series share a drain and a source through a drain select transistor and a source select transistor to form one string, and the plurality of strings are stored in one memory cell array. In the method of programming a flash memory device comprising a multi-level cell consisting of two memory cell array, Performing the program operation in a word line direction; And And program verifying and reading operations are performed in the page direction. A program method of a flash memory device having a multi-level cell in which upper and lower data bits are defined in first to fourth threshold voltage periods, And a 2-bit data storage state in each of the threshold voltage sections is sequentially defined as '11', '01', '10', '00' and has LSB and MSB programmed multi-level cells. The method of claim 2, And the first to fourth threshold voltage periods have multi-level cells defined in order of low threshold voltage. The method of claim 2, And wherein the LSB program has a multi-level cell in which the data storage state is changed from '11' to '10'. The method of claim 2, The MSB program has a multi-level cell in which the data storage state is changed from '11' to '01' according to the LSB program state. The method of claim 2, And the MSB program has a multi-level cell in which the data storage state is changed from '10' to '00' according to the LSB program state.

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