KR100854871B1 - Non-volatile memory device and method for program using the same - Google Patents

Abstract

A non-volatile memory device and a program method using the same are provided to assure sufficient read margin by forming narrow threshold voltage distribution by enabling total word lines to have equal interference effect. A source select line(SSL) is connected to a floating gate and a control gate electrically. The floating gate is separated from the control gate electrically in a drain select line(DSL). A number of word lines(WL0-WL31) are formed between the source select line and the drain select line. According to the program method of a non-volatile memory device, the word lines are programmed first, before the drain select line are programmed.

Description

Non-volatile memory device and method for using the same {Non-volatile memory device and method for program using the same}

1A is a cross-sectional view illustrating a device for explaining a nonvolatile memory device according to the present invention.

1B is a flowchart illustrating a program method using a nonvolatile memory device according to the present invention.

2 is a diagram illustrating a threshold voltage distribution of a word line according to the related art.

3 is a schematic diagram illustrating a program method using a nonvolatile memory device according to the present invention.

<Description of the symbols for the main parts of the drawings>

102 semiconductor substrate 104 gate insulating film

106: first conductive film for floating gate 108: dielectric film

110: second conductive film for the control gate

The present invention relates to a nonvolatile memory device and a programming method using the same, and more particularly, to a NAND flash memory device having a multi level cell (MLC) and a program method using the same.

Flash memory is a nonvolatile memory that can retain data even when the power is cut off, and can be programmed and erased electrically without the need to refresh data at regular intervals. Refers to the device. Here, the program refers to an operation of writing data to a memory cell, and the erasing means an operation of erasing data written to the memory cell.

Such flash memory devices are divided into NOR-type flash memory devices and NAND-type flash memory devices according to cell structures and operating conditions. In the quinoa flash memory device, the drain of each memory cell transistor is connected to a bit line. Therefore, since it can be programmed and erased for an arbitrary address and its operation speed is high, it is mainly used for applications requiring high speed operation. On the other hand, in a NAND flash memory device, a plurality of memory cell transistors are connected in series to form a string, and one string is connected to a bit line and a common source line. Therefore, since it is easy to increase the degree of integration, it is mainly used in applications requiring high capacity data storage.

On the other hand, the memory cell size of the flash memory device required by the high integration of the semiconductor device is gradually decreasing, but there is a limit in physically reducing the memory cell size due to the limitation of the patterning technology and process equipment. In order to overcome this limitation, studies on multiple bit cells capable of storing a plurality of data in one memory cell are being actively conducted. A memory cell having such an operation method is called a multi-level cell (MLC).

A multi-level cell (MLC) typically has two or more threshold voltage (Vt) distributions and corresponding two or more data storage states. For example, a multi-level cell (MLC) capable of programming two bits of data has four data storage states: [11], [10], [01], and [00]. These correspond to threshold voltage distributions of each multi-level cell MLC, and if the threshold voltage of the multi-level cell MLC corresponds to one of four threshold voltage distributions, [11], [10], [01] ], Two bits of data information corresponding thereto are read out. As such, since the multi-level cell MLC has a plurality of threshold voltage distributions, it is necessary to ensure sufficient read margin between threshold voltage distributions at each level.

According to the present invention, by forming the drain select line to be programmable, programming the word line, and then programming the drain select line, the entire word line is subjected to the same interference effect, so that the threshold voltage distribution is narrow, thereby ensuring sufficient read margin.

According to an exemplary embodiment of the present invention, a nonvolatile memory device may include a source select line electrically connected to a floating gate and a control gate, a drain select line electrically isolated from the floating gate and a control gate, and between the source select line and the drain select line. And a plurality of formed word lines.

According to another aspect of the present invention, a method of programming a nonvolatile memory device includes a source select line electrically connected to a floating gate and a control gate, and a plurality of word lines and drain select lines electrically isolated from the floating gate and the control gate. And performing a program operation on the word lines, and performing a program operation on the drain select line.

According to another aspect of the present invention, a method of programming a nonvolatile memory device includes a first selection line electrically connected to a floating gate and a control gate, a plurality of word lines and second selection to which the floating gate and the control gate are electrically isolated. Providing a line, performing a first program operation on the second select line, performing a second program operation on the plurality of word lines, and performing a third program operation on the second select line. Characterized in that it comprises a step.

In the first program operation, the threshold voltage of the memory cell connected to the second selection line may be at the same level as the threshold voltage of the transistor connected to the first selection line. The method may further include performing an erase operation on the plurality of word lines and the second selection line before performing the first program operation. The method may further include verifying whether the threshold voltage of the memory cell connected to the second selection line has risen to 0V or more after the first program operation. In the first program operation, 0V may be applied to a bit line, the first select line may be in a floating state, and the plurality of word lines may be in a pass voltage or in a floating state. During the second program operation, a program voltage may be applied to the selected word line, and a pass voltage may be applied to the unselected word lines. In the third program operation, a voltage applied to the drain select line is applied such that the interference effect received by the word line adjacent to the second select line is the same as the interference effect generated in the remaining word lines by the second program. I can regulate it. The first selection line may be a source selection line and the second selection line may be a drain selection line.

Hereinafter, with reference to the accompanying drawings will be described a preferred embodiment of the present invention.

However, the present invention is not limited to the embodiments described below, but may be implemented in various forms, and the scope of the present invention is not limited to the embodiments described below. In addition, those skilled in the art will understand that various embodiments are possible within the scope of the technical idea of the present invention. Only this embodiment is provided to complete the disclosure of the present invention and to fully inform those skilled in the art, the scope of the present invention should be understood by the claims of the present application.

1A is a cross-sectional view illustrating a device for explaining a nonvolatile memory device according to the present invention. 1B is a flowchart illustrating a program method using a nonvolatile memory device according to the present invention. 2 is a diagram illustrating threshold voltage distributions of the word lines WL0 to WL31 when there is no interference effect on the word line WL31. 3 is a schematic diagram illustrating a program method using a nonvolatile memory device according to the present invention.

Referring to FIG. 1A, source select lines SSL, word lines WL0 to WL31, and drain select lines DSL are formed on the semiconductor substrate 102 in parallel at predetermined intervals. . The source select line is formed by connecting gates of the source select transistors, and the source select transistor is selected and operated by the source select line. The source of this source select transistor is electrically connected to the common source line CSL. Normally, 16, 32, or 64 word lines may be formed between the source select line SSL and the drain select line DSL. In the present invention, 32 word lines WL0 to WL31 are formed. In the drawings, only six of them are illustrated.

The word lines WL0 to WL31 and the drain select line DSL are formed on the semiconductor substrate 102 by the gate insulating film 104, the first conductive film 106 for the floating gate, the dielectric film 108, and the second control gate. The conductive film 110 is formed in a stacked structure. Preferably, the first conductive film 106 for the floating gate and the second conductive film 110 for the control gate are formed of polysilicon, and the dielectric film 108 is formed of ONO (sequentially stacked oxide, nitride and oxide films). Oxide / Nitride / Oxide) film structure can be formed. In addition, a low resistance layer (not shown) may be further formed on the second conductive layer 110 for the control gate. The low resistance layer may be formed of a laminated film including a metal silicide and a hard mask. Thereafter, an ion implantation process is performed to form a junction region 114 in the semiconductor substrate 102 between each of the source select lines SSL, the word lines WL0 to WL31, and the drain select line DSL.

The first conductive film 106 for the floating gate and the second conductive film 110 for the control gate of the source select line SSL are electrically connected through a predetermined process. Specifically, all or part of the dielectric film 108 is removed from the source select line SSL so that the first conductive film 106 for the floating gate and the second conductive film 110 for the control gate of the source select line SSL are removed. Can be electrically connected. Alternatively, a plug (not shown) may be connected to the source selection line SSL such that the first conductive layer 106 for the floating gate and the second conductive layer 110 for the control gate of the source selection line SSL may be connected in a subsequent process. ) May be formed.

Meanwhile, referring to the drain select line DSL structure of the present invention, the floating gate and the control gate are electrically connected to each other in the drain select line DSL. However, in the present invention, the floating gate and the control gate are electrically connected to each other. Insulated by. Therefore, the device connected to the drain select line DSL may operate like a memory cell rather than a transistor. A drain of the memory cell connected to the drain select line DSL is electrically connected to the bit line BL.

In this manner, the drain select line DSL is formed in the same structure as the word lines WL0 to WL31 to enable programming of the drain select line DSL. As a result, the same interference effect may be applied to each of the word lines WL0 to WL31 programmed in a sequential manner. This will be described in detail below.

In the related art, since the drain select line DSL is formed in the same structure as the source select line SSL, the drain select line DSL cannot be programmed. In this case, in a general program operation, the word line WL31 adjacent to the drain select line DSL is programmed last among the word lines WL0 to WL31 programmed in a sequential manner. At this time, the first programmed word line receives an interference effect as the adjacent word lines are programmed, and the threshold voltage of the first programmed word line is changed.

However, the word line WL31 that is last programmed adjacent to the drain select line DSL has no word line programmed thereafter. Therefore, the word lines WL0 to WL30 programmed before the last programmed word line WL31 have the same interference effect, and the threshold voltages are changed accordingly, but the last programmed word line WL31 is Since there is no interference effect, threshold voltage fluctuations due to programming of adjacent word lines WL0 to WL30 do not occur. This will be described in more detail with reference to FIG. 2 as follows.

Referring to FIG. 2, the threshold voltage distribution 201 of the word line WL31 that is not subjected to the interference effect after the program is generally wider than the threshold voltage distribution 202 of the word lines WL0 to WL30 that are subjected to the interference effect after the program. Is formed wide. Of course, the word lines WL0 to WL30 which are subjected to the interference effect after the program also have the word lines WL0 to WL30 which are not affected by the interference when adjacent cells are in the erased state. However, since the last programmed word line WL31 does not always have the interference effect, the threshold voltage distribution 201 of the word line WL31 that does not receive the interference effect after the programming has a threshold voltage of the word lines WL0 to WL30. The width is wider than the distribution 202. As a result, a margin between the verification voltages PV1 to PV3 and the read voltages R1 to R3 may be reduced, thereby decreasing program throughput.

However, when the drain select line DSL adjacent to the word line WL31 that is programmed last is programmable, and the drain select line DSL is programmed after the word line WL31 is programmed. In addition, the word line WL31 is also subjected to the interference effect in the same way as the interference effects of the previously programmed word lines WL0 to WL30. Then, the interference effect of the entire word lines WL0 to WL31 is the same, and the width of the threshold voltage level of the word line WL31 is narrowed to be equal to the width of the threshold voltage levels of the other word lines WL0 to WL30. As a result, margins with the read voltages R1 to R3 may be increased, thereby improving program throughput.

Hereinafter, a program method of a nonvolatile memory device according to the present invention will be described in detail with reference to FIG. 1B.

In the method of programming a memory device according to the present invention, first, the entire block to be programmed, that is, the entire word lines WL0 to WL31 and the drain select line DSL are erased (S11). At this time, 0 V is applied to the drain select line DSL as well as the word lines WL0 to WL31 and an erase bias is applied to the bulk to perform the erase operation. As a result, the memory cell connected to the drain select line DSL is also erased to lower the threshold voltage. At this time, the source selection line SSL is set to the floating state.

Subsequently, prior to programming the word lines WL0 to WL31, a voltage (a ground voltage or a power supply voltage) applied through the bit lines for programming the word lines WL0 to WL31 is selected from the channels of the word lines WL0 to WL31. It must be delivered to the area. This role may be performed by the drain select transistor connected to the drain select line DSL. However, in the present invention, a memory cell other than a transistor is connected to a drain select line, and a memory cell connected to the drain select line serves as a drain select transistor.

At this time, the threshold voltage of the memory cell connected to the drain select line is lower than 0V by the above-described erase operation. Therefore, the threshold voltage of the memory cell is raised to the same level as the threshold voltage of a general transistor (or a transistor connected to the source select line SSL) so that the memory cell connected to the drain select line DSL can operate like a transistor. You have to. To this end, the program operation is performed on the drain select line DSL (S12), and the threshold voltage of the memory cell connected to the drain select line DSL is the threshold of a general transistor (or a transistor connected to the source select line SSL). It is verified whether the voltage has risen to, for example, 0 V or more (S13). In the program operation of the memory cell connected to the drain select line DSL, 0V is applied to all bit lines, and the source select line SSL is set to the floating state. A pass voltage may be applied to the word lines WL0 to WL31, and the word lines WL0 to WL31 may be set to a floating state.

When the program for the drain select line DSL is completed, the program is selectively applied to the word lines WL0 to WL31 to perform the program (S14), and the program is verified (S15). In the program operation, a program voltage is applied to the selected word lines WL0 to WL31 and a pass voltage is applied to the unselected word lines WL0 to WL31. Meanwhile, as illustrated in FIG. 3, the program operation for the word lines WL0 to WL31 may be performed by performing LSB programs and MSB programs of memory cells connected to the first word line WL0 and the odd bit line BLo. After performing the LSB program and the MSB program of the memory cells connected to the line BLe, the process is then performed in the same manner as the LSB program and the MSB program for the word line WL1.

Subsequently, the drain select line DSL is reprogrammed (S16) and verified (S17) in order to give an interference effect to the last programmed word line WL31. When reprogramming the drain select line DSL, the drain select line DSL may have the same effect as that of the previously programmed word lines WL0 to WL30. It is desirable to adjust the level of the voltage applied to.

Meanwhile, even when the drain select line DSL is programmed, a read bias is applied to the drain select line DSL to electrically connect the memory cell to be read with the bit line.

According to the nonvolatile memory device and the programming method using the same, the drain select line is programmable, the word line is programmed, and the drain select line is programmed so that the entire word line receives the same interference effect and thus the threshold voltage. The narrow distribution allows sufficient read margin. As a result, the peak value of the program threshold voltage is reduced, thereby reducing program time and improving performance of a semiconductor device.

Claims (10)

A source selection line electrically connected to the floating gate and the control gate; A drain select line in which the floating gate and the control gate are electrically isolated; And And a plurality of word lines formed between the source select line and the drain select line.  Providing a source select line electrically connected to the floating gate and the control gate, and a plurality of word lines and drain select lines electrically isolated from the floating gate and the control gate; Performing a program operation on the word lines; And And performing a program operation on the drain select line. Providing a first selection line electrically connected to the floating gate and the control gate, and a plurality of word lines and the second selection line, the isolation gate and the control gate being electrically isolated; Performing a first program operation on the second select line; Performing a second program operation on the plurality of word lines; And And performing a third program operation on the second select line. The method of claim 3, And the threshold voltage of the memory cell connected to the second select line is at the same level as the threshold voltage of a transistor connected to the first select line during the first program operation. The method of claim 3, And performing an erase operation on the plurality of word lines and the second select line before performing the first program operation. The method of claim 3, And verifying whether a threshold voltage of a memory cell connected to the second selection line has risen above 0V after performing the first program operation. The method of claim 3, In the first program operation, 0V is applied to a bit line, the first select line is in a floating state, and the plurality of word lines are in a pass voltage or floating state. The method of claim 3, And a program voltage is applied to the selected word line during the second program operation, and a pass voltage is applied to the unselected word lines. The method of claim 3, In the third program operation, the interference effect received by the word line adjacent to the second select line is equal to the voltage applied to the second select line such that the interference effect generated on the remaining word lines by the second program is the same. Program method of controlling a nonvolatile memory device. The method of claim 3, And the first select line is a source select line and the second select line is a drain select line.

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