KR20080020371A - Method of manufacturing semiconductor device - Google Patents

Method of manufacturing semiconductor device Download PDF

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KR20080020371A
KR20080020371A KR1020060083790A KR20060083790A KR20080020371A KR 20080020371 A KR20080020371 A KR 20080020371A KR 1020060083790 A KR1020060083790 A KR 1020060083790A KR 20060083790 A KR20060083790 A KR 20060083790A KR 20080020371 A KR20080020371 A KR 20080020371A
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South Korea
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contact hole
low dielectric
semiconductor device
manufacturing
laser
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KR1020060083790A
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Korean (ko)
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KR101185855B1 (en
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김찬배
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주식회사 하이닉스반도체
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H01L21/76814—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics post-treatment or after-treatment, e.g. cleaning or removal of oxides on underlying conductors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76822—Modification of the material of dielectric layers, e.g. grading, after-treatment to improve the stability of the layers, to increase their density etc.
    • H01L21/76825—Modification of the material of dielectric layers, e.g. grading, after-treatment to improve the stability of the layers, to increase their density etc. by exposing the layer to particle radiation, e.g. ion implantation, irradiation with UV light or electrons etc.
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76822—Modification of the material of dielectric layers, e.g. grading, after-treatment to improve the stability of the layers, to increase their density etc.
    • H01L21/76826—Modification of the material of dielectric layers, e.g. grading, after-treatment to improve the stability of the layers, to increase their density etc. by contacting the layer with gases, liquids or plasmas
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Plasma & Fusion (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

A method for manufacturing a semiconductor device is provided to improve resistance of a metal line by removing fully carbon-based residues from a contact hole. A low dielectric layer(23) including carbon is formed on a semiconductor substrate(21) having a lower metal line(22). A photosensitive layer pattern is formed on the low dielectric layer in order to expose a contact hole region. A contact hole(H) is formed by etching the low dielectric layer exposed through the photosensitive layer pattern. A laser beam is irradiated to remove carbon-based residues from a sidewall and a bottom surface of the contact hole in a photosensitive layer removal process. A metal layer(25) is formed on the low dielectric layer in order to bury the contact hole.

Description

반도체 소자의 제조방법{METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE}Manufacturing method of semiconductor device {METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE}

도 1은 종래기술의 문제점을 설명하기 위한 반도체 소자의 사진.1 is a photograph of a semiconductor device for explaining the problems of the prior art.

도 2a 내지 도 2f는 본 발명의 실시예에 따른 반도체 소자의 제조방법을 설명하기 위한 공정별 단면도.2A through 2F are cross-sectional views of processes for describing a method of manufacturing a semiconductor device, according to an embodiment of the present invention.

* 도면의 주요 부분에 대한 부호의 설명 *Explanation of symbols on the main parts of the drawings

21 : 반도체 기판 22 : 하부 금속배선21 semiconductor substrate 22 lower metal wiring

23 : 저유전막 24 : 감광막 패턴23: low dielectric film 24: photosensitive film pattern

H : 콘택홀 S : 카본 계열의 잔류물H: Contact hole S: Carbon residue

25 : 금속막 26 : 상부 금속배선25 metal film 26 upper metal wiring

본 발명은 반도체 소자의 제조방법에 관한 것으로, 보다 상세하게는, 카본 성분을 함유한 저유전막을 적용한 금속배선의 형성시 카본 계열의 잔류물을 완전히 제거하여 금속배선의 저항을 개선시킬 수 있는 반도체 소자의 제조방법에 관한 것이다.The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a semiconductor that can improve the resistance of the metal wiring by completely removing the carbon-based residues during the formation of the metal wiring to which the low dielectric film containing the carbon component is applied. It relates to a method for manufacturing a device.

일반적으로, 반도체 소자의 제조시 소자와 소자 간, 또는, 배선과 배선 간을 전기적으로 연결하기 위해 금속배선을 사용하고 있다. 한편, 최근 반도체 소자의 고집적화가 진행함에 따라 금속배선의 폭 및 콘택 면적이 감소하여 콘택저항을 비롯한 금속배선의 저항이 점차 증가하게 되었다. 또한, 상기 금속배선 및 콘택플러그 간의 간격이 좁아짐에 따라 금속배선을 절연시키는 절연막으로 인해 유발되는 기생 캐패시턴스가 증가하게 되었으며, 아울러, 금속배선 간 공간의 매립 공정이 어려워지게 되었다.In general, in the manufacture of semiconductor devices, metal wirings are used to electrically connect the devices with each other or between the wirings and the wirings. On the other hand, as the integration of semiconductor devices in recent years has progressed, the width and contact area of metal wirings have decreased, and the resistance of metal wirings including contact resistances has gradually increased. In addition, as the gap between the metal wiring and the contact plug is narrowed, parasitic capacitance caused by the insulating film for insulating the metal wiring is increased, and the process of filling the space between the metal wiring becomes difficult.

이에, 상기 금속배선의 저항을 낮추고 기생 캐패시턴스를 감소시키기 위한 다양한 공정 기술들이 연구되고 있으며, 그 일환으로서, 상기 금속배선 간 공간을 매립하기 위한 절연막 물질로 매립특성이 우수하며 유전상수 값(K)이 낮은 저유전막을 사용하려는 시도가 이루어지고 있다. 상기 금속배선의 매립을 위해 저유전막을 형성하면, 기생 캐패시턴스(Parasitic Capacitance)의 형성이 방지되어 반도체 소자의 동작속도가 개선된다는 장점이 있다.Therefore, various process technologies for reducing the resistance of the metal wiring and reducing the parasitic capacitance have been studied. As a part of this, an insulating material for filling the space between the metal wirings has excellent embedding characteristics and a dielectric constant value (K). Attempts have been made to use this low low dielectric film. When the low dielectric film is formed to fill the metal wiring, parasitic capacitance is prevented from being formed, thereby improving the operation speed of the semiconductor device.

한편, 상기 저유전막으로서 플루오린(Fluorine)이 함유된 실리콘산화막, 또는, 카본(Carbon)이 함유된 실리콘산화막을 사용하는 방법이 제안되고 있다. 여기서, 상기 플루오린이 함유된 실리콘산화막은 유전상수 값이 3.5∼3.7 정도로 비교적 높은 편이기 때문에 커플링(Coupling)을 감소시키는 효과가 적으므로, 상기 저유전막으로서 2.5∼3.0 정도의 낮은 유전상수 값을 갖는 카본이 함유된 실리콘산화막(이하, SiOC막)이 두루 적용되고 있다. Meanwhile, a method of using a silicon oxide film containing fluorine or a silicon oxide film containing carbon as the low dielectric film has been proposed. Here, since the silicon oxide film containing fluorine has a relatively high dielectric constant value of 3.5 to 3.7, there is little effect of reducing coupling, and thus the low dielectric film has a low dielectric constant value of about 2.5 to 3.0. Silicon oxide films (hereinafter, referred to as SiOC films) containing carbons are applied throughout.

이하에서는, 저유전막으로서 상기 SiOC막을 적용한 종래의 금속배선 공정을 개략적으로 설명하도록 한다.Hereinafter, a conventional metallization process in which the SiOC film is applied as the low dielectric film will be described schematically.

우선, 하부 금속배선이 형성된 반도체 기판 상에 SiOC막으로 저유전막을 형성한 후, 상기 저유전막 상에 공지의 포토리소그라피 공정을 통해 감광막 패턴을 형성한다. 그런 다음, 상기 감광막 패턴에 의해 노출된 저유전막 부분을 식각하여 콘택홀을 형성함과 아울러 감광막 패턴을 제거한다.First, a low dielectric film is formed of an SiOC film on a semiconductor substrate on which a lower metal wiring is formed, and then a photosensitive film pattern is formed on the low dielectric film through a known photolithography process. Then, the portion of the low dielectric film exposed by the photoresist pattern is etched to form a contact hole and to remove the photoresist pattern.

이때, 상기 감광막 패턴을 제거하기 위해 통상 O2 플라즈마 처리를 수행하지만, 상기 O2 플라즈마 처리는 SiOC막으로 형성된 저유전막에 어택(Attack)을 유발한다. 따라서, 상기 콘택홀을 형성하기 위한 저유전막의 식각 공정시 상기 감광막 패턴이 함께 제거되도록 감광막 패턴을 적절한 두께, 바람직하게는, 0.8∼1.0㎛ 정도의 두께로 형성해주어야 한다.At this time, the O 2 plasma treatment is usually performed to remove the photoresist pattern, but the O 2 plasma treatment causes an attack on the low dielectric film formed of the SiOC film. Therefore, during the etching process of the low dielectric film for forming the contact hole, the photoresist pattern should be formed to an appropriate thickness, preferably, about 0.8 to 1.0 μm so that the photoresist pattern is removed together.

계속해서, 상기 콘택홀을 완전 매립하도록 금속막, 예컨데, 텅스텐막이나 구리막을 증착하고 나서, 이를 CMP(Chemical Mechanical Polishing)한 후, 상기 CMP된 금속막을 포함한 기판 결과물 상에 상부 금속배선을 형성한다.Subsequently, a metal film, for example, a tungsten film or a copper film is deposited so as to completely fill the contact hole, followed by CMP (Chemical Mechanical Polishing), and then an upper metal wiring is formed on the substrate product including the CMP metal film. .

그러나, 저유전막으로 상기 SiOC막이 적용된 종래 기술의 경우에는 반도체 소자의 고집적화 추세에 따라 미세해진 패턴 사이즈 때문에 상기 감광막 패턴이 완전히 제거되지 않아, 도 1에 도시된 바와 같이, 상기 콘택홀 측벽 및 저면에 카본 계열의 잔류물이 존재하여 금속배선의 저항을 증가시킨다는 문제점이 있다. However, in the conventional technology in which the SiOC film is applied as a low dielectric film, the photoresist pattern is not completely removed due to a pattern size that has been miniaturized according to a high integration trend of semiconductor devices, as shown in FIG. There is a problem that the residue of the carbon series increases the resistance of the metal wiring.

따라서, 본 발명은 상기와 같은 종래의 문제점을 해결하기 위해 안출된 것으로서, 카본 성분을 함유한 저유전막을 적용한 금속배선의 형성시 카본 계열의 잔류물을 완전히 제거할 수 있는 반도체 소자의 제조방법을 제공함에 그 목적이 있다.Accordingly, the present invention has been made to solve the above-mentioned conventional problems, a method of manufacturing a semiconductor device that can completely remove the carbon-based residues in the formation of the metal wiring to which the low-dielectric film containing the carbon component is applied. The purpose is to provide.

또한, 본 발명은 상기 카본 계열의 잔류물을 완전히 제거하여 금속배선의 저항을 개선시킬 수 있는 반도체 소자의 제조방법을 제공함에 그 다른 목적이 있다.In addition, another object of the present invention is to provide a method of manufacturing a semiconductor device capable of completely removing the carbon-based residue to improve the resistance of metal wiring.

상기와 같은 목적을 달성하기 위한 본 발명의 반도체 소자의 제조방법은, 하부 금속배선이 형성된 반도체 기판 상에 카본 성분을 함유한 저유전막을 형성하는 단계; 상기 저유전막 상에 콘택홀 형성 영역을 노출시키는 감광막 패턴을 형성하는 단계; 상기 감광막 패턴에 의해 노출된 저유전막 부분을 식각하여 콘택홀을 형성함과 아울러 상기 감광막 패턴을 제거하는 단계; 상기 콘택홀이 형성된 기판 결과물에 대해 상기 감광막 패턴의 제거시 상기 콘택홀 측벽 및 저면에 발생된 카본 계열의 잔류물을 제거하기 위해 레이저를 조사하는 단계; 및 상기 콘택홀을 매립하도록 상기 저유전막 상에 금속막을 형성하는 단계;를 포함하는 것을 특징으로 한다.The method of manufacturing a semiconductor device of the present invention for achieving the above object comprises the steps of: forming a low dielectric film containing a carbon component on a semiconductor substrate on which a lower metal wiring is formed; Forming a photoresist layer pattern exposing a contact hole forming region on the low dielectric layer; Etching the low dielectric film portion exposed by the photoresist pattern to form a contact hole and removing the photoresist pattern; Irradiating a laser on the resultant substrate on which the contact hole is formed to remove carbon-based residues generated on the sidewalls and the bottom of the contact hole when the photoresist pattern is removed; And forming a metal film on the low dielectric film to fill the contact hole.

여기서, 상기 레이저를 조사하는 단계는, 레이저만 조사하는 제1단계와 레이저의 조사와 함께 퍼지 가스를 플로우시키는 제2단계로 수행하는 것을 특징으로 한다.The irradiating the laser may be performed as a first step of irradiating only the laser and a second step of flowing purge gas together with irradiation of the laser.

상기 제1단계는, 50mTorr∼1Torr의 압력과 25∼100℃의 온도에서 10∼50W의 파워를 가하면서 수행하는 것을 특징으로 한다.The first step is performed by applying a power of 10 to 50 W at a pressure of 50 mTorr to 1 Torr and a temperature of 25 to 100 ° C.

상기 제1단계의 파워는 50∼350회의 펄스로 가하는 것을 특징으로 한다.The power of the first step is characterized in that applied to 50 to 350 pulses.

상기 제2단계는, 1Torr∼100Torr의 압력과 100∼250℃의 온도에서 30∼100W의 파워를 가하면서 수행하는 것을 특징으로 한다.The second step is carried out while applying a power of 30 to 100W at a pressure of 1 Torr to 100 Torr and a temperature of 100 to 250 ℃.

상기 제2단계의 파워는 300∼6000회의 펄스로 가하는 것을 특징으로 한다.The power of the second step is characterized in that applied to 300 to 6000 pulses.

상기 제2단계는 퍼지 가스로서 Ar 가스와 N2 가스를 플로우시키면서 수행하는 것을 특징으로 한다.The second step may be performed while flowing Ar gas and N 2 gas as a purge gas.

상기 Ar 가스와 N2 가스의 유량은 500∼3000sccm인 것을 특징으로 한다.The Ar gas and the N 2 gas have a flow rate of 500 to 3000 sccm.

(실시예)(Example)

이하, 첨부된 도면을 참조하여 본 발명의 바람직한 실시예를 상세하게 설명하도록 한다.Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

먼저, 본 발명의 기술적 원리를 간략하게 설명하면, 본 발명은 SiOC막으로 형성된 저유전막을 식각하여 콘택홀을 형성하고 나서, 상기 콘택홀 측벽 및 저면에 발생된 카본 계열의 잔류물을 제거하기 위해 1차로 레이저를 조사한 다음, 퍼지 가스를 플로우시키면서 2차로 레이저를 조사한다.First, the technical principle of the present invention will be briefly described. The present invention forms a contact hole by etching a low dielectric film formed of a SiOC film, and then removes carbon-based residues generated on the sidewalls and the bottom of the contact hole. The laser is first irradiated, and then the laser is irradiated secondly while flowing purge gas.

이렇게 하면, 상기 1차 레이저 조사시 일시적인 온도 증가로 인해 잔류물이 불안정한 상태로 존재하게 되고, 그 상태에서 다시 2차로 레이저를 조사하면서 퍼지 가스를 플로우시킴으로써 상기 불안정한 상태의 잔류물을 완전히 제거할 수 있으므로 상기 잔류물로 인해 유발되는 금속배선의 저항 증가를 방지할 수 있다.In this case, the residue remains in an unstable state due to a temporary temperature increase during the first laser irradiation, and the residue in the unstable state can be completely removed by flowing the purge gas while irradiating the laser again in that state. Therefore, it is possible to prevent an increase in resistance of the metal wiring caused by the residue.

자세하게, 도 2a 내지 도 2f는 본 발명의 실시예에 따른 반도체 소자의 제조 방법을 설명하기 위한 공정별 단면도로서, 이를 설명하면 다음과 같다.2A to 2F are cross-sectional views illustrating processes for manufacturing a semiconductor device according to an embodiment of the present invention, which will be described below.

도 2a를 참조하면, 하부 금속배선(22)이 형성된 반도체 기판(21) 상에 카본 성분을 함유한 저유전막(23)을 형성한다. 여기서, 상기 저유전막(23)은 매립특성이 우수하며 유전상수 값(K)이 낮은 SiOC막으로 형성한다.Referring to FIG. 2A, a low dielectric film 23 containing a carbon component is formed on the semiconductor substrate 21 on which the lower metal wiring 22 is formed. Here, the low dielectric film 23 is formed of an SiOC film having excellent embedding characteristics and a low dielectric constant value (K).

도 2b를 참조하면, 상기 저유전막(23) 상에 콘택홀 형성 영역을 노출시키는 감광막 패턴(24)을 형성한다. 이때, 상기 감광막 패턴(24)은 카본을 함유한 막으로 공지의 포토리소그라피 공정, 자세하게, 감광막의 증착, 노광 및 현상 공정을 차례로 수행하여 형성하며, 후속 저유전막(23)의 식각 공정시 상기 감광막 패턴(24)이 제거될 수 있도록 적절한 두께, 바람직하게는, 0.8∼1.0㎛ 정도의 두께로 형성한다.Referring to FIG. 2B, a photosensitive film pattern 24 exposing a contact hole forming region is formed on the low dielectric film 23. In this case, the photoresist layer pattern 24 is formed of a carbon-containing film by performing a well-known photolithography process, in detail, deposition, exposure and development processes of the photoresist layer, and subsequent etching of the low dielectric layer 23. The pattern 24 is formed to an appropriate thickness, preferably 0.8 to 1.0 mu m, so that the pattern 24 can be removed.

도 2c를 참조하면, 상기 감광막 패턴에 의해 노출된 저유전막(23) 부분을 식각하여 콘택홀(H)을 형성한다. 여기서, 상기 식각 공정시 상기 감광막 패턴이 함께 제거되는데, 이때, 일부 감광막 및 상기 감광막과 저유전막 내에 함유된 카본 성분이 상기 콘택홀(H) 측벽 및 저면에 잔류하여 카본 계열의 잔류물(S)이 발생된다.Referring to FIG. 2C, a portion of the low dielectric film 23 exposed by the photoresist pattern is etched to form a contact hole H. Here, the photoresist pattern is removed together during the etching process, wherein a portion of the photoresist and the carbon components contained in the photoresist and the low dielectric film remain on the sidewalls and the bottom of the contact hole (H) to form a carbon-based residue (S). Is generated.

도 2d를 참조하면, 상기 콘택홀(H)이 형성된 기판(21) 결과물에 대해 1차로 레이저를 조사한다.Referring to FIG. 2D, a laser is first irradiated to the resultant of the substrate 21 on which the contact hole H is formed.

여기서, 상기 1차 레이저의 조사는 50mTorr∼1Torr 정도의 압력과 25∼100℃ 정도의 온도에서 10∼50W 정도의 파워를 가하면서 수행하되, 상기 파워는 50∼350회 정도의 펄스를 사용하여 가하도록 한다. 상기 온도는 웨이퍼의 온도를 의미한다. 이때, 상기 1차 레이저 조사에 의해 기판(21) 결과물의 온도가 일시적으로 상 승하므로 상기 카본 계열의 잔류물(S)이 불안정해져서 약간 들뜬 상태로 존재한다.Here, the irradiation of the primary laser is performed while applying a power of about 10 to 50 W at a pressure of about 50 mTorr to 1 Torr and a temperature of about 25 to 100 ° C., and the power is applied by using about 50 to 350 pulses. Do it. The temperature means the temperature of the wafer. At this time, the temperature of the resultant substrate 21 temporarily increases by the first laser irradiation, so that the carbon-based residue S is unstable and exists in a slightly excited state.

도 2e를 참조하면, 상기 1차로 레이저가 조사된 기판(21) 결과물에 대해 상기 1차 레이저의 조사시보다 파워, 온도 및 압력 조건을 높게 해서 2차로 레이저를 조사하여 카본 계열의 잔류물을 완전히 제거한다.Referring to FIG. 2E, the resultant of the substrate 21 irradiated with the first laser is irradiated with the laser secondarily with higher power, temperature and pressure conditions than when the first laser is irradiated to completely remove the carbon-based residue. Remove

상기 2차 레이저의 조사는 1Torr∼100Torr 정도의 압력과 100∼250℃ 정도의 온도에서 30∼100W 정도의 파워를 가하면서 수행하되, 상기 파워는 300∼6000회 정도의 펄스를 사용하여 가한다. 또한, 상기 2차 레이저의 조사와 함께 퍼지 가스로서 불활성 기체인 Ar 가스와 N2 가스를 500∼3000sccm 정도의 유량으로 플로우시켜 상기 들뜬 상태의 잔류물이 원활하게 제거되도록 한다. 이때, 상기 온도는 웨이퍼의 온도를 의미하며, 상기 잔류물의 제거시 발생하는 아웃개싱(Outgassing)을 고려하여 챔버 내의 압력을 적절히 조절함이 바람직하다.Irradiation of the secondary laser is performed while applying a power of about 30 to 100 W at a pressure of about 1 Torr to 100 Torr and a temperature of about 100 to 250 ° C., and the power is applied by using about 300 to 6000 pulses. In addition, with the irradiation of the secondary laser, Ar gas and N 2 gas, which is an inert gas, are flowed at a flow rate of about 500 to 3000 sccm as a purge gas so that the residue in the excited state is smoothly removed. At this time, the temperature means the temperature of the wafer, it is preferable to properly adjust the pressure in the chamber in consideration of the outgassing (Outgassing) generated during the removal of the residue.

도 2f를 참조하면, 상기 카본 계열의 감광막이 완전히 제거된 기판(21) 전면 상에 상기 콘택홀(H)을 매립하도록 금속막(25), 예컨데, 텅스텐막이나 구리막을 증착한다. 그 다음, 상기 금속막(25)을 CMP(Chemical Mechanical Polishing)한 후, 상기 금속막(25)을 포함한 기판(21) 결과물 상에 상부 금속배선(26)을 형성한다.Referring to FIG. 2F, a metal film 25, for example, a tungsten film or a copper film is deposited to fill the contact hole H on the entire surface of the substrate 21 on which the carbon-based photoresist film is completely removed. Next, after the chemical mechanical polishing (CMP) of the metal film 25, the upper metal wiring 26 is formed on the resultant of the substrate 21 including the metal film 25.

여기서, 본 발명은 카본 성분을 함유한 저유전막을 적용한 금속배선의 형성시 상기 저유전막을 식각하여 콘택홀을 형성한 후, 기판 결과물에 대해 레이저를 조사함으로써, 상기 콘택홀의 측벽 및 저면에 발생된 카본 계열의 잔류물을 완전히 제거할 수 있으며, 이를 통해, 금속배선의 저항을 개선시킬 수 있다.Herein, the present invention forms a contact hole by etching the low dielectric film when forming the metal wiring to which the low dielectric film containing carbon component is formed, and then irradiates a laser to the substrate resultant, thereby generating the sidewalls and the bottom of the contact hole. It is possible to completely remove the carbon-based residues, thereby improving the resistance of the metal wiring.

이상, 여기에서는 본 발명을 특정 실시예에 관련하여 도시하고 설명하였지만, 본 발명이 그에 한정되는 것은 아니며, 이하의 특허청구의 범위는 본 발명의 정신과 분야를 이탈하지 않는 한도 내에서 본 발명이 다양하게 개조 및 변형될 수 있다는 것을 당업계에서 통상의 지식을 가진 자가 용이하게 알 수 있다.As mentioned above, although the present invention has been illustrated and described with reference to specific embodiments, the present invention is not limited thereto, and the following claims are not limited to the scope of the present invention without departing from the spirit and scope of the present invention. It can be easily understood by those skilled in the art that can be modified and modified.

이상에서와 같이, 본 발명은 카본 성분을 함유한 저유전막 내에 콘택홀이 형성된 기판 결과물에 대해 레이저를 조사함으로써 상기 콘택홀 내에 잔류된 카본 계열의 잔류물을 완전히 제거할 수 있으며, 이를 통해, 금속배선의 저항을 개선시킬 수 있다.As described above, the present invention can completely remove the carbon-based residues remaining in the contact hole by irradiating a laser to the substrate product in which the contact hole is formed in the low-dielectric film containing the carbon component, through which the metal The resistance of the wiring can be improved.

Claims (8)

하부 금속배선이 형성된 반도체 기판 상에 카본 성분을 함유한 저유전막을 형성하는 단계;Forming a low dielectric film containing carbon on a semiconductor substrate on which lower metal wirings are formed; 상기 저유전막 상에 콘택홀 형성 영역을 노출시키는 감광막 패턴을 형성하는 단계;Forming a photoresist layer pattern exposing a contact hole forming region on the low dielectric layer; 상기 감광막 패턴에 의해 노출된 저유전막 부분을 식각하여 콘택홀을 형성함과 아울러 상기 감광막 패턴을 제거하는 단계;Etching the low dielectric film portion exposed by the photoresist pattern to form a contact hole and removing the photoresist pattern; 상기 콘택홀이 형성된 기판 결과물에 대해 상기 감광막 패턴의 제거시 상기 콘택홀 측벽 및 저면에 발생된 카본 계열의 잔류물을 제거하기 위해 레이저를 조사하는 단계; 및Irradiating a laser on the resultant substrate on which the contact hole is formed to remove carbon-based residues generated on the sidewalls and the bottom of the contact hole when the photoresist pattern is removed; And 상기 콘택홀을 매립하도록 상기 저유전막 상에 금속막을 형성하는 단계;Forming a metal film on the low dielectric layer to fill the contact hole; 를 포함하는 것을 특징으로 하는 반도체 소자의 제조방법. Method of manufacturing a semiconductor device comprising a. 제 1 항에 있어서,The method of claim 1, 상기 레이저를 조사하는 단계는, 레이저만 조사하는 제1단계와 레이저의 조사와 함께 퍼지 가스를 플로우시키는 제2단계로 수행하는 것을 특징으로 하는 반도체 소자의 제조방법.The irradiating of the laser may include performing the first step of irradiating only the laser and the second step of flowing purge gas together with the irradiation of the laser. 제 2 항에 있어서,The method of claim 2, 상기 제1단계는, 50mTorr∼1Torr의 압력과 25∼100℃의 온도에서 10∼50W의 파워를 가하면서 수행하는 것을 특징으로 하는 반도체 소자의 제조방법.The first step is a method of manufacturing a semiconductor device, characterized in that performed while applying a power of 10-50W at a pressure of 50mTorr ~ 1 Torr and a temperature of 25 ~ 100 ℃. 제 3 항에 있어서,The method of claim 3, wherein 상기 제1단계의 파워는 50∼350회의 펄스로 가하는 것을 특징으로 하는 반도체 소자의 제조방법.And the power of the first step is applied in 50 to 350 pulses. 제 2 항에 있어서,The method of claim 2, 상기 제2단계는, 1Torr∼100Torr의 압력과 100∼250℃의 온도에서 30∼100W의 파워를 가하면서 수행하는 것을 특징으로 하는 반도체 소자의 제조방법.The second step is a method of manufacturing a semiconductor device, characterized in that performed while applying a power of 30 ~ 100W at a pressure of 1 Torr ~ 100 Torr and a temperature of 100 ~ 250 ℃. 제 5 항에 있어서,The method of claim 5, wherein 상기 제2단계의 파워는 300∼6000회의 펄스로 가하는 것을 특징으로 하는 반도체 소자의 제조방법.The second step of power is a semiconductor device manufacturing method, characterized in that for applying a pulse of 300 to 6000 times. 제 2 항에 있어서,The method of claim 2, 상기 제2단계는 퍼지 가스로서 Ar 가스와 N2 가스를 플로우시키면서 수행하는 것을 특징으로 하는 반도체 소자의 제조방법.The second step is a semiconductor device manufacturing method, characterized in that performed while flowing Ar gas and N 2 gas as a purge gas. 제 7 항에 있어서,The method of claim 7, wherein 상기 Ar 가스와 N2 가스의 유량은 500∼3000sccm인 것을 특징으로 하는 반도체 소자의 제조방법.The flow rate of the Ar gas and N 2 gas is a manufacturing method of a semiconductor device, characterized in that 500 to 3000sccm.
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