KR20080018414A - Method of fabricating semiconductor devices - Google Patents
Method of fabricating semiconductor devices Download PDFInfo
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- KR20080018414A KR20080018414A KR1020060080481A KR20060080481A KR20080018414A KR 20080018414 A KR20080018414 A KR 20080018414A KR 1020060080481 A KR1020060080481 A KR 1020060080481A KR 20060080481 A KR20060080481 A KR 20060080481A KR 20080018414 A KR20080018414 A KR 20080018414A
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 20
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 8
- 239000010410 layer Substances 0.000 claims abstract description 39
- 238000000034 method Methods 0.000 claims abstract description 32
- 229910052751 metal Inorganic materials 0.000 claims abstract description 30
- 239000002184 metal Substances 0.000 claims abstract description 30
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 claims abstract description 28
- 239000011229 interlayer Substances 0.000 claims abstract description 19
- 239000000758 substrate Substances 0.000 claims abstract description 19
- 229910052721 tungsten Inorganic materials 0.000 claims abstract description 17
- 239000010937 tungsten Substances 0.000 claims abstract description 17
- 238000000059 patterning Methods 0.000 claims description 16
- 238000005530 etching Methods 0.000 claims description 14
- 239000004020 conductor Substances 0.000 claims description 10
- 230000004888 barrier function Effects 0.000 claims description 9
- 239000000460 chlorine Substances 0.000 claims description 3
- ZAMOUSCENKQFHK-UHFFFAOYSA-N Chlorine atom Chemical compound [Cl] ZAMOUSCENKQFHK-UHFFFAOYSA-N 0.000 claims description 2
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 claims description 2
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 claims description 2
- 229910052782 aluminium Inorganic materials 0.000 claims description 2
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical group [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims description 2
- 229910052801 chlorine Inorganic materials 0.000 claims description 2
- 239000010936 titanium Substances 0.000 claims description 2
- 229910052719 titanium Inorganic materials 0.000 claims description 2
- FAQYAMRNWDIXMY-UHFFFAOYSA-N trichloroborane Chemical compound ClB(Cl)Cl FAQYAMRNWDIXMY-UHFFFAOYSA-N 0.000 claims description 2
- 238000010891 electric arc Methods 0.000 abstract description 11
- 230000007547 defect Effects 0.000 abstract description 6
- 230000015572 biosynthetic process Effects 0.000 abstract description 5
- 238000001020 plasma etching Methods 0.000 abstract description 4
- 239000002245 particle Substances 0.000 description 4
- 238000009825 accumulation Methods 0.000 description 2
- 230000018109 developmental process Effects 0.000 description 2
- 230000010354 integration Effects 0.000 description 2
- 238000002955 isolation Methods 0.000 description 2
- 238000001465 metallisation Methods 0.000 description 2
- 229920002120 photoresistant polymer Polymers 0.000 description 2
- 238000011109 contamination Methods 0.000 description 1
- 230000003247 decreasing effect Effects 0.000 description 1
- 238000007599 discharging Methods 0.000 description 1
- 238000010030 laminating Methods 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 150000002739 metals Chemical class 0.000 description 1
- 230000002093 peripheral effect Effects 0.000 description 1
- 230000007261 regionalization Effects 0.000 description 1
- 238000009751 slip forming Methods 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
- H01L21/0271—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers
- H01L21/0273—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers characterised by the treatment of photoresist layers
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/321—After treatment
- H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
- H01L21/32133—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only
- H01L21/32135—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/321—After treatment
- H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
- H01L21/32139—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer using masks
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
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- Microelectronics & Electronic Packaging (AREA)
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Abstract
Description
도1 내지 도3은 종래의 반도체 장치 형성 과정에서 아크 방전이 발생하는 한 예를 나타내는 공정 단면도이다. 1 to 3 are process cross-sectional views illustrating an example in which arc discharge occurs in a conventional semiconductor device formation process.
도4 내지 도6은 본 발명의 일 실시예에 따른 중요 공정 단계를 나타내는 공정 단면도이다. 4 through 6 are process cross-sectional views illustrating important process steps according to an embodiment of the present invention.
본 발명은 반도체 장치 제조방법에 관한 것으로, 보다 상세하게는 반도체 장치The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a semiconductor device.
반도체 장치는 반도체 기판을 이용하여 전자, 전기 소자를 형성하고, 그 위쪽에 절연막, 반도체막, 도체막을 적층 및 패터닝하여 다른 전기 소자나 이미 형성된 소자들을 연결하여 회로를 구성할 배선을 형성함으로써 이루어진다. A semiconductor device is formed by forming electronic and electrical elements using a semiconductor substrate, and forming an interconnection to form a circuit by connecting and insulating other electrical elements or already formed elements by stacking and patterning an insulating film, a semiconductor film, and a conductor film thereon.
반도체 장치의 소자 고집적화를 위하여 소자나 배선의 크기는 점차 줄어들고 있으며, 그에 따라 반도체 장치 형성을 위한 각 공정의 디자인 룰(design rule)로 점차 엄격해지고 있다.In order to increase the integration of devices in semiconductor devices, the size of devices and wirings is gradually decreasing, and accordingly, design rules of respective processes for forming semiconductor devices are gradually becoming strict.
소자 고집적화를 위한 한 방법으로 다층 배선이 많이 사용되고, 다층 배선을 형성하기 위해 반도체 장치의 절연막 및 도체막 적층 및 패터닝 회수도 늘어나고 있다. 복수 층을 이루는 금속 배선의 상층과 하층 배선 패턴은 그 사이의 층간 절연막에 비아 콘택홀을 형성하고 콘택홀을 도체 플러그로 채우는 방식으로 통상 연결된다. As one method for high integration of devices, multilayer wiring is widely used, and the number of insulating and conductor film stacking and patterning of semiconductor devices is increasing to form multilayer wiring. Upper and lower wiring patterns of a plurality of metal wirings are usually connected in such a manner as to form a via contact hole in an interlayer insulating film therebetween and fill the contact hole with a conductor plug.
비아 콘택홀을 형성하기 위한 식각으로 식각 효율성을 높일 수 있는 플라즈마 식각이 흔히 사용된다. 그런데 하층 배선 패턴으로 고립된 배선 패턴(floating metal)이 있는 경우, 배선 패턴에 전하가 축적되어 아크 방전을 일으킬 염려가 커진다. 가령, 플라즈마가 인가되는 공정에서 플라즈마의 영향으로 고립된 패턴에 한 극성의 전하가 축적되거나, 플라즈마가 균일하지 못하여 부분적으로 전기적 불균형이 발생하는 경우 배선 패턴별로 다른 전하가 축적되고, 이들 고립 배선 사이에 전위차가 커져 아크 방전이 발생할 수 있다. Plasma etching, which can increase the etching efficiency, is commonly used as an etching to form a via contact hole. However, when there is a wiring pattern (floating metal) isolated by the lower wiring pattern, there is a high possibility that electric charges will accumulate in the wiring pattern and cause arc discharge. For example, in a process in which plasma is applied, charges of one polarity accumulate in the isolated pattern due to the influence of the plasma, or when the plasma is not uniform and partial electric imbalance occurs, different charges are accumulated for each wiring pattern. The potential difference may increase, resulting in arc discharge.
아크 방전이 발생하는 경우, 패턴이 파손되거나, 주변 소자가 파괴될 수 있다. 방전 과정에서 파티클이 발생하여 다른 부분에 위치하면서 패턴 사이의 단락 등의 문제를 일으킬 수 있다. 결국 반도체 장치 불량이 발생하거나, 반도체 장치에서 소자 신뢰성이 저하되는 문제가 있다.When arc discharge occurs, the pattern may be broken or the peripheral elements may be broken. Particles may be generated during the discharging process and may be located in different parts, causing problems such as short circuits between patterns. As a result, semiconductor device defects may occur or device reliability may be degraded in the semiconductor device.
도1 내지 도3은 종래의 반도체 장치 형성 과정에서 아크 방전이 발생하는 한 예를 나타내는 공정 단면도이다. 도1을 참조하면, 기판(1) 상의 제1 층간 절연막(10)에 콘택 홀을 형성한 후에 베리어 메탈(Barrier metal:21,23) 및 플러그 금속인 텅스텐층(25)을 증착한다. 도2와 같이 텅스텐 에치백(Etch-back) 공정을 수행하면 식각 장비의 클램프 링(Clamp ring)과 같은 파지 기구에 의해 웨이퍼 에 지(wafer edge) 일부 영역에 텅스텐층이 미약하나마 제거되지 않고 레지듀(253)로 남게 될 수 있다. 에치백이 균일하지 못한 경우에도 부분적으로 텅스텐 레지듀(253)가 존재할 수 있다. 도3과 같이 후속의 금속 배선 및 제2 층간 절연막 적층 후 비아홀 형성을 위한 플라즈마 에치가 이루어질 때 플라즈마의 영향으로 하부의 금속 배선 패턴(31,33,35) 가운데 고립된 금속 배선 패턴(35)에 전하가 축적되면 주변의 얇은 절연막(40)을 통해 외부와 방전을 일으키면서 주변이 손상되고, 파티클이 양산되는 아크 결함을 일으킨다. 1 to 3 are process cross-sectional views illustrating an example in which arc discharge occurs in a conventional semiconductor device formation process. Referring to FIG. 1, after forming contact holes in the first
본 발명은 상술한 종래 반도체 장치 형성 방법에서의 아크 발생의 문제점을 완화시키기 위한 것으로, The present invention is to alleviate the problem of arc generation in the aforementioned method of forming a semiconductor device,
반도체 제조 시 아크 결함(Arcing defect)으로 인한 수율 저하를 막고, 아크로 인한 파티클 양산과 파티클에 의한 기판 오염을 방지하기 위한 것이다. This is to prevent yield decrease due to arcing defects in semiconductor manufacturing, and to prevent mass production of particles due to arc and substrate contamination by particles.
상기 목적을 달성하기 위한 본 발명 방법은, 소자가 형성된 공정기판 위로 제1 층간 절연막을 형성하고 패터닝하여 콘택홀을 형성하는 단계, 콘택홀을 채우는 텅스텐막을 적층하는 단계, 에치백을 실시하여 콘택홀을 채우는 텅스텐 플러그를 형성하는 단계, 텅스텐 플러그가 형성된 기판 위에 도체층을 형성하고 패터닝하여 배선 패턴을 형성하는 단계, 제2 층간 절연막을 적층하고 패터닝하여 비아 홀을 형성하는 단계를 구비하며, 도체층을 형성하고 패터닝하여 배선 패턴을 형성하는 단계에서 패터닝을 위한 노광 공정에서 웨이퍼 에지부에 대한 에지부 노광을 실시하 는 단계를 구비하는 것을 특징으로 한다.In order to achieve the above object, the present invention provides a method of forming a contact hole by forming and patterning a first interlayer insulating film on a process substrate on which a device is formed, stacking a tungsten film filling a contact hole, and performing etch back to form a contact hole. Forming a tungsten plug which fills the gap, forming and patterning a conductor layer on the substrate on which the tungsten plug is formed, and forming a via hole by laminating and patterning a second interlayer insulating film; And forming an interconnection pattern to form an interconnection pattern, and performing edge portion exposure to the wafer edge portion in an exposure process for patterning.
본 발명의 에치백 단계에서 웨이퍼 에지에는 텅스텐 레지듀가 형성되기 쉬우나, 에치부 노광을 통해 에지부 전체에는 배선 패터닝 식각 단계에서 도체층 식각을 위한 에천트가 계속 작용하여 고립된 배선 패턴 형성이 없어지고, 텅스텐 레지듀를 제거하는 역할을 할 수 있다. In the etching back step of the present invention, tungsten residue is easily formed on the wafer edge, but the etchant for etching the conductor layer is continuously formed on the entire edge part through the etching part exposure so that there is no isolated wiring pattern formation. And remove tungsten residues.
본 발명에서 텅스텐막을 적층하는 단계에는 텅스텐막 적층 전에 티타늄이나티타늄 질화막과 같은 베리어 메탈층이 먼적 기판에 콘포말하게 형성되는 부속 단계가 구비될 수 있으며, 이들 베리어 메탈층 가운데 제1 층간 절연막 위에 형성된 부분은 텅스텐 에치백이 이루어지는 플러그 형성 단계에서 제거되거나, 도체층 배선 패턴 형성을 위한 식각 단계에서 대부분 제거될 수 있다. In the present invention, the step of stacking the tungsten film may include an additional step in which a barrier metal layer such as titanium or titanium nitride film is conformally formed on a remote substrate before the tungsten film is laminated, and formed on the first interlayer insulating film among the barrier metal layers. The portion may be removed in the plug forming step in which the tungsten etch back is made or mostly removed in the etching step for forming the conductor layer wiring pattern.
이하 도면을 참조하면서 실시예를 통해 본 발명을 보다 상세히 설명하기로 한다.Hereinafter, the present invention will be described in more detail with reference to the accompanying drawings.
본 발명은 초기 단계에서 도1 및 도2에 나타난 종래의 기술과 같이 이루어진다. 즉, 제1 층간 절연막에 콘택 홀을 형성한 후에 베리어 메탈(Barrier metal) 및 플러그 금속인 텅스텐을 증착한다. 그리고, 텅스텐 에치백(Etch-back) 공정을 수행한다. 이때 웨이퍼 에지(wafer edge) 일부 영역에 텅스텐층이 미약하나마 제거되지 않고 레지듀로 남을 수 있다. 에치백이 균일하지 못한 경우에도 부분적으로 텅스텐 레지듀가 존재할 수 있다. The present invention is accomplished in the early stages as in the prior art shown in FIGS. 1 and 2. That is, after forming contact holes in the first interlayer insulating film, a barrier metal and tungsten, which is a plug metal, are deposited. Then, a tungsten etch-back process is performed. At this time, although the tungsten layer is weakly removed in a portion of the wafer edge, it may remain as a residue. Tungsten residues may also be present, even in some cases where the etch back is uneven.
이어서 종래와 달리 4도와 같이 배선 메탈층을 적층한 뒤 웨이퍼 에지 노광 (WEE)및 현상을 실시하여 포토레지스트층(160) 가운데 에지부를 제거한다. 에지부 제거는 2 내지 3mm 정도의 폭으로 이루어질 수 있다. Subsequently, unlike the prior art, the wiring metal layer is stacked as shown in FIG. 4, and then the edge portion of the
이어서 메탈 배선층(130) 패턴닝을 위한 노광 및 현상을 실시하여 도5와 같은 포토레지스트 패턴(165)을 형성하고, 식각을 실시한다. 이 단계에서 종래에는 존재하던 에지부의 메탈 배선 고립 패턴은 형성되지 않으며, 메탈 배선층(130) 오버 에치를 통해 베리어 메탈층((21,23)을 제1 층간 절연막(10) 상부에서 제거하는 과정에서 기판 에지부의 텅스텐 레지듀(253)에 대한 식각도 이루어져 대부분이 제거된다. 즉, 종래에 아크 방전을 일으키는 원인이 되었던 고립된 메탈 배선 패턴과 텅스텐 레지듀가 공정 기판에 존재하지 않게 된다.Subsequently, exposure and development for patterning the
배선 메탈층을 식각하기 위한 에천트로는 배선 메탈층이 주로 알미늄이 되므로 염소(Cl2)나 삼염화 보론(BCl3)이 사용될 수 있다. 이들 에천트는 텅스텐 레지듀에 대한 식각 선택비는 높지 않으나, 텅스텐 하부의 베리어 메탈까지 오버 에치하는 시간이 길어지므로 텅스텐 레지듀를 제거할 정도의 식각력을 가질 수 있다. As an etchant for etching the wiring metal layer, since the wiring metal layer is mainly aluminum, chlorine (Cl 2 ) or boron trichloride (BCl 3 ) may be used. These etchant may not have a high etching selectivity to the tungsten residue, but may have an etching force enough to remove the tungsten residue due to a long time for overetching the barrier metal under the tungsten.
이어서 이루어지는 공정은 종래의 공정과 유사하게 이루어질 수 있다. 즉, 메탈 배선 패턴(131,133)이 형성된 기판 위로 전체적인 제2 층간 절연막(140) 적층이 이루어진다. 그리고, 제2 층간 절연막(140)에 대한 패터닝 작업을 통해 메탈 배선 패턴의 일부를 드러내는 비아 홀(150)이 형성된다. Subsequent processes may be similar to conventional processes. That is, the entire second interlayer insulating layer 140 is stacked on the substrate on which the metallization patterns 131 and 133 are formed. The via hole 150 exposing a part of the metal wiring pattern is formed through the patterning operation on the second interlayer insulating layer 140.
이러한 패터닝 작업이 이루어지는 과정에서 종래에는 제2 층간 절연막에 대한 플라즈마 인가 식각이 있을 때 고립 패턴 및 텅스텐 레지듀에 전하가 축적되고, 전위가 높아져 아크 방전이 발생되었으나, 본 실시예에서는 고립 패턴 및 텅스텐 레지듀가 없어 전하의 축적 및 방전이 이루어지지 않게 된다.In the process of performing the patterning operation, conventionally, when the plasma is applied to the second interlayer insulating film, charges are accumulated in the isolation pattern and the tungsten residue, and the electric potential is increased to generate the arc discharge. There is no residue, which prevents charge accumulation and discharge.
이상의 실시예에서는 제2 층간 절연막 형성 및 패터닝 시의 플라즈마 식각에서 아크 방전이 방지되는 것을 주로 설명하였으나, 이보다 상층의 단계에서 층간 절연막에 비아홀을 형성하는 단계들에서도 동일한 방식으로 본 발명을 적용하여 고립된 메탈 배선 및 텅스텐 레지듀로 인한 전하 축적과 아크 방전을 방지할 수 있게 된다.In the above embodiment, the arc discharge is mainly prevented from the plasma etching during the formation and patterning of the second interlayer insulating film. However, in the step of forming the via hole in the interlayer insulating film in the upper layer, the present invention is applied in the same manner. Metal wiring and tungsten residues prevent charge accumulation and arc discharge.
이상에서 제시된 실시예에서 반도체 장치의 층간 절연막이나 금속층, 베리어 메탈층은 예시적으로 제시된 것이므로 다른 재질로 이들 층이 이루어지는 것을 배재하는 것은 아니다.In the above-described embodiment, since the interlayer insulating film, the metal layer, and the barrier metal layer of the semiconductor device are provided by way of example, they do not exclude the formation of these layers from other materials.
본 발명에 따르면, 종래의 반도체 장치 제조 공정에서 비아홀 형성을 위한 플라즈마 에칭 과정에서 발생하던 아크 방전을 억제시켜 기판의 아크 결함이 생기는 것을 방지할 수 있다. According to the present invention, the arc discharge generated during the plasma etching process for forming the via hole in the conventional semiconductor device manufacturing process can be suppressed to prevent the occurrence of arc defects on the substrate.
따라서, 아크 결함 발생으로 인한 반도체 장치 생산 수율 저하를 막아 공정 능률을 높여주고, 제품 신뢰성, 안정성을 높이는 효과가 있다. Therefore, it is possible to prevent a decrease in the yield of semiconductor device production due to the occurrence of arc defects, thereby improving process efficiency and improving product reliability and stability.
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| CN108122894B (en) * | 2016-11-29 | 2019-12-27 | 中芯国际集成电路制造(上海)有限公司 | Method for improving arc discharge defect of MIM capacitor |
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