JP5044930B2 - MIS type capacitor manufacturing method - Google Patents

Description

The present invention, in producing a MIS (Metal Insulator Semiconductor) capacitor, a method of manufacturing a M IS capacitor capable of preventing the dielectric breakdown caused by charge-up phenomenon.

  FIG. 3 is a cross-sectional view showing the structure of a conventional MIS capacitor. In the MIS capacitor 10, a predetermined region on the upper surface of the P-type silicon substrate 11 is doped with an N + type region 12, and a dielectric film 13 is formed in a predetermined region on the upper surface of the N + type region 12. A thermal oxide film 14 is formed on the upper surface. Further, a predetermined region protrudes from the thermal oxide film 14 on the dielectric film 13 to form an upper electrode wiring 15, and a lower electrode wiring 17 is formed on the thermal oxide film 14 while being insulated from the upper electrode wiring 15. .

The lower electrode wiring 17 is formed in a connected state to the N + type region 12 through a via (via hole) 16 penetrating the thermal oxide film 14. The upper electrode wiring 15 and the lower electrode wiring 17 are formed using a conductive material such as aluminum. The upper electrode wiring 15 and the lower electrode wiring 17 are also referred to as upper and lower electrodes 15 and 17.
In such a structure, a portion surrounded by a broken line frame is a MIS structure portion 18 having a three-layer structure including a metal formed by the upper electrode wiring 15, an insulator formed by the dielectric film 13, and a semiconductor formed by the N + type region 12.

Next, a manufacturing method for forming a plurality of layers of wiring on the MIS capacitor 10 having such a structure will be described with reference to FIGS.
As shown in (a), in the capacitor electrode formation step, the MIS capacitor 10 is formed.
As shown in (b), in the first TEOS (Tetra Ethyl Ortho Silicate) interlayer film forming step by plasma CVD (Chemical Vapor Deposition), the first MIS type capacitor 10 formed in (a) is covered with the first surface. The TEOS interlayer film 21 is formed.

As shown in (c), vias 22 are formed in the first TEOS interlayer film 21 in the interlayer via formation step. This is done by forming a photomask (not shown) having a via 22 opening on the first TEOS interlayer 21 which is an insulating film between wirings, and removing the TEOS interlayer 21 in the opening by etching. Then, it forms by removing a photomask.
As shown in (d), in the second wiring generation film process, a wiring generation film 23 is formed on the first TEOS interlayer film 21 in which the vias 22 are formed. The wiring generation film 23 is also introduced into the via 22.

As shown in (e), in the second wiring formation step, the wiring generation film 23 is etched to form the second wiring 23a having a predetermined layout pattern.
As shown in (f), in the second TEOS interlayer film forming step, the second TEOS interlayer film 24 is formed on the entire surface covering the second wiring 23a, and the MIS type capacitor is manufactured.
As this type of conventional MIS type capacitor, there are those described in Patent Documents 1 and 2, for example.
Japanese Patent Laid-Open No. 62-154661 JP 2000-150790 A

  However, in the conventional MIS type capacitor, in the TEOS interlayer film forming step (b), the upper electrode wiring 15 is charged up by plasma irradiation at the initial stage of TEOS film formation, and the dielectric film is equal to the number of charges thus charged up. Charges having different polarities are stored immediately below 13. Due to this phenomenon, a potential difference is generated between the upper and lower electrodes 15, 17, and when this potential exceeds the dielectric breakdown potential of the dielectric film 13, dielectric breakdown has occurred.

There are mainly the following two measures for preventing this dielectric breakdown.
The first is a method that does not cause charge-up. Specific examples of this method include improvement of the equipment mechanism for controlling the plasma density that is correlated with charge-up and optimization of manufacturing conditions.
The second is a method of forming a dielectric film that can withstand charge-up. Specific examples of this method include changing the dielectric material and increasing the thickness of the dielectric film. Dielectric materials generally used for MIS type capacitors include silicon oxide films, nitride films, and metal oxide films. This is a measure to change the material and film thickness according to the specifications of the capacitor capacity and withstand voltage.

However, when considering a method that does not cause the first charge-up, it is necessary to verify the correlation with the element non-defective rate for each improvement of the equipment mechanism and manufacturing conditions. Necessary. In addition, the optimized equipment and manufacturing conditions do not necessarily match elements with different specifications for each product.
In addition, when considering a second dielectric material and a method of changing the thickness, in order to apply a material that meets the specifications, a film that can withstand changes in manufacturing equipment and manufacturing conditions, and withstands dielectric breakdown. It is necessary to verify the thickness by experiment, and these also require enormous costs and a countermeasure period.

The present invention, such has been made in view of the problems, the M IS-type capacitor due to charge-up efficiently low cost without a long-term measures periods Ru can prevent dielectric breakdown of the dielectric The object is to provide a manufacturing method.

In order to achieve the above object, a method of manufacturing a MIS capacitor according to claim 1 of the present invention includes forming a semiconductor layer on a semiconductor substrate, forming a first electrode on the upper surface via a dielectric film, A method for manufacturing a MIS capacitor , wherein a second electrode connected to the semiconductor layer in an insulated state from the first electrode is formed on an insulating film formed outside a region where the dielectric film is formed. And forming the short-circuit wiring on the insulating film for connecting the first and second electrodes to the conductive state when forming the first and second electrodes; and An insulating layer for forming a multilayer wiring structure is formed on the short-circuit wiring, the first electrode, and the second electrode, and an opening is formed in the insulating layer together with a via for connecting upper and lower wirings, Conductive after formation of via and said opening When forming a wiring layer using a material and etching the wiring layer, the short-circuit wiring exposed from the opening is etched so that the first and second electrodes are in an insulating state. And a step of dividing .

  According to this method, when an insulating layer for forming a multilayer wiring structure is formed on the upper surface of the MIS capacitor after the formation of the first and second electrodes, the first irradiation is performed by plasma irradiation for forming the insulating layer. The charge is charged up on the electrode, and the charge is stored directly under the dielectric film. However, since this accumulated charge flows from the second electrode through the semiconductor layer to the first electrode via the short-circuit wiring, the potential difference between the first and second electrodes becomes substantially zero, so that the dielectric as in the prior art The body film will not break down.

According to a second aspect of the present invention, there is provided a method for manufacturing a MIS capacitor according to the first aspect of the present invention, wherein a layout of a photomask for transferring a pattern of the first and second electrodes is formed when the short-circuit wiring is formed. Is changed so that the pattern of the short-circuit wiring can also be transferred, and the first and second electrodes and the short-circuit wiring are formed by the changed photomask.
According to this method, when the short-circuit wiring is formed, the photomask can be slightly changed and can be realized by the same manufacturing process as the conventional method. .

According to a third aspect of the present invention, there is provided a method for manufacturing an MIS capacitor according to the first or second aspect , wherein the via is formed when the opening is formed in the insulating layer together with the via for connecting the upper and lower wirings. The layout of the photomask is changed to a layout that can also form an opening penetrating at the position of the short-circuit wiring, and the via and the opening are formed by the changed photomask, and the via and the opening are formed. in forming the wiring by the etching after, characterized in that said first and second electrodes of the shorting bar to remove the wiring layer filled in the opening is divided so that the insulating state And
According to this method, even when the short-circuit wiring is divided so that the first and second electrodes are in an insulated state after the short-circuit wiring is formed, the photomask can be slightly changed in the same manufacturing process as before. It can be divided efficiently with almost no increase in cost.

According to a fourth aspect of the present invention, there is provided a method for manufacturing a MIS capacitor according to the third aspect, wherein the wiring layer filled in the opening and the etching at the time of dividing the short-circuited wiring are performed in the fourth step. , Dry etching or etchant wet etching is used.
According to this method, since the opening is filled with the wiring layer, the wiring layer in this portion is more than twice as thick as the wiring layer formed on the insulating layer. In addition, the etching time needs to be about 2.5 times longer than usual, and when etching is performed as usual, the necessary portion of the wiring layer may be damaged, but if dry etching or etchant wet etching is used, the wiring layer is necessary. It becomes possible to remove the short-circuit wiring properly and divide without damaging the portion.

  As described above, according to the present invention, there is an effect that dielectric breakdown due to charge-up can be prevented efficiently and at low cost without requiring a long measure period.

Hereinafter, embodiments of the present invention will be described with reference to the drawings. However, parts corresponding to each other in all the drawings in this specification are denoted by the same reference numerals, and description of the overlapping parts will be omitted as appropriate.
1A and 1B show a structure of a MIS capacitor according to an embodiment of the present invention, in which FIG. 1A is a plan view and FIG.

The MIS capacitor 30 shown in FIG. 1 is different from the conventional MIS capacitor 10 in that an upper electrode wiring (first electrode) 15 and a lower electrode wiring (second electrode) are formed on a thermal oxide film (insulating film) 14. The short circuit wiring (short circuit wiring) 31 for connecting the electrode 17 to the conductive state is provided.
The short circuit wiring 31 has a U shape connecting one end of the lower electrode wiring 17 and the end of the upper electrode wiring 15 close to the one end, and one side of the U shape is a P-type silicon substrate (semiconductor substrate). 11 in a state of being arranged in the vicinity of one side.

A method for forming the short circuit wiring 31 and a manufacturing method for forming a plurality of layers of wiring on the MIS type capacitor 30 after forming the short circuit wiring 31 are shown in FIGS. The description will be given with reference.
As shown to (a), the short circuit wiring 31 is formed in a capacitor electrode formation process. The wiring pattern for forming the short circuit wiring 31 is changed by changing the layout of the photomask for transferring the pattern of the upper electrode wiring 15 and the lower electrode wiring 17 so that the pattern of the short circuit wiring 31 can also be transferred. Do. As a result, the wiring pattern can be realized in the same capacitor electrode forming process as in the prior art, and the number of manufacturing processes can be realized in the same number as in the prior art.

As shown in (b), in the first TEOS interlayer film forming step, a first TEOS interlayer film (insulating layer) 21 is formed on the entire upper surface of the MIS capacitor 30 formed in the step (a). Accordingly, the short circuit wiring 31 is also covered with the first TEOS interlayer film 21.
In this TEOS interlayer film forming step, conventionally, as described above, charges are charged up in the upper electrode wiring 15 by plasma irradiation at the initial stage of TEOS film formation, whereby charges of different polarities are accumulated directly under the dielectric film 13, The dielectric film 13 was broken down due to the potential difference generated between the upper and lower electrodes 15 and 17.

However, in this manufacturing method, the electric charge accumulated immediately below the dielectric film 13 passes through the lower electrode wiring 17 and flows to the upper electrode wiring 15 via the short circuit wiring 31, so that the potential difference between the upper and lower electrodes 15 and 17 is reduced. Nearly zero. Therefore, the dielectric film 13 does not break down.
Next, as shown in (c), vias 22 are formed in the first TEOS interlayer film 21 in the interlayer via formation step. At this time, an opening 33 for removing the short circuit wiring 31 is formed in the first TEOS interlayer film 21. The short circuit wiring 31 may be completely removed, but may be performed so that the short circuit wiring 31 is divided and the upper and lower electrodes 15 and 17 are insulated.

  Further, the opening 33 is formed by changing the layout of the photomask for opening the via 22 so that the pattern of the opening 33 can be transferred. Thus, the TEOS interlayer film 21 in the two opening forming portions is removed by etching, and then the photomask is removed to form the via 16 and the opening 33. That is, the opening 33 can be formed by the same interlayer via forming process as that of the prior art.

Next, as shown in (d), in the second wiring generation film step, the wiring generation film 23 is formed on the first TEOS interlayer film 21 in which the via 22 and the opening 33 are formed. The wiring generation film 23 is also introduced into the via 22 and the opening 33.
Next, as shown in (e), in the second wiring formation step, the wiring generation film (wiring layer) 23 is etched to form a second wiring 23a having a predetermined layout pattern. The short circuit wiring 31 is also removed together with the wiring generation film 23 filled in the portion 33.

  The metal film thickness of the opening 33 before the removal is more than twice the metal film thickness of the wiring generation film 23 formed on the first TEOS interlayer film 21. Therefore, the etching time including the margin is set to about 2.5 times the conventional time. As an etching method, dry etching or etchant wet etching is used. The short circuit wiring 31 can be removed by etching using this method. After this removal, an opening 34 is formed.

Then, as shown in (f), in the second TEOS interlayer film forming step, the second TEOS interlayer film 24 is formed on the entire surface covering the second wiring 23a, and the MIS type capacitor is manufactured. However, the film agent is also filled in the opening 34 when the second TEOS interlayer film 24 is formed.
According to the MIS capacitor of this embodiment, since the short circuit wiring 31 for connecting the upper and lower electrodes 15 and 17 to the conductive state is provided on the thermal oxide film 14, the upper and lower electrodes 15 and 17 are formed after the formation. The following effects are produced when the first TEOS interlayer film 21 is formed on the upper surface of the capacitor.

  That is, even if charges are accumulated in the upper electrode wiring 15 due to plasma irradiation in the initial stage of TEOS film formation, and charges are accumulated immediately below the dielectric film 13, this accumulated charge passes through the N + type region 12 and lower electrode wiring. Since the current flows from 17 to the upper electrode wiring 15 via the short circuit wiring 31, the potential difference between the upper and lower electrodes 15 and 17 becomes substantially zero, and the dielectric film 13 does not break down as in the prior art.

  When the short circuit wiring 31 is formed, the layout of the photomask for transferring the pattern of the upper and lower electrodes 15 and 17 may be changed so that the pattern of the short circuit wiring 31 can be transferred. When the upper and lower electrodes 15 and 17 are formed in the electrode forming step, the short circuit wiring 31 can also be formed. Therefore, it can be realized with the same number of manufacturing steps as in the prior art, and the photomask can be slightly changed, so that the cost can be hardly increased and the photomask can be formed efficiently.

Further, even when the short circuit wiring 31 is divided so that the upper and lower electrodes 15 and 17 are in an insulated state after the short circuit wiring 31 is formed, in the same manufacturing process as in the prior art, the photomask is slightly changed and the wiring metal is used. Since it is only necessary to change the etching time of a certain wiring generation film 23, the cost is hardly increased, and it can be divided efficiently.
Further, the short circuit wiring 31 may be divided by burning out the exposed short circuit wiring 31 with a laser beam in the interlayer via forming step (c). Furthermore, the short circuit wiring 31 may be cut when the chip is divided by dicing in the final process. In this way, the short circuit wiring 31 can be removed efficiently and at a low cost without changing the manufacturing process as in the prior art.

The structure of the MIS type | mold capacitor | condenser which concerns on embodiment of this invention is shown, (a) is a top view, (b) is A1-A2 sectional drawing shown to (a). It is explanatory drawing of the manufacturing process at the time of forming the wiring of several layers on the MIS type | mold capacitor of the said embodiment. It is sectional drawing which shows the structure of the conventional MIS type | mold capacitor. It is explanatory drawing of the manufacturing process at the time of forming the multilayer wiring on the conventional MIS type capacitor.

Explanation of symbols

11 P-type silicon substrate 12 N + type region 13 Dielectric film 14 Thermal oxide film 15 Upper electrode wiring 1
16, 22 Via 17 Lower electrode wiring 18 MIS structure 21 First TEOS interlayer film 23 Wiring generation film 23a Second wiring 24 Second TEOS interlayer film 30 MIS type capacitor 31 Short circuit wiring 33, 34 Opening

Claims (4)

The semiconductor layer is formed on a semiconductor substrate, in the upper surface through the dielectric film forming a first electrode, a second electrode connected to the semiconductor layer between the first electrode insulated, the In a method of manufacturing a MIS capacitor formed on an insulating film formed outside a region where a dielectric film is formed ,
Forming a short-circuit wiring on the insulating film to connect the first and second electrodes to a conductive state when forming the first and second electrodes;
An insulating layer for forming a multilayer wiring structure is formed on the short-circuited wiring, the first electrode, and the second electrode formed in the step, and an opening is formed in the insulating layer together with a via for connecting upper and lower wirings. Forming a wiring layer made of a conductive material after forming the via and the opening, and etching the wiring layer to form the wiring. Dividing by etching so that the first and second electrodes are in an insulating state;
A method for manufacturing a MIS type capacitor, comprising:   When forming the short-circuit wiring, the layout of the photomask for transferring the pattern of the first and second electrodes is changed so that the pattern of the short-circuit wiring can also be transferred, and the changed photomask allows the 2. The method for manufacturing a MIS capacitor according to claim 1, wherein the first and second electrodes and the short-circuit wiring are formed. When the opening is formed in the insulating layer together with the via for connecting the upper and lower wirings, the layout of the photomask for forming the via is changed to a layout that can also form the opening penetrating the position of the short-circuit wiring. Forming the via and the opening by the modified photomask;
In forming the wiring by the etching after formation of the vias and the opening, the first and second electrodes of the shorting bar to remove the wiring layer filled in the opening and insulated The manufacturing method of the MIS type capacitor according to claim 1, wherein the MIS type capacitor is divided. The etching in the cutting removal and the shorting bar prior Symbol wiring layer filled in the opening, a manufacturing method of a MIS capacitor according to claim 3, characterized by using dry etching or edge Chang wet etching .

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