KR20080009418A - Test apparatus for detecting the system fail and test method thereof - Google Patents

Abstract

A mounting test apparatus for detecting system fail and a test method thereof are provided to detect accurate information of a memory chip causing an error as reducing mounting test cost and time in a system level, by testing a plurality of memory modules in parallel at the same time. A main board comprises at least more than two memory modules as including a first and a second memory module(130,120) including a number of memory chips(132,134,136,138). A test unit(150) performs test by connecting corresponding memory chips of each module. The test unit connects or disconnects the corresponding memory chips.

Description

Test apparatus for detecting the system fail and test method

BRIEF DESCRIPTION OF THE DRAWINGS In order to better understand the drawings cited in the detailed description of the invention, a brief description of each drawing is provided.

1 is a view showing a mounting test apparatus according to an embodiment of the present invention.

FIG. 2 is a diagram illustrating the operation of the FET logic of FIG. 1.

3 is a view showing a mounting test apparatus according to another embodiment of the present invention.

4 is a view for explaining the operation of the switch of FIG.

5 is a flow chart illustrating a test method according to an embodiment of the present invention.

* Description of the symbols for the main parts of the drawings **

101: computer system (CPU)

110: main board

120, 130: memory module

122, 132: memory chips

150 test means

152: FET logic

154: connecting device

BACKGROUND OF THE INVENTION 1. Field of the Invention [0001] The present invention relates to system module memory module testing, and more particularly, to a mounting test apparatus for detecting system errors.

The semiconductor chip may operate as a single unit, but as various applications and applications are diversified and capacity is highly integrated, many types of semiconductor chips are modularized and used. A typical one is a memory module that is formed by modularizing several memory chips into one.

In order to check whether the memory module operates normally, it is necessary to accurately test each memory chip in the memory module. Currently, a method of testing a memory module includes a method of using memory test equipment and a method of directly mounting and testing a system using a memory module.

In the method of using the memory test equipment, the test is performed in a separate experimental environment, not an environment in which the memory module is actually installed and used. Therefore, there is a disadvantage in that the accuracy of the test is lowered because the characteristics of various noises in the actual use environment cannot be tested.

For example, a system hold that causes the system to stop working while using a computer system, or a blue screen error that causes a blue desktop to display a message indicating the occurrence of a fatal error while using the computer system. have. Errors such as system hold and blue screen are cases in which the memory module that worked normally in the experiment environment generates an error in the real environment. Therefore, the use of the memory test equipment cannot detect the occurrence of the above-described error.

The method of directly testing a system using a memory module has a disadvantage in that test time increases and mass productivity decreases due to high integration and large capacity of the memory module. In addition, the equipment to be mounted and tested in the system is very expensive and not readily available. In addition, the conventional mounting test apparatus tests the memory module as a whole, and thus it is impossible to accurately detect the location of the memory chip that generates a system level error.

SUMMARY OF THE INVENTION The present invention provides a memory chip that simultaneously tests a plurality of memory modules in parallel and sequentially tests each memory chip in the memory module, thereby reducing system-level mounting test cost and time and generating errors. An object of the present invention is to provide a test apparatus for mounting a memory module capable of detecting accurate information.

The mounting test apparatus according to the embodiment of the present invention for achieving the above technical problem is provided with a main board and test means.

The main board has at least two memory modules.

The test means includes a connection means and a transmission device, and connects and tests respective memories in the memory module.

Here, the memory module includes a plurality of memory chips.

The connection device of the test means electrically connects the memory chip and the transmission device, and the transmission device controls the transmission of the signal transmitted from the memory chip in the first memory module to the memory chip in the corresponding second memory module.

The first memory module, which is one memory module in the main board, receives a signal from the system using a memory module in which an error does not occur, and the second memory module, which is another memory module, uses a memory module in which an error occurs, and the first memory module It will be connected in parallel at one end of.

The n data signals generated in the system are input to the n memory chips in the first memory module, respectively, and the command signals generated in the system are input to both the memory chips of the first memory module and the second memory module.

DETAILED DESCRIPTION In order to fully understand the present invention, the operational advantages of the present invention, and the objects achieved by the practice of the present invention, reference should be made to the accompanying drawings which illustrate preferred embodiments of the present invention and the contents described in the drawings.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. Like reference numerals in the drawings denote like elements.

1 is a view showing a mounting test apparatus according to an embodiment of the present invention.

개의 메모리 칩을 장착하고 있다. 여기서, 하나의 메모리 모듈을 제1 메모리 모듈(130), 다른 하나의 메모리 모듈을 제2 메모리 모듈(120)이라 한다. 설명의 편의상 두개의 메모리 모듈이 장착된 경우가 도시되어 있으나, 3개 이상의 메모리 모듈이 장착될 수 있음은 자명하다. 제3 메모리 모듈(미도시)은 제2 메모리 모듈(120)의 일단에 병렬로 연결된다. The main board 110 mounts two or more memory modules. The memory module 130 is a memory module used in an actual system and includes a plurality of memory chips 132, 134, 136, and 138. Memory modules are usually 2, 4, 8, 16, etc. 2

Memory chips are installed. Here, one memory module is referred to as a first memory module 130 and the other memory module is referred to as a second memory module 120. For convenience of description, a case in which two memory modules are mounted is illustrated, but it is apparent that three or more memory modules may be mounted. The third memory module (not shown) is connected in parallel to one end of the second memory module 120.

As such, by configuring a plurality of memory modules in parallel, two or more memory modules can be tested at the same time during the module test, thereby reducing test time.

The test unit 150 connects the memory chips 132, 134, 136, and 138 in the first memory module 130 and the memory chips 122, 124, 126, and 128 in the second memory module 120. Each of the memory chips in the first memory module 130 is connected to each of the memory chips of the second memory module 120 corresponding in parallel.

The test means 150 has a connection device 154 and a transmission device 152.

The connection device 154 electrically connects the memory modules 120 and 130 and the transmission device 152 to transmit an applied signal.

The transmission device according to an embodiment of the present invention is composed of FET logic 152. The FET logic 152 determines whether the memory chips 132 and 122 are connected according to the FET control signal. When the FET control signal is applied high, the FET logic 152 is enabled and the corresponding connection device 154 is turned on so that a signal applied from the system 101 is applied to the memory chips 132 and 122. Is sent to. In addition, when the FET control signal is applied low, the FET logic 152 is disabled and the corresponding connection device 154 is turned off so that a signal applied from the system 101 is stored in the memory chips ( 132, 122 are blocked.

개의 메모리 칩(130, 132, 134, 136, 138)을 내장한다면, 2

개의 동일한 실행 명령 데이터를 각각의 메모리 칩으로 전송한다. 또한, 커맨드 신호(CMD- Command signal)는 /RAS, /CAS, /CS, /WE 신호들의 조합으로 데이터의 읽기(read) 및 쓰기(write)를 명령한다. 커맨드 신호(CMD)는 다수개의 메모리 모듈내의 메모리 칩 모두로 전송된다. 커맨드 신호(CMD)는 항상 활성화되어 모든 메모리 칩에 입력되어 있으므로, 시스템(101)으로부터 데이터(Data signal)가 전송되면, 메모리 칩은 바로 데이터를 독출 할 수 있게 되는 것이다. The computer system 101 transmits data (Data signal) to the first memory module instructing execution or termination of the program. Here, one memory module 130 is 2

Two memory chips (130, 132, 134, 136, 138), 2

Two identical execution command data are transferred to each memory chip. In addition, the command signal CMD-Command signal commands to read and write data in a combination of / RAS, / CAS, / CS, and / WE signals. The command signal CMD is transmitted to all of the memory chips in the plurality of memory modules. Since the command signal CMD is always activated and input to all the memory chips, when the data signal is transmitted from the system 101, the memory chip can immediately read the data.

Here, it is preferable that the first memory module 130 uses a good module in which an error does not occur, and the second memory module 120 uses a bad module in which an error occurs. If the first memory module 130 is a good module and the second memory module 120 is a bad module, it is bad when an error occurs after the data signal is transmitted. This is because the exact location of the memory module of the bad module can be determined.

The data signal input to the first memory chip 134 in the first memory module 130 passes through the test means 156 and 158 to allow the second memory chip 124 in the second memory module 120 to pass through. Let's see if it was sent to. The transmitted data signal is called a data signal for commanding the end of the program. If the memory chip 124 receiving the data signal does not terminate the program and generates an error such as the system hold described above, the memory chip 124 in the second memory module 120 may receive an error. It is judged that this is defective.

The test proceeds with sequential activation of the first FET logic 152 through the n-th FET logic 164. Here, enabling one FET logic disables the rest of the FET logic. In addition, the first FET logic 152 is sequentially activated, but if there is no abnormality in the test result, the next FET logic is activated. When the system operates according to the data signal transmitted through the activated FET logic 152 and the turned-on transmission device 154, it is determined that there is no abnormality. When a data signal for terminating the currently executed program is transmitted through the first memory chip 130, it is determined that there is no abnormality if the test is terminated. On the contrary, if a data signal for terminating the currently executed program is transmitted but the termination of the program is not executed and an error such as a system hold or a blue screen occurs, the corresponding memory It is determined that the chip 122 is defective.

First, when the first FET logic 152 is enabled, the connection device 154 connected to each of the first memory chips 132 and 122 is turned on. The remaining FET logics are then disabled. The remaining connection devices 158, 162, 164 are turned off. Therefore, the data signal transmitted from the computer system 101 is transmitted to the first memory chip 122 of the second memory module via the first memory chip 132 of the first memory module.

Then, the second FET logic 156 is activated and the remaining FET logics are deactivated. Then, the connection device 158 connected to each of the second memory chips 134 and 124 is turned on. The third FET logic 160 is activated to turn on the connection device 162 connected to the third memory chips 136 and 126, respectively. It proceeds sequentially, and finally, the n-th FET logic 164 is activated to turn on the connector 166 connected to the n-th memory chips 138 and 128, respectively.

Here, when the command signal CMD-Command signal is transmitted to the first and second memory modules 130 and 120, the delay caused by the FET logic 152 should be considered. FET logic 152 has its own inherent delay time. The delay time of the FET logic depends on the type of MOS transistor used.

If the time point at which the data signal is transmitted to the first memory chip 132 in the first memory module 130 is t = 0 and the delay time of the FET logic 152 is Td, The time point at which the command signal CMD is transmitted to the memory chip 132 is such that t = 0. In addition, a time point at which a data signal is transmitted from the memory chip 132 in the first memory module to the first memory chip 122 in the second memory module becomes t = Td. Accordingly, the time point at which the command signal CMD is transmitted to the first memory chip 122 in the second memory module may be t = Td. Therefore, the signal delay unit 105 must be placed between the transmission paths from which the command signal is transmitted from the first memory module 130 to the second memory module 120 to consider the delay time by the FET logic 152 described above. something to do.

In this way, a system error occurs when a bad memory chip is tested. Therefore, it is possible to detect the exact position of the memory chip in which the error occurs.

FIG. 2 is a diagram illustrating the operation of the FET logic of FIG. 1.

Referring to FIG. 2, the operation of the FET logic determines whether the FET control signal is applied to the input terminal, and whether the enable output terminal or the disable output terminal is activated according to the input FET control signal. do. Here, when the output is made to the enable output terminal (Enable output), the memory chip in the first memory module and the memory chip in the second memory module of FIG. 1 are turned on by the connection device. On the contrary, when the disable output terminal is activated, the connection device connecting the memory chip in the first memory module and the memory chip in the second memory module is opened.

In general, a field effect transistor (FET) (not shown) determines whether to pass current through the FET in accordance with the FET control signal applied to the gate voltage terminal. In the N-type FET, when the gate signal is applied to logic high (1), the FET is turned on and current flows.

The FET logic herein utilizes the FET characteristics described above. In the case of using an N-type FET, FET logic, which is a logic high-side transfer device, through the input terminal is enabled. When the logic low signal is applied, the FET logic is turned off so that the transmitter cannot transmit the signal.

As described above, depending on whether the FET logic is N-type or P-type, the type (logical high (1) or logic low (0)) of the FET control signal that causes the connection device to conduct varies. Therefore, the input FET control signal should be determined according to the FET logic used.

3 is a view showing a mounting test apparatus according to another embodiment of the present invention.

1 is a test apparatus according to an exemplary embodiment of the present invention, and FIG. 3 is a test apparatus according to another exemplary embodiment of the present invention, except for the transmitters 152 and 352 and the signal delay unit 105. All of these have the same configuration. Therefore, in the test apparatus according to another exemplary embodiment of FIG. 3, the rest of the configuration except for the transmitter 352 and the signal delay unit 105 is the same as described above with reference to FIG. 1.

Referring to FIG. 3, the transmission device includes a switch 352. By turning on or off the switch, it can be controlled like the FET of FIG. When the first switch 352 is turned on, the corresponding transmission device 354 is turned on. Therefore, the data signal transmitted to the first memory chip 332 in the first memory module 330 is transmitted to the first memory chip 322 of the second memory module 320. At this time, the other switches except the turned-on switch 325 is turned off.

If there is nothing wrong with the test by turning on the first switch, the next switch is turned on and tested. The determination of whether there is an error is the same as in the case of using the FET logic. The data signal transmitted to the first memory chip 332 in the first memory module 330 is data for commanding the end of the program. The first memory module 330 is a good module and a second memory module ( 320 is a bad module. If the bad memory module 322 of the bad module is defective, the program is not terminated and an error such as a system hold or a blue screen occurs. When the first memory chip 322 of the bad module is normal, the program is terminated according to the input data signal.

If the first memory chips 332 and 322 are not defective, the second switch 356 is turned on to test the second memory chips 334 and 324. If it is not a fault, the n-th switch 364 is turned on to test the n-th memory chips 338 and 328.

Here, the switch 352 does not cause a delay of the signal. Therefore, the signal delay unit 105 provided in FIG. 1 is not provided. If the command CMD signal is first input to the first memory module 130 and then input to the second memory module, a delay of the signal occurs according to a moving distance from the first memory module to the second memory module. However, the delay of the signal is the same in the transmission device 152, and need not be considered. In addition, since the length of the transmission device 152 is very short, the delay time due to the movement of the signal hardly occurs. Therefore, when the command signal CMD is input from the first memory module 330 to the second memory module 320, the respective memory chips 322 and 324 in the second memory module 320 do not go through the signal delay unit. , 326, 328).

4 is a diagram illustrating the switch of FIG. 3.

Referring to FIG. 4, the switch may be turned on or off to connect or block a signal movement path connected to the first memory chip and the second memory chip. Here, the switch is operated manually. The user who wants to test shorts the switch that he wants to turn on, and the rest of the switches are open.

5 is a flow chart illustrating a test method according to an embodiment of the present invention.

The test device is mounted between the memory chips corresponding to each of the at least two memory modules, including the first memory module and the second memory module (500). Here, the first memory module is a memory module (Good Module) that does not cause an error, and the second memory module is a memory module (Bad Module) in which an error occurs. This is because when one memory module is a good module and a system error occurs, it may be determined that an error has occurred in a memory chip in the bad memory module. Here, the test apparatus includes a transmission device 152 and a connection device 154, as described above.

The data signal generated in the system (user computer system) is transmitted to each memory chip in the first memory module. In operation 505, the command CMD signal is transmitted to all of the two or more memory modules. Here, the data signal is a signal having information for instructing execution and termination of a specific program. The command signal CMD is a signal for commanding read or write of the transmitted signal when there is a transmitted signal. Therefore, if a data signal and a read command command signal CMD signal for terminating the current program are transmitted to the memory chip, the memory chip that is not a bad chip terminates the program.

Then, the nth transmitter is activated, and the remaining transmitters are deactivated. Here, the activation means to turn on the movement path of the signal so that the transmission device can transmit the data signal applied to the first memory chip to the second memory chip. In contrast, deactivation means that the movement path of the signal is turned off. It is preferable to test the memory chips sequentially by setting the initial value of n to 1.

It is determined whether an operation according to the transmitted data signal is executed (515). It is to determine whether a system error has occurred. The determination method is as described above in the description of FIG. 1.

When the operation according to the transmitted data signal is executed, 1 is added to the value of n and the process returns to step 510. This is because it is necessary to determine whether the remaining memory chips are defective.

When the operation according to the transmitted data signal is not performed, it is determined that the memory chip in the bad module, which has caused an error, is defective among the nth memory chips connected to both ends of the nth transmission device (525).

 As described above, optimal embodiments have been disclosed in the drawings and the specification. Although specific terms have been used herein, these terms are only used for the purpose of describing the present invention and are not intended to limit the scope of the present invention as defined in the claims or the claims. Therefore, those skilled in the art will understand that various modifications and equivalent other embodiments are possible from this. Therefore, the true technical protection scope of the present invention will be defined by the technical spirit of the appended claims.

As described above, the mounting test apparatus according to the present invention has the advantage of sequentially testing each memory in the memory module, deriving accurate information of the defective memory, and reducing the cost and time of the test.

Claims (11)

In a test apparatus for detecting errors in the system, A main board including at least two memory modules, including first and second memory modules having a plurality of memory chips; Test means for connecting and testing respective memory chips in the two or more memory modules, And the test means causes the corresponding memory chips to be connected or disconnected. The method of claim 1, wherein the test means, A connection device for electrically connecting the memory and the transmission device; And And a transmission device for controlling the transmission of a signal transmitted from a memory in the first memory module to a memory in a corresponding second memory module. The method of claim 2, wherein the main board, The first memory module, which is one memory module, receives a signal from a system using a memory module in which an error does not occur, and the second memory module, which is another memory module, uses a memory module in which an error occurs, and one end of the first memory module Mount test apparatus for detecting a system error, characterized in that connected in parallel. The apparatus of claim 3, wherein the mounting test apparatus comprises: N data signals generated in the system are respectively input to n memories in the first memory module, and command signals generated in the system are input to both memories of the first memory module and the second memory module. Mount test device for detecting errors. The method of claim 2, wherein the transmission device And a FET logic turned on or off by a FET control signal. The method of claim 2, wherein the transmission device A mounting test apparatus for detecting a system error, comprising a switch that is turned on or off according to an intention of a user. The method of claim 5, wherein the mounting test apparatus, The test apparatus for detecting a system error, wherein the command signal is input to the second memory module by being delayed by a delay time by the FET logic based on the time when the command signal is input to the first memory module. .  CLAIMS 1. A memory module including at least two memory modules, including first and second memory modules, comprising: mounting test devices between respective corresponding memory chips in the memory modules; Transmitting a data signal generated in a system to each memory chip in the first memory module, and transmitting a command signal in common to the memory chips; Activating the nth test device and deactivating the remaining test devices; And determining that any one of the n-th memory chips connected to both ends of the n-th test apparatus is defective if the operation according to the transmitted data signal is not performed. The memory module of claim 8, wherein the memory modules include: The first memory module is a memory module in which no system error occurs, and the second memory module is a memory module in which a system error occurs. The method of claim 9, wherein the failure determination step, And a memory chip in the first memory module in which the error occurs is determined to be defective. The method according to claim 9, wherein when an operation according to the transmitted data signal is executed, The method of claim 1, further comprising returning to the step of activating the n-th test device.

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