KR20080002501A - Flip chip type semiconductor package - Google Patents

Flip chip type semiconductor package Download PDF

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Publication number
KR20080002501A
KR20080002501A KR1020060061368A KR20060061368A KR20080002501A KR 20080002501 A KR20080002501 A KR 20080002501A KR 1020060061368 A KR1020060061368 A KR 1020060061368A KR 20060061368 A KR20060061368 A KR 20060061368A KR 20080002501 A KR20080002501 A KR 20080002501A
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KR
South Korea
Prior art keywords
underfill
substrate
semiconductor chip
solder
back grinding
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Application number
KR1020060061368A
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Korean (ko)
Inventor
김성철
박명근
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주식회사 하이닉스반도체
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Priority to KR1020060061368A priority Critical patent/KR20080002501A/en
Publication of KR20080002501A publication Critical patent/KR20080002501A/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/50—Tape automated bonding [TAB] connectors, i.e. film carriers; Manufacturing methods related thereto
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/07—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L29/00
    • H01L25/074—Stacked arrangements of non-apertured devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector

Abstract

A flip chip type semiconductor package is provided to eliminate the necessity of an underfill liquid injecting and hardening process and an additional preliminary process for performing an underfill process by using an adhesive layer of back grinding laminate tape as an underfill that protects a conduction member between a semiconductor chip and a printed circuit board. A plurality of input/output pads(12) are formed at one side of a semiconductor substrate(10). A plurality of connection pads(22) are immanent in a substrate. An adhesion/conduction member bonds the semiconductor chip to the substrate, supplying an electrical path between the input/output pad and the connection pad. An underfill is made of an adhesive layer(28) of a back grinding laminate tape, position between the semiconductor chip and the substrate. The conduction member can be a stack structure of UBM(under bump metallurgy)(14), a solder bump(16) and a solder(18).

Description

플립 칩 타입 반도체 패키지 {FLIP CHIP TYPE SEMICONDUCTOR PACKAGE}Flip Chip Type Semiconductor Package {FLIP CHIP TYPE SEMICONDUCTOR PACKAGE}

도 1은 종래 언더필 공정이 실시된 플립 칩 타입 반도체 패키지를 설명하기 위해 도시한 단면도.1 is a cross-sectional view illustrating a flip chip type semiconductor package subjected to a conventional underfill process.

도 2a내지 도2c는 본 발명의 실시예에 따른 플립 칩 타입 반도체 패키지의 제조 과정을 설명하기 위하여 도시한 단면도.2A to 2C are cross-sectional views illustrating a fabrication process of a flip chip type semiconductor package according to an embodiment of the present invention.

* 도면의 주요 부분에 대한 부호의 설명 *Explanation of symbols on the main parts of the drawings

10 : 반도체 칩 12 : 입출력 패드10 semiconductor chip 12 input / output pad

14 : UBM 16 : 솔더 범프14: UBM 16: Solder Bump

18 : 솔더 22 : 접속 패드18 solder 22 connection pad

24 : 인쇄회로 기판 26 : 백 그라인딩 라미네이트 테이프 24: printed circuit board 26: back grinding laminate tape

28 : 접착제 층28: adhesive layer

본 발명은 플립 칩 타입의 반도체 패키지에 관한 것으로, 보다 상세하게는, 언더필 공정이 필요없는 플립 칩 타입 반도체 패키지에 관한 것이다.The present invention relates to a flip chip type semiconductor package, and more particularly, to a flip chip type semiconductor package that does not require an underfill process.

플립 칩 타입 반도체 패키지는 반도체 칩을 패키지하지 않고 그대로 인쇄회 로 기판에 실장하는 기술로, 반도체 칩의 상부에 형성되어 있는 패드들 위에 솔더 범프(Solder Bump)와 같은 돌출부를 형성하고 범프와 인쇄회로 기판에 인쇄된 접속패드를 플립 칩 본딩 방식으로 접속시키는 것이다. 이와 같은 방법으로 인쇄회로 기판에 반도체 칩을 실장하면, 반도체 칩과 인쇄회로 기판의 열팽창계수 차이로 인하여 그들과 접합되어 있는 솔더 범프의 상,하부 면에 전단 응력이 부가되어 소성 변형(Plastic Strain)과 같은 솔더 접합의 변형이 일어나고, 솔더 접합이 심한 온도 변화를 겪게 되면 소성 변형은 점점 증가하고 솔더 자체의 파괴 임계점을 넘게 되어 솔더 접합에 크랙(Crack)이 가게 되어 반도체 패키지의 전기적 특성이 저하된다.The flip chip type semiconductor package is a technology in which a semiconductor chip is mounted on a printed circuit board without packaging a semiconductor chip. A flip chip type semiconductor package forms protrusions such as solder bumps on pads formed on an upper side of the semiconductor chip, and bumps and printed circuits. The connection pad printed on the substrate is connected by flip chip bonding. When the semiconductor chip is mounted on the printed circuit board in this manner, the shear stress is applied to the upper and lower surfaces of the solder bumps bonded thereto due to the difference in thermal expansion coefficient between the semiconductor chip and the printed circuit board, thereby causing plastic strain. When the solder joint is deformed and the solder joint undergoes a severe temperature change, the plastic strain gradually increases and crosses the fracture threshold of the solder itself, causing cracks in the solder joint, thereby deteriorating the electrical characteristics of the semiconductor package. .

또한, 반도체 칩의 솔더 범프의 높이로 인해 반도체 칩과 인쇄회로 기판 사이에 갭(Gap)이 형성되어 반도체 칩의 지지력이 약화된다. 따라서, 반도체 칩을 안정적으로 지지하고 솔더 범프의 상하 접합면에 크랙이 가는 것을 방지하기 위하여 언더필 공정을 실시한다.In addition, a gap (Gap) is formed between the semiconductor chip and the printed circuit board due to the height of the solder bump of the semiconductor chip weakens the bearing capacity of the semiconductor chip. Therefore, an underfill process is performed to stably support the semiconductor chip and to prevent cracks on the upper and lower joining surfaces of the solder bumps.

도 1은 종래 언더필 공정이 실시된 플립 칩 타입 반도체 패키지를 설명하기 위해 도시한 단면도이다.1 is a cross-sectional view illustrating a flip chip type semiconductor package in which a conventional underfill process is performed.

도 1에 도시된 바와 같이, 일측에 다수의 입출력 패드(12)가 형성된 반도체 칩(10), 접속 패드(22) 및 그 상부에 솔더(18)가 형성되어 있고 반도체 칩(10)의 전기적 신호를 외부에 전달하기 위한 매개체 역할을 하는 인쇄회로 기판(24), 반도체 칩(10)의 입출력 패드(12)에 콘택되어 있는 다수의 언더 범프 메탈러지(Under Bump Metallurgy : 이하 "UBM" 이라고 함)(14), UBM(14)에 접합되어 반도체 칩(10) 의 입출력 패드(12)와 인쇄회로 기판(24) 사이에서 전기 신호의 도선 역할을 하는 다수의 솔더 범프(16), 솔더 범프(16)와 인쇄회로 기판(24) 사이의 공간에 충진되어 반도체 칩(10)을 안정적으로 지지하고 솔더 접합부의 피로 수명을 향상시키고 솔더 범프(16)가 받는 응력의 일부를 흡수하는 언더필(20)로 구성된다.As shown in FIG. 1, a semiconductor chip 10 having a plurality of input / output pads 12 formed on one side, a connection pad 22, and solder 18 formed thereon, and an electrical signal of the semiconductor chip 10. A plurality of under bump metallurgy (hereinafter referred to as "UBM") contacted to the printed circuit board 24 and the input / output pad 12 of the semiconductor chip 10, which serves as a medium for delivering the material to the outside. 14, a plurality of solder bumps 16 and solder bumps 16 bonded to the UBM 14 to serve as conductors of electrical signals between the input / output pads 12 of the semiconductor chip 10 and the printed circuit board 24. Filled into the space between the printed circuit board 24 and the underfill 20 to stably support the semiconductor chip 10, to improve the fatigue life of the solder joint, and to absorb a part of the stress applied by the solder bump 16. It is composed.

그러나, 상기 언더필 공정이 필요한 플립 칩 타입 반도체 패키지에서는 언더필 공정에서 에폭시(Epoxy) 레진(Resin) 복합체로 이루어진 언더필 액을 경화시키킬 때 언더필 액에 내재되어 있는 공기가 제대로 배출되지 않을 경우, 배출되지 못한 공기로 인해 언더필(20)에 에폭시 보이드(Void)가 발생되고, 이런 에폭시 보이드를 막기 위하여 충분한 경화시간이 요구되는 언더필 경화(Cure) 공정이 추가되어 공정 시간을 길어지고 제품을 제작하는데 많은 시간이 소요된다.However, in the flip chip type semiconductor package which requires the underfill process, when the underfill liquid composed of epoxy resin composite is cured in the underfill process, the air contained in the underfill liquid is not discharged properly. Poor air creates epoxy voids in the underfill 20 and adds an underfill curing process that requires sufficient curing time to prevent these epoxy voids, resulting in longer process times and longer time to manufacture the product. This takes

그리고, 언더필(20)에 열이 가해지면 언더필(20) 내부에 존재해 있던 공기가 과도하게 팽창되어 언더필에 크랙(Crack)을 발생시킴으로써 제품의 신뢰성을 저하시키고, 생성된 에폭시 보이드로 인하여 전기 신호 경로의 쇼트(Short)가 발생하는 등의 공정 불량을 야기시킨다.In addition, when heat is applied to the underfill 20, the air present in the underfill 20 is excessively expanded to cause cracks in the underfill, thereby lowering the reliability of the product, and causing the electrical signal due to the generated epoxy voids. It causes process defects such as short circuit of the path.

또한, 언더필 물질에 사용되는 에폭시 레진 복합체는 고가이기 때문에 반도체 패키지의 제조 단가를 상승시키게 된다. In addition, the epoxy resin composite used in the underfill material is expensive, thereby increasing the manufacturing cost of the semiconductor package.

본 발명은 상기와 같은 종래의 문제점을 해결하기 위해 안출된 것으로서, 본 발명의 목적은 백 그라인딩 라미네이트 테이프 접착제 층을 이용하여 언더필을 형성함으로써 제품을 제작하는 시간을 단축함에 있다.SUMMARY OF THE INVENTION The present invention has been made to solve the above conventional problems, and an object of the present invention is to shorten the time to manufacture a product by forming an underfill using a back grinding laminate tape adhesive layer.

또한, 본 발명의 다른 목적은 솔더 범프의 위치별로 높이의 편차를 줄일 수 있어 공정 중에 발생할 수 있는 위치별 상이한 접합을 방지할 수 있고, 에폭시 계열의 언더필을 형성할 때 발생하는 에폭시 보이드를 원천적으로 방지하여 언더필의 크랙 및 전기적 신호의 쇼트를 없애 패키지의 신뢰성을 확보함에 있다. In addition, another object of the present invention is to reduce the variation in height for each position of the solder bumps to prevent different bonding by position that can occur during the process, and the epoxy voids generated when forming the epoxy-based underfill is essentially It prevents underfill cracks and shorts of electrical signals to ensure package reliability.

상기와 같은 목적을 달성하기 위하여, 본 발명에 따른 플립 칩 타입 반도체 패키지는, 일측에 다수의 입출력 패드가 형성된 반도체 칩, 반도체 칩과 기판 사이에서 전기 신호의 도선 역할을 하는 다수의 통전 부재, 통전 부재가 형성되어 있는 반도체 칩의 면에 통전 부재를 수용하면서 테이핑되고 기부 필름 층이 제거되어 접착제 층만 남아있는 백 그라인딩 라미네이트 테이프, 반도체 칩에 콘택된 솔더 범프와 일대일 대응으로 부착되는 접속패드가 내재된 인쇄회로 기판을 포함하여 이루어진다.In order to achieve the above object, the flip chip type semiconductor package according to the present invention, a semiconductor chip having a plurality of input and output pads on one side, a plurality of conducting members that serve as conductors of electrical signals between the semiconductor chip and the substrate, The back-grinding laminate tape is taped while receiving the conducting member on the surface of the semiconductor chip on which the member is formed, and the base film layer is removed so that only the adhesive layer remains. It includes a printed circuit board.

(실시예)(Example)

이하, 첨부된 도면을 참조하여 본 발명의 바람직한 실시예를 상세하게 설명 하도록 한다. 여기서, 도 1과 동일한 부분은 동일한 도면부호로 나타내도록 한다.Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. Here, the same parts as in FIG. 1 will be indicated by the same reference numerals.

도 2a내지 도2c는 본 발명의 실시예에 따른 플립 칩 타입 반도체 패키지의 제조 과정을 설명하기 위하여 도시한 단면도이다.2A to 2C are cross-sectional views illustrating a fabrication process of a flip chip type semiconductor package according to an embodiment of the present invention.

도 2a에 도시된 바와 같이, 본 발명에 따른 플립 칩 타입 반도체 패키지는, 일측에 다수의 입출력 패드가 형성된 반도체 칩(10)과, 반도체 칩(10)의 입출력 패드(12) 위에 전기 신호의 도선 역할을 하는 다수의 UBM(14)과 솔더 범프(16)가 형 성시키고, 솔더 범프(16)가 형성되어 있는 반도체 칩(10)의 면에 백 그라인딩 라미네이트 테이프(26)를 테이핑하고, 테이핑 된 반대면에서 백 그라인딩 공정을 진행한다.As shown in FIG. 2A, the flip chip type semiconductor package according to the present invention includes a semiconductor chip 10 having a plurality of input / output pads formed on one side thereof, and a conductive signal conductor on the input / output pad 12 of the semiconductor chip 10. A plurality of UBMs 14 and solder bumps 16, which play a role, are formed, and the back grinding laminate tape 26 is taped on the surface of the semiconductor chip 10 on which the solder bumps 16 are formed, and the taped The back grinding process is performed on the opposite side.

UBM(14)은 솔더 범프(16)가 반도체 칩(10)의 입출력 패드(12)에 직접적으로 연결되는 것이 힘들기 때문에 접합이 용이하고 솔더 범프(16)를 형성하는 솔더의 용융시 솔더가 반도체 칩으로 확산하는 것을 방지하도록 반도체 칩(10)의 입출력 패드(12)와 솔더 범프(16) 사이에 형성하는 다층 금속층으로 접합층(미도시), 확산방지층(미도시), 젖음층(미도시)으로 구성되어 반도체 칩(10)의 입출력 패드(12) 부분에 직접 부착되어 있다.Since the UBM 14 has difficulty in directly connecting the solder bumps 16 to the input / output pads 12 of the semiconductor chip 10, the solders are easy to join and the solders are semiconductor during melting of the solder forming the solder bumps 16. Multi-layered metal layers formed between the input / output pads 12 and the solder bumps 16 of the semiconductor chip 10 to prevent diffusion into the chip. The bonding layer (not shown), the diffusion barrier layer (not shown), and the wet layer (not shown). ) Is directly attached to the input / output pad 12 portion of the semiconductor chip 10.

그리고, 백 그라인딩 라미네이트 테이프(26)는 접착제 층(Adhesive layer)(28)과 기부 필름 층(Base film Layer)(30)으로 구성되어 있는데, 기부 필름 층(30)은 접착제 층(28)을 고정시켜 주는 역할을 하고 접착제 층(28)은 반도체 칩(10)에 콘택된 UBM(14) 및 솔더 범프(16)를 수용한 채 반도체 칩(10)에 테이핑 된다. The back grinding laminate tape 26 is composed of an adhesive layer 28 and a base film layer 30, which base film layer 30 fixes the adhesive layer 28. The adhesive layer 28 is taped to the semiconductor chip 10 while receiving the UBM 14 and the solder bumps 16 contacted to the semiconductor chip 10.

상기 도 2a에서의 제조 과정 이후, 도 2b에 도시된 바와 같이, 백 그라인딩 공정 후 백 그라인딩 라미네이트 테이프(26)의 기부 필름 층(30)만 제거하고 접착제 층(28)은 반도체 칩(10)에 접착된 채 남겨둔다. After the fabrication process in FIG. 2A, as shown in FIG. 2B, only the base film layer 30 of the back grinding laminate tape 26 is removed after the back grinding process and the adhesive layer 28 is applied to the semiconductor chip 10. Leave glued.

상기 접착제 층(28)은 UBM(14)과 솔더 범프(16) 등의 통전 부재를 수용한 채 반도체 칩(10)과 접착되어 통전 부재를 보호하는 언더필(28)로 사용됨으로 별도의 언더필 공정 없이 언더필(28)이 생성된다.The adhesive layer 28 is bonded to the semiconductor chip 10 while accommodating the conduction members such as the UBM 14 and the solder bumps 16 and used as the underfill 28 to protect the conduction member. Underfill 28 is generated.

그리고, 언더필로 사용되는 접착제 층(28)은 반도체 칩(10)에 형성되는 솔더 범프(16)에 따라서 그 높이를 결정할 수 있고 반도체 칩(10)의 본딩 형상에 따라 여러 가지 형상으로 제작된다.The adhesive layer 28 used as the underfill can determine its height according to the solder bumps 16 formed on the semiconductor chip 10 and is manufactured in various shapes according to the bonding shape of the semiconductor chip 10.

도 2a에서의 제조 과정 이후, 도 2c에 도시된 바와 같이, 인쇄회로 기판(24)에 형성되어 있는 다수의 접속 패드(22)에 솔더 범프(16)를 일대일 대응으로 콘택시키고 압력을 가하여 전기적인 패스를 형성시켜 플립 칩 타입 반도체 패키지를 완성한다. After the manufacturing process in FIG. 2A, as shown in FIG. 2C, the solder bumps 16 are contacted in a one-to-one correspondence to a plurality of connection pads 22 formed on the printed circuit board 24, and electrical pressure is applied. A pass is formed to complete a flip chip type semiconductor package.

인쇄회로 기판(24)에 배열된 접속 패드(22)의 상부에는 솔더(18)가 도포되어 솔더 범프(16)와 콘택되고, 전기적 연결을 위하여 가해지는 압력으로 필렛(Fillet)(미도시)이 형성된다.Solder 18 is applied on top of the connection pads 22 arranged on the printed circuit board 24 to contact the solder bumps 16, and fillet (not shown) is applied under pressure applied for electrical connection. Is formed.

본 발명에 따르면, 반도체 칩(10)에 접착되어 있는 백 그라인딩 라미네이트 테이프(26)의 접착제 층(28)이 언더필로 사용되어 언더필 액의 주입 및 경화 공정과 같은 부가적인 언더필 공정 없이 플립 칩 타입 반도체 패키지를 제조할 수 있다.According to the present invention, the adhesive layer 28 of the back grinding laminate tape 26 adhered to the semiconductor chip 10 is used as an underfill, so that a flip chip type semiconductor can be used without an additional underfill process such as the injection and curing process of the underfill liquid. The package can be manufactured.

이상에서와 같이, 본 발명은 플립 칩 타입 반도체 패키지에서 백 그라인딩 라미네이트 테이프의 접착제 층이 반도체 칩과 인쇄회로 기판 사이에서 통전 부재를 보호하는 언더필로 사용되어 언더필 액의 주입 및 경화 공정과 언더필 공정을 진행하기 위한 별도의 예비 공정이 필요 없어 제작 시간을 단축할 수 있다.As described above, in the flip chip type semiconductor package, the adhesive layer of the back grinding laminate tape is used as an underfill to protect the conduction member between the semiconductor chip and the printed circuit board, thereby injecting and curing the underfill liquid and the underfill process. There is no need for a separate preliminary process to proceed, reducing the production time.

그리고, 언더필 액의 주입 및 경화 공정과 같은 언더필 공정이 필요 없어 언 더필의 재료로 사용되는 에폭시 레진 복합체를 사용하지 않아 패키지의 제작 비용을 낮출 수 있다.In addition, there is no need for an underfill process such as an underfill liquid injection and curing process, and thus, a manufacturing cost of the package can be lowered by not using an epoxy resin composite used as an underfill material.

또한, 솔더 범프의 위치별로 높이의 편차를 줄일 수 있어 공정 중에 발생할 수 있는 위치별 상이한 접합을 방지할 수 있고, 에폭시 언더필에서 발생되는 에폭시 보이드 및 그로 인한 전기적 쇼트를 원천적으로 막아 패키지의 신뢰성을 확보할 수 있다.In addition, it is possible to reduce the height variation for each position of the solder bumps to prevent different bonding by position that can occur during the process, and to ensure the reliability of the package by preventing the epoxy voids generated from the epoxy underfill and the resulting electrical short can do.

Claims (5)

일측에 다수의 입출력 패드가 형성되어 있는 반도체 칩;A semiconductor chip having a plurality of input / output pads formed on one side thereof; 다수의 접속 패드가 내재된 기판;A substrate having a plurality of connection pads embedded therein; 상기 반도체 칩과 상기 기판을 접합시키면서 상기 입출력 패드와 상기 접속 패드 사이에 전기적 패스를 제공하는 접착 및 통전 부재; 를An adhesion and conduction member which bonds the semiconductor chip to the substrate and provides an electrical path between the input / output pad and the connection pad; To 포함하고, 상기 반도체 칩과 기판 사이에 위치하며 백 그라인딩 라미네이트 테이프의 접착제 층으로 이루어지는 언더필을 특징으로 하는 플립 칩 타입 반도체 패키지.And an underfill positioned between the semiconductor chip and the substrate, the underfill comprising an adhesive layer of a back grinding laminate tape. 제 1항에 있어서,The method of claim 1, 통전 부재가 UBM과 솔더 범프 및 솔더의 적층구조인 것을 특징으로 하는 플립 칩 타입 반도체 패키지.A flip chip type semiconductor package, wherein the conductive member is a laminate structure of UBM, solder bumps, and solder. 제 1항에 있어서,The method of claim 1, 통전 부재가 스투드 범프와 솔더의 적층구조인 것을 특징으로 하는 플립 칩 타입 반도체 패키지.A flip chip type semiconductor package, wherein the energizing member is a laminated structure of a stud bump and a solder. 제 1항에 있어서,The method of claim 1, 통전 부재가 패터닝된 금속 범프와 솔더의 적층구조인 것을 특징으로 하는 플립 칩 타입 반도체 패키지.A flip chip type semiconductor package, wherein the conductive member is a laminated structure of a patterned metal bump and a solder. 반도체 칩의 입출력 패드에 콘택된 접착 및 통전 부재가 위치한 면에 접착 및 통전 부재를 수용하는 기부 필름 층과 접착제 층으로 구성되어 있는 백 그라인딩 라미네이트 테이프를 테이핑하고 백 그라인딩 공정을 진행하는 단계;Taping a back grinding laminate tape including a base film layer and an adhesive layer on the surface where the adhesive and conducting members contacted to the input / output pads of the semiconductor chip are located, and performing a back grinding process; 상기 백 그라인딩 라미네이트 테이프의 기부 필름 층을 제거하고 접착제 층을 외부로 노출시키는 단계 단계;Removing the base film layer of the back grinding laminate tape and exposing the adhesive layer to the outside; 기판에 내재된 다수의 접속 패드에 솔더를 배열시키는 단계;Arranging solder on a plurality of connection pads embedded in the substrate; 상기 기부 필름 층을 제거한 상기 백 그라인딩 라미네이트 테이프의 접착제 층 면에 상기 기판을 접착시켜서 상기 백 그라인딩 라미네이트 테이프의 접착제 층에 수용되어 있는 통전 부재와 상기 기판의 접속 패드를 일대일 대응시키는 단계;를Adhering the substrate to the adhesive layer side of the back grinding laminate tape from which the base film layer has been removed, thereby one-to-one correspondence of the conductive member accommodated in the adhesive layer of the back grinding laminate tape and the connection pad of the substrate; 포함하는 것을 특징으로 하는 플립 칩 타입 반도체 패키지의 제조 방법.Method for manufacturing a flip chip type semiconductor package, characterized in that it comprises a.
KR1020060061368A 2006-06-30 2006-06-30 Flip chip type semiconductor package KR20080002501A (en)

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Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100884192B1 (en) * 2007-07-20 2009-02-18 앰코 테크놀로지 코리아 주식회사 Manufacturing method of semiconductor package
US7807507B2 (en) 2008-08-20 2010-10-05 Samsung Electronics Co., Ltd. Backgrinding-underfill film, method of forming the same, semiconductor package using the backgrinding-underfill film, and method of forming the semiconductor package
US10276538B2 (en) 2016-08-01 2019-04-30 Samsung Display Co., Ltd. Electronic device having an under-fill element, a mounting method of the same, and a method of manufacturing a display apparatus having the electronic device
CN116741648A (en) * 2023-08-11 2023-09-12 四川遂宁市利普芯微电子有限公司 Flip chip packaging method and flip chip packaging structure

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100884192B1 (en) * 2007-07-20 2009-02-18 앰코 테크놀로지 코리아 주식회사 Manufacturing method of semiconductor package
US7807507B2 (en) 2008-08-20 2010-10-05 Samsung Electronics Co., Ltd. Backgrinding-underfill film, method of forming the same, semiconductor package using the backgrinding-underfill film, and method of forming the semiconductor package
US10276538B2 (en) 2016-08-01 2019-04-30 Samsung Display Co., Ltd. Electronic device having an under-fill element, a mounting method of the same, and a method of manufacturing a display apparatus having the electronic device
CN116741648A (en) * 2023-08-11 2023-09-12 四川遂宁市利普芯微电子有限公司 Flip chip packaging method and flip chip packaging structure
CN116741648B (en) * 2023-08-11 2023-11-17 四川遂宁市利普芯微电子有限公司 Flip chip packaging method and flip chip packaging structure

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