KR20080002055A - Method for fabricating semiconductor device - Google Patents

Method for fabricating semiconductor device Download PDF

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Publication number
KR20080002055A
KR20080002055A KR1020060060614A KR20060060614A KR20080002055A KR 20080002055 A KR20080002055 A KR 20080002055A KR 1020060060614 A KR1020060060614 A KR 1020060060614A KR 20060060614 A KR20060060614 A KR 20060060614A KR 20080002055 A KR20080002055 A KR 20080002055A
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South Korea
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silicon substrate
well
ion implantation
dopants
semiconductor device
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KR1020060060614A
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Korean (ko)
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함철영
장민식
손현수
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주식회사 하이닉스반도체
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Priority to KR1020060060614A priority Critical patent/KR20080002055A/en
Publication of KR20080002055A publication Critical patent/KR20080002055A/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
    • H01L21/0257—Doping during depositing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02367—Substrates
    • H01L21/0237—Materials
    • H01L21/02373—Group 14 semiconducting materials
    • H01L21/02381—Silicon, silicon germanium, germanium
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31105—Etching inorganic layers
    • H01L21/31111—Etching inorganic layers by chemical means
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823493—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the wells or tubs, e.g. twin tubs, high energy well implants, buried implanted layers for lateral isolation [BILLI]

Abstract

A method for fabricating a semiconductor device is provided to improve a threshold voltage shift characteristic and a cell disturbance characteristic by removing residual dopants on the surface of a silicon substrate. Dopants for forming wells(21,22) are implanted into a silicon substrate(20) to form the well. The surface of the silicon substrate having the well is oxidized to form an oxide layer. The oxide layer is removed by a blanket etch process to remove the dopants and damage on the surface of the silicon substrate and has a thickness of 50 to 200 angstroms.

Description

반도체 소자의 제조방법{Method for fabricating semiconductor device}Method for fabricating semiconductor device {Method for fabricating semiconductor device}

도 1은 웰 이온 주입 후 실리콘 기판 깊이 방향에 따른 도펀트 농도를 나타낸 그래프1 is a graph showing the dopant concentration according to the silicon substrate depth direction after well ion implantation

도 2a 내지 도 2d는 본 발명의 실시예에 따른 반도체 소자의 제조공정 단면도2A through 2D are cross-sectional views illustrating a manufacturing process of a semiconductor device in accordance with an embodiment of the present invention.

<도면의 주요 부분에 대한 부호의 설명><Explanation of symbols for the main parts of the drawings>

20 : 실리콘 기판 21 : 트리플 n웰20 silicon substrate 21 triple n well

22 : p웰 23 : 잔류 도펀트22: p well 23: residual dopant

24 : 산화막 24: oxide film

본 발명은 반도체 소자의 제조방법에 관한 것으로, 특히 웰 이온 주입시 발생된 실리콘 기판 표면의 잔류 도펀트 및 데미지를 제거하기 위한 반도체 소자의 제조방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a method for manufacturing a semiconductor device for removing residual dopants and damage on the surface of a silicon substrate generated during well ion implantation.

최근, 고집적화되는 플래시 소자를 구현함에 있어서 소자 구조 형성 및 특성 확보에 용이한 SA-STI(Shallow Trench Isolation) 스킴을 적용하여 소자분리막을 형성함으로써 터널 산화막의 손상을 방지하여 열악한 소자 특성을 개선하고 있다.Recently, in implementing a highly integrated flash device, a device isolation film is formed by applying a SA-STI (Shallow Trench Isolation) scheme which is easy to form and secure device characteristics, thereby preventing damage to the tunnel oxide film, thereby improving poor device characteristics. .

플래시 소자의 디바이스 사이즈가 감소됨에 따라서 정션 깊이(junction depth)도 감소하였으며, 얕은 정션(shallow junction)을 형성함에 있어서 현재보다 더 정교한 이온 주입이 필요하게 되었다. 특히, 웰(well) 형성시, 일정 범위의 높은 에너지로 이온주입을 실시할 경우 실리콘 기판 표면에 도펀트의 표면 피크가 존재하게 된다.As the device size of the flash device is reduced, the junction depth has also decreased, and more sophisticated ion implantation is needed to form shallow junctions. In particular, when the wells are formed, the surface peaks of the dopants are present on the surface of the silicon substrate when ion implantation is performed at a high range of energy.

도 1은 웰 이온 주입 후 실리콘 기판 깊이 방향에 따른 도펀트 농도를 나타낸 그래프이다.1 is a graph showing dopant concentrations in a silicon substrate depth direction after well ion implantation.

도 1을 참조하면, 소자의 웰(well) 형성시 높은 에너지(high energy)로 웰 이온을 주입하면 목표 이온 주입 깊이(Projection Range, Rp)에서의 실제 피크(real peak)(A) 이외에 실리콘 기판 표면에서 침투되지 않고 남아있는 도펀트들이 존재하여 실리콘 기판 표면에 도펀트 표면 피크(surface peak)(B)가 발생되게 된다.Referring to FIG. 1, when well ions are implanted with high energy when forming wells of a device, a silicon substrate may be added in addition to a real peak A at a target ion implantation depth Rp. Dopants that remain uninfiltrated at the surface are present, resulting in a dopant surface peak B on the silicon substrate surface.

이러한 실리콘 기판 표면의 도펀트는 문턱전압 쉬프트(threshold voltage shift)를 일으켜 셀 분포(cell disturbance)에 영향을 줄 수 있다. The dopant on the surface of the silicon substrate may cause a threshold voltage shift and affect cell disturbance.

또한, 실리콘 기판 표면에 도펀트가 존재하면 이후 실시하는 필드 스탑 이온 주입 공정 및 문턱전압 조절 이온 주입 공정시 도펀트의 도즈량을 늘려야 하므로 도즈량 증가에 따른 표면 스트레스(surface stress) 증가로 누설이 커지게 된다.In addition, when dopants are present on the surface of the silicon substrate, the dose amount of the dopant must be increased during the field stop ion implantation process and the threshold voltage control ion implantation process to be performed. do.

따라서, 본 발명은 전술한 종래 기술의 문제점을 해결하기 위하여 안출한 것으로써, 웰 이온 주입시 발생된 실리콘 기판 표면의 잔류 도펀트 및 데미지를 제거하기 위한 반도체 소자의 제조방법을 제공하는데 그 목적이 있다.Accordingly, an object of the present invention is to provide a method of manufacturing a semiconductor device for removing residual dopants and damage on the surface of a silicon substrate generated during well ion implantation. .

본 발명에 따른 반도체 소자의 제조방법은 실리콘 기판에 웰 이온을 주입하여 웰을 형성하는 단계와, 상기 웰이 형성된 실리콘 기판의 표면을 산화시키어 산화막을 형성하는 단계와, 상기 산화막을 제거하여 상기 실리콘 기판 표면의 도펀트 및 데미지가 제거되는 단계를 포함한다.A method of manufacturing a semiconductor device according to the present invention includes the steps of forming wells by implanting well ions into a silicon substrate, oxidizing a surface of the silicon substrate on which the wells are formed, and forming an oxide film, and removing the oxide film to remove the silicon. Dopant and damage to the substrate surface is removed.

이하, 첨부된 도면을 참조하여 본 발명의 바람직한 실시예를 설명하기로 한다. 그러나, 본 발명은 이하에서 개시되는 실시예에 한정되는 것이 아니라 서로 다른 다양한 형태로 구현될 수 있으며, 본 발명의 범위가 다음에 상술하는 실시예에 한정되는 것은 아니다. 단지 본 실시예는 본 발명의 개시가 완전하도록 하며 통상의 지식을 가진 자에게 발명의 범주를 완전하게 알려주기 위해 제공되는 것이며, 본 발명의 범위는 본원의 특허청구범위에 의해서 이해되어야 한다. Hereinafter, with reference to the accompanying drawings will be described a preferred embodiment of the present invention. However, the present invention is not limited to the embodiments disclosed below, but may be implemented in various forms, and the scope of the present invention is not limited to the embodiments described below. Only this embodiment is provided to complete the disclosure of the present invention and to fully inform those skilled in the art, the scope of the present invention should be understood by the claims of the present application.

도 2a 내지 도 2d는 본 발명의 실시예에 따른 반도체 소자의 제조공정 단면도이다.2A through 2D are cross-sectional views illustrating a process of manufacturing a semiconductor device in accordance with an embodiment of the present invention.

도 2a를 참조하면, 실리콘 기판(20)에 웰(21)(22)을 형성한다.Referring to FIG. 2A, wells 21 and 22 are formed in the silicon substrate 20.

예를 들어, 다른 트랜지스터와 분리된 웰을 구현하기 위하여 p 타입의 실리콘 기판(20)에 n 타입 도펀트를 주입하여 트리플 n웰(21)을 형성하고, n 타입 트랜지스터 형성을 위하여 트리플 n 웰(21)에 p 타입 도펀트를 주입하여 p웰(22)을 형성한다.For example, to form a well separated from other transistors, n-type dopants are implanted into a p-type silicon substrate 20 to form triple n wells 21, and triple n wells 21 to form n-type transistors. P type dopant is injected into the p well 22 to form p well 22.

트리플 n웰(21)을 형성하기 위한 n 타입 도펀트로는 인(P)을 사용함이 바람직하고, n 타입 도펀트의 도즈량은 1E11 내지 1E14ions/㎠, 이온 주입 에너지는 1000 내지 15000KeV가 되게 함이 바람직하며, 3.2°의 트위스트각(twist angle)과 1.6°의 틸트각(tilt angle)을 주어 좌, 우로 틀어서 이온 주입이 되도록 하는 것이 좋다.Phosphorus (P) is preferably used as the n-type dopant for forming the triple n well 21, and the dose of the n-type dopant is preferably 1E11 to 1E14ions / cm2 and the ion implantation energy is 1000 to 15000 KeV. In addition, the twist angle of 3.2 ° and the tilt angle of 1.6 ° may be given so that the ion implantation is turned left and right.

p웰(22)을 형성하기 위한 p 타입 도펀트로는 보론(B)을 사용함이 바람직하고, p 타입 도펀트의 도즈량은 1E11 내지 1E14ions/㎠, 이온 주입 에너지는 300 내지 500KeV가 되게 함이 바람직하며, 3.2°의 트위스트각(twist angle)과 1.6°의 틸트각(tilt angle)을 주어 좌, 우로 틀어서 이온 주입이 되도록 하는 것이 좋다.It is preferable to use boron (B) as the p-type dopant for forming the p well 22, the dose of the p-type dopant is preferably 1E11 to 1E14ions / cm 2, and the ion implantation energy is 300 to 500 KeV. , 3.2 ° twist angle (tilt) and 1.6 ° tilt angle (tilt angle) to give a right to turn the ion implantation is good.

트리플 n웰(21) 및 p웰(22) 형성시 도펀트들이 실리콘 기판(20) 내부로 침투되지 못하여 실리콘 기판(20) 표면에 잔류 도펀트(23)가 다량 발생되어 실리콘 기판(20) 표면에 도펀트 표면 피크가 형성된다.When the triple n well 21 and the p well 22 are formed, dopants do not penetrate into the silicon substrate 20, so that a large amount of residual dopants 23 are generated on the surface of the silicon substrate 20, and thus dopants are formed on the surface of the silicon substrate 20. Surface peaks are formed.

이러한 잔류 도펀트(23)가 이후에도 계속 남아 있으면 후속 필드 스탑 이온 주입 공정 및 문턱전압 조절을 위한 이온 주입 공정시 이온 도즈량을 증가시켜야 한다. 그러나, 이온 도즈량이 높아지면 이온 주입시 실리콘 기판(20) 표면에 발생되는 스트레스가 증가되어 누설이 커지는 원인이 된다. 또한, 잔류 도펀트(23)는 후속 트랜지스터 형성시 문턱전압 쉬프트(Vt shift)를 일으켜 셀 디스터번스(cell disturbance)를 증가시킨다.If the residual dopant 23 remains thereafter, the amount of ion dose must be increased during the subsequent field stop ion implantation process and the ion implantation process for adjusting the threshold voltage. However, when the amount of ion dose is increased, the stress generated on the surface of the silicon substrate 20 during ion implantation is increased, causing leakage. In addition, the residual dopant 23 causes a Vt shift in subsequent transistor formation to increase cell disturbance.

도 2b를 참조하면, 실리콘 기판(20) 표면의 잔류 도펀트(23) 및 데미지를 제거하기 위하여 산화 공정으로 실리콘 기판(20)의 표면을 산화시키어 산화막(24)을 형성한다. 산화막(24)의 두께는 50 내지 200Å이 되도록 함이 바람직하다.Referring to FIG. 2B, an oxide film 24 is formed by oxidizing the surface of the silicon substrate 20 by an oxidation process in order to remove residual dopants 23 and damage on the surface of the silicon substrate 20. It is preferable to make the thickness of the oxide film 24 50-200 kPa.

도 2c를 참조하면, 산화막(24)을 제거하여 실리콘 기판(20) 표면의 잔류 도펀트(23)와 데미지를 제거한다. 산화막(24)은 전면 식각 방식으로 제거하며 건식식각법이나 습식식각법 중 어느 하나를 사용한다. 건식식각법을 사용할 경우 플루오르(F) 계열의 가스를 사용하고, 습식식각법을 사용할 경우에는 HF 계열이나 BOE(Buffer Oxide Etchant) 계열의 캐미컬을 사용함이 바람직하다.Referring to FIG. 2C, the oxide layer 24 is removed to remove residual dopants 23 and damage from the surface of the silicon substrate 20. The oxide film 24 is removed by a front etching method and may use either a dry etching method or a wet etching method. When using dry etching, it is preferable to use fluorine (F) -based gas, and when using wet etching, HF-based or BOE (Buffer Oxide Etchant) -based chemicals are preferably used.

도 2d를 참조하면, 필드 스탑 이온 주입 공정 및 문턱전압 조절 이온 주입 공정을 실시한다.Referring to FIG. 2D, a field stop ion implantation process and a threshold voltage control ion implantation process are performed.

필드 스탑 이온 주입 공정시 보론(B) 이온을 사용하고, 도즈량은 1E11~1E14ions/㎠, 이온주입 에너지는 50 내지 150KeV가 되게 하며, 3 내지 30°의 틸트각과 112°의 트위스트각을 주어 좌, 우로 틀어서 이온을 주입하는 것이 바람직하다.In the field stop ion implantation process, boron (B) ions are used, the dose amount is 1E11 to 1E14ions / ㎠, the ion implantation energy is 50 to 150 KeV, and the tilt angle of 3 to 30 ° and the twist angle of 112 ° are given. It is preferable to inject ions by twisting them.

문턱전압 조절 이온 주입 공정시 보론(B) 이온을 사용하고, 도즈량은 1E11~1E14ions/㎠, 이온주입 에너지는 10 내지 50KeV가 되게 하며, 3 내지 30°의 틸트각과 112°의 트위스트각을 주어 좌, 우로 틀어서 이온을 주입하는 것이 바람직하다.In the threshold voltage control ion implantation process, boron (B) ions are used, the dose amount is 1E11 ~ 1E14ions / ㎠, the ion implantation energy is 10 to 50KV, and the tilt angle of 3 to 30 ° and the twist angle of 112 ° are given. It is preferable to turn the left and right to inject ions.

본 발명에 의하면, 웰 이온을 주입한 후 실리콘 기판(20) 표면에 산화막(24)을 형성하고 제거하는 일련의 공정을 통하여 웰 이온 주입시 실리콘 기판(20) 표면에 발생된 잔류 도펀트(23) 및 데미지를 제거할 수 있다.According to the present invention, the residual dopant 23 generated on the surface of the silicon substrate 20 during the well ion implantation through a series of processes of forming and removing the oxide film 24 on the surface of the silicon substrate 20 after implanting the well ions. And damage can be removed.

따라서, 잔류 도펀트(23)로 인한 문턱전압 쉬프트 및 셀 디스터브 발생을 줄일 수 있고, 이후 필드 스탑 이온 주입 공정 및 문턱전압 조절 이온 주입 공정시 도즈량을 상향하지 않아도 되므로 필드 스탑 이온 주입 공정 및 문턱전압 조절 이온 주입 공정시 표면 스트레스 발생을 줄일 수 있다.Therefore, the threshold voltage shift and the cell disturbance caused by the residual dopant 23 can be reduced, and the field stop ion implantation process and the threshold voltage do not need to be increased during the field stop ion implantation process and the threshold voltage control ion implantation process. Surface stress can be reduced during the controlled ion implantation process.

또한, 실리콘 기판(20) 표면의 데미지를 제거할 수 있으므로 후속 열처리에 안정적인 소자 제조가 가능하다.In addition, since the damage on the surface of the silicon substrate 20 can be removed, it is possible to manufacture a stable device for subsequent heat treatment.

상술한 바와 같이, 본 발명은 다음과 같은 효과가 있다.As described above, the present invention has the following effects.

첫째, 실리콘 기판 표면의 잔류 도펀트를 제거할 수 있으므로 문턱전압 쉬프트 특성 및 셀 디스터브 특성을 개선할 수 있다. First, since the residual dopant on the surface of the silicon substrate can be removed, the threshold voltage shift characteristics and the cell disturb characteristics can be improved.

둘째, 실리콘 기판 표면의 잔류 도펀트를 제거하여 후속 필드 스탑 이온 주입 공정 및 셀 문턱전압 이온 주입 공정시 도즈량을 올리지 않아도 되므로 표면 스트레스 및 누설 전류를 줄일 수 있다.Second, surface dosing and leakage currents can be reduced by removing residual dopants on the surface of the silicon substrate, thereby eliminating the dose amount during the subsequent field stop ion implantation process and the cell threshold voltage ion implantation process.

셋째, 실리콘 기판 표면의 데미지를 제거할 수 있으므로 후속 열처리에 안정적인 소자를 제조할 수 있다.Third, since the damage on the surface of the silicon substrate can be removed, a device stable to subsequent heat treatment can be manufactured.

Claims (5)

실리콘 기판에 웰을 형성하기 위한 도펀트를 주입하여 웰을 형성하는 단계;Implanting a dopant for forming a well into the silicon substrate to form a well; 상기 웰이 형성된 실리콘 기판의 표면을 산화시키어 산화막을 형성하는 단계; 및Oxidizing a surface of the silicon substrate on which the well is formed to form an oxide film; And 상기 산화막을 제거하여 상기 실리콘 기판 표면의 도펀트 및 데미지가 제거되는 단계를 포함하는 반도체 소자의 제조방법.Removing the oxide layer to remove dopants and damages from the surface of the silicon substrate. 제 1항에 있어서, 상기 산화막을 50 내지 200Å의 두께로 형성하는 반도체 소자의 제조방법.The method for manufacturing a semiconductor device according to claim 1, wherein the oxide film is formed to a thickness of 50 to 200 GPa. 제 1항에 있어서, 상기 산화막을 전면 식각방식으로 제거하는 반도체 소자의 제조방법.The method of claim 1, wherein the oxide layer is removed by an entire surface etching method. 제 1항에 있어서, 상기 산화막을 플루오르(F) 계열의 가스를 이용한 건식식각법으로 제거하는 반도체 소자의 제조방법.The method of claim 1, wherein the oxide film is removed by a dry etching method using a fluorine (F) -based gas. 제 1항에 있어서, 상기 산화막을 HF 계열 또는 BOE 계열의 캐미컬을 이용한 습식식각법으로 제거하는 반도체 소자의 제조방법.The method of claim 1, wherein the oxide film is removed by a wet etching method using an HF-based or BOE-based chemical.
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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100985880B1 (en) * 2008-05-21 2010-10-08 주식회사 하이닉스반도체 Method for monitering plasma doping apparatus

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100985880B1 (en) * 2008-05-21 2010-10-08 주식회사 하이닉스반도체 Method for monitering plasma doping apparatus

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