KR20080001978A - Circuit and method for controlling isolation of cell mat in semiconductor memory apparatus - Google Patents

Abstract

A circuit and a method for controlling isolation of a cell mat in a semiconductor memory apparatus are provided to prevent an operation error by performing isolation control operation by reducing current consumption and then considering redundancy operation, by generating an isolation signal with a constant level. An end control unit(110) generates an end signal after a last word line of a cell mat is enabled during a refresh mode. A latch control unit(120) generates a latch control signal in correspondence to the end signal and a redundancy signal. An isolation signal generation unit(130) generates an isolation signal in correspondence to the latch control signal and a mat selection signal.

Description

Circuit and Method for Controlling Isolation of Cell Mat in Semiconductor Memory Apparatus

1 is a layout view of a cell mat insulation control circuit of a semiconductor memory device according to the related art;

2 is a block diagram showing a configuration of a cell mat insulation control circuit of a semiconductor memory device according to the present invention;

3 is a detailed block diagram of the termination control means shown in FIG. 2;

4 is a detailed configuration diagram of the latch control means shown in FIG. 2;

FIG. 5 is a detailed configuration diagram of the insulation signal generation means shown in FIG. 2.

<Description of the symbols for the main parts of the drawings>

1: cell mat 2: sense amplifier

5, 10: cell mat insulation control circuit 110: termination control means

120: latch control means 130: insulation signal generating means

The present invention relates to a cell mat insulation control circuit and method of a semiconductor memory device, and more particularly to a cell mat insulation control circuit and method of a semiconductor memory device to reduce the current consumption.

In general, a dynamic random access memory (DRAM) includes a plurality of memory cells including one transistor and one capacitor, and a unit of a predetermined number of memory cells is called a cell mat. A plurality of word lines for activating the memory cells are connected to the cell mat, and a plurality of sense amplifiers for performing input / output operations of data to the memory cells are connected through the bit lines. In the prior art, the cell mat is configured to share a bit line with one sense amplifier and a sub bit line with another sense amplifier to reduce the area. Accordingly, when one cell mat is activated, two sense amplifiers are operated, and a sense amplifier isolation control circuit that selectively isolates between the sense amplifier and the cell mat is used to prevent the neighboring cell mat from being affected. do.

Hereinafter, a sense amplifier isolation control circuit according to the related art will be described with reference to FIG. 1.

FIG. 1 is a layout view of a cell mat isolation control circuit of a semiconductor memory device according to the related art, in which the number of bit lines connected to the cell mat is four and the word lines are omitted. In addition, since the transistor provided between the bit line and the insulating line is omitted, when the insulating line has a high level potential, the bit line is insulated to simplify the drawing.

As shown, an insulation line ISL is provided between the cell mat 1 and the sense amplifier 2, and each insulation line ISL is controlled by the cell mat insulation control circuit 5. At this time, if the enabled mat select signal (cms) is input to two cell mat insulation control circuits 5 at the same time, the isolation signal (iso) is enabled from each cell mat insulation control circuit 5 to enable one cell mat. The bit line pairs BL and / BL outside the two sense amplifiers 2 are insulated around (1). In this case, in the cell mat insulation control circuit 5 other than the two cell mat insulation control circuits 5 inputted with the mat selection signal cms enabled, the insulation signal iso is disabled, and thus the insulation line is disabled. ISL does not insulate the corresponding bit line BL or the sub bit line / BL.

In the precharge operation of the semiconductor memory device, all the insulation lines do not perform the insulation operation. In the active operation, on the other hand, the cell mat selected by the address is activated, so that the cell mat isolation control circuitry prevents the adjacent cell mat from affecting the sense amplifier by insulating the corresponding isolation lines from the pair of bit lines. In this case, the word line selected by the address is activated, and data input / output is performed accordingly. The mat selection signal cms is enabled when the word line in the mat is activated. Accordingly, the insulation signal iso is enabled to perform the insulation operation.

In the refresh operation of the semiconductor memory device, unlike the active operation, one cell mat is selected and a plurality of word lines are sequentially activated. Subsequently, when the refresh operation for one cell mat is finished, the refresh operation for the next cell mat is performed to sequentially activate the plurality of word lines. In this case, since the mat selection signal cms is enabled every time the word line is activated, the mat selection signal cms is enabled as many times as the number of word lines included in one cell mat. Accordingly, the isolation signal iso is also used. It is enabled as many times as there are word lines. That is, if the cell mat has 512 word lines, the isolation signal iso must be enabled 512 times. When the isolation signal is a high enable signal, when a refresh operation is performed on one cell mat, only two cell mats 1 and two sense amplifiers 2 are shared and two adjacent cell mats are insulated. The potential of the repetitive pulse waveform having the rising edge and the falling edge 512 times is applied to the insulation line ISL. Accordingly, current consumption by peak current of 1024 times occurs.

When the refresh operation for one cell mat is terminated during the refresh operation, the refresh operation for the next cell mat is performed, and thus the current consumption caused by the peak current is repeatedly generated. Since a plurality of cell mats are provided in one memory bank, the current consumption described above becomes a deterioration factor of the semiconductor memory device that cannot be ignored considering the entire semiconductor memory device. In view of the current situation in which current consumption of a semiconductor memory device is the most important technical problem, the above-described current consumption becomes an essential factor to be solved. However, in the prior art, there is no means and a method for reducing the current consumption by the peak current repeatedly generated in the insulating line during the refresh operation.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned problems, and generates an isolation signal as a signal having a constant level to selectively insulate between the cell mat and the sense amplifier during a refresh operation, thereby reducing current consumption, and thus redundancy operation. In view of the above, there is a technical problem to provide a cell mat insulation control circuit and a method of a semiconductor memory device which prevent a malfunction by performing an insulation control operation.

According to another aspect of the present invention, there is provided a cell mat insulation control circuit of an exemplary embodiment of the present invention, comprising: end control means for generating a termination signal after a last word line of a cell mat is activated in a refresh mode; Latch control means for generating a latch control signal in response to the end signal and the redundancy signal; And an isolation signal generating means for generating an isolation signal in response to the latch control signal and the mat selection signal.

In addition, the cell mat isolation control circuit of the semiconductor memory device of the present invention, termination control means for generating a termination signal when the last word line of the cell mat in the refresh mode; And outputting the insulation signal as a level signal of a predetermined level by using a latch circuit in an insulation signal generation operation corresponding to a mat selection signal, and disabling the insulation signal when the termination signal is enabled or when a redundancy signal is input. Signal generating means; characterized in that it comprises a.

The cell mat isolation method of the semiconductor memory device may include: a) generating a termination signal after the last word line of the cell mat is activated in the refresh mode; b) generating a latch control signal in response to the end signal and the redundancy signal; And c) generating an isolation signal corresponding to the latch control signal and the mat selection signal.

Hereinafter, with reference to the accompanying drawings will be described in detail a preferred embodiment of the present invention.

2 is a block diagram showing a configuration of a cell mat insulation control circuit of a semiconductor memory device according to the present invention.

As shown, the cell mat isolation control circuit 10 of the semiconductor memory device according to the present invention receives an end word line selection signal lws and a refresh signal rfsh to generate an end signal fnsh. (110), the latch control means 120 for generating a latch control signal (lcnt) corresponding to the end signal (fnsh) and the first and second redundancy signals (rdcy <1: 2>) and the latch control signal ( and an isolation signal generating means 130 for generating an isolation signal iso in response to lcnt and the mat selection signal cms.

The last word line selection signal lws is a signal that is enabled when the last word line of a plurality of word lines provided per cell mat is activated. The final word line selection signal lws is generated by decoding an external address. The termination control means 110 enables and outputs the termination signal fnsh when the final word line selection signal lws is enabled in the refresh mode.

Thereafter, the latch control means 120 disables and outputs the latch control signal lcnt when both the termination signal fnsh and the first and second redundancy signals rdcy <1: 2> are disabled. . However, when one of the termination signal fnsh and one of the first and second redundancy signals rdcy <1: 2> is enabled, the latch control signal lcnt is enabled and output.

At this time, the first redundancy signal (rdcy <1>) is a redundancy operation to any word line of the cell mat of the preceding stage during the repair for any word line in the cell mat matching the cell mat isolation control circuit 10. This signal contains information that it performs In addition, the second redundancy signal rdcy <2> is a signal containing information that a redundancy operation is performed on an arbitrary word line of a cell mat of a later stage. The first and second redundancy signals rdcy <1: 2> are signals generated from a configuration of a general fuse circuit, and generally use signals used for redundancy operation in the present invention.

The isolation signal generating means 130 generates the isolation signal iso in response to the latch control signal lnt and the mat selection signal cms. When the mat select signal cms is enabled, the insulation signal iso is also enabled to insulate the corresponding insulation line. At this time, a latch circuit is provided in the insulation signal generating means 130, and thus the insulation signal iso becomes a level signal of a predetermined level. However, when the refresh operation for the cell mat is completed, the isolation signal iso that is continuously enabled by the configuration of the latch circuit must be disabled. At this time, the latch control signal lcnt is enabled and thus the isolation signal iso is disabled.

In addition, when a redundancy cell is provided in an adjacent cell mat during a repair operation on any word line of the cell mat matching the cell mat insulation control circuit 10, the isolation signal iso should be disabled. This is because adjacent cell mats can use sense amplifiers that exist between them when redundancy of the isolation lines is released during redundancy to adjacent cell mats. Information about the redundancy operation to the adjacent cell mat is transmitted to the isolation signal generating means 130 by the latch control signal lcnt.

The last word line selection signal lws, the refresh signal rfsh, and the isolation signal as mentioned above are high enable signals, the end signal fynsh, the first and the first signals. The two redundancy signals rdcy <1: 2>, the mat select signal cms, and the latch control signal lcnt are low enable signals.

FIG. 3 is a detailed configuration diagram of the termination control means shown in FIG. 2.

The termination control means 110 is a signal combination unit 112 for combining the final word line selection signal lws and the refresh signal rfsh, and a delay for delaying an output signal of the signal combination unit 112 by a predetermined time. The unit 114 includes a first driver 116 for non-inverting driving the output signal of the delay unit 114.

Here, the signal combination unit 112 receives a first inverter IV1 receiving the final word line selection signal lws, a first receiving the final word line selection signal lws and the refresh signal rfsh. A second NOR gate NR1 receiving the NAND gate ND1, an output signal of the first inverter IV1, an output signal of the first NAND gate ND1, and a second receiving the refresh signal rfsh. A second NOR gate NR2 receives an output signal of the inverter IV2 and the first NOR gate NR1 and an output signal of the second inverter IV2.

The delay unit 114 includes a delay unit DLY for delaying the output signal of the signal combination unit 112 by a predetermined time. The delay selector DLY may include the mat selection signal cms input to the insulation signal generating unit 130 when a last word line is selected and the last word line selection signal lws is enabled. ) Is earlier than the time when it is disabled.

The first driver 116 includes third and fourth inverters IV3 and IV4 for non-inverting driving the output signal of the delay unit 114.

Before the semiconductor memory device enters the refresh mode, the end signal ffnsh is enabled at a low level. In this case, whether to enable the insulation signal iso is determined depending on whether the mat selection signal cms input to the insulation signal generating unit 130 is enabled regardless of the final word line selection signal lws. do. However, when the semiconductor memory device enters a refresh mode, the end signal ffnsh is affected by the final word line selection signal lws. In this case, the end signal fnsh is disabled before the last word line selection signal lws is enabled. However, when the final word line selection signal lws is enabled, the end signal fnsh is enabled, and when the mat selection signal cms input to the isolation signal generating unit 130 is disabled, the isolation signal is disabled. (iso) is disabled and output.

FIG. 4 is a detailed configuration diagram of the latch control means shown in FIG. 2.

The latch control unit 120 receives the end signal f nsh and the first and second redundancy signals rdcy <1: 2> and outputs the second NAND gate ND2 to output the latch control signal lcnt. ).

In this configuration, when both the termination signal fnsh and the first and second redundancy signals rdcy <1: 2> are disabled, the latch control signal lnt is enabled, and the termination signal fnsh is enabled. ) And the latch control signal lcnt is disabled when any one of the first and second redundancy signals rdcy <1: 2> is enabled. That is, when the refresh operation on the corresponding cell mat ends, the end signal fnsh is enabled, and accordingly, the latch control signal lnt is disabled and the insulation signal output from the insulation signal generation unit 130 is output. (iso) is disabled. In addition, when a redundancy operation to an adjacent mat is performed when a word line of the corresponding cell mat is repaired, the latch control signal lcnt is disabled, and thus the isolation signal iso is disabled. In this case, the two sense amplifiers connected to the cell mat and the adjacent cell mat are isolated. However, when the repair operation is not performed during the refresh of the cell mat, the isolation signal iso is enabled to insulate the two sense amplifiers and the adjacent cell mat.

FIG. 5 is a detailed configuration diagram of the insulation signal generation means shown in FIG. 2.

The insulation signal generating unit 130 performs an operation of the second driver 131 in response to an input of the latch control signal lcnt and the second driver 131 for non-inverting driving the mat selection signal cms. The control unit 132 for controlling, the latch unit 133 for latching the output signal of the second driver 131, and the first and second comparison signals by inverting and non-inverting driving the output signals of the second driver 131. a signal generator 134 for generating cmp1 and cmp2, an output signal of the comparator 135 and the comparator 135 for comparing the first comparison signal cmp1 and the second comparison signal cmp2. Is configured as a third driver 136 which generates the insulation signal iso by non-inverting driving.

Herein, the second driver 131 receives a fifth inverter IV5 that receives the mat selection signal cms, an output signal of the fifth inverter IV5 is input to a gate terminal, and the controller 132 is connected to a source terminal. Output signal of the fifth inverter IV5 is input to the first transistor TR1 and the gate terminal of which the drain terminal is connected to the first node N1, and the drain terminal of the first node is connected to the first node N1. And a second transistor TR2 connected to N1) and having a source terminal grounded.

The control unit 132 receives the latch control signal lcnt at a gate terminal, an external supply power VDD at a source terminal, and a third transistor TR3 having a drain terminal connected to the second driver 131. ).

In addition, the latch unit 133 includes sixth and seventh inverters IV6 and IV7 for latching a signal applied to the first node N1.

The signal generator 134 inverts the signal applied to the first node N1 to output an eighth inverter IV8 and the first comparison signal cmp1 that output the first comparison signal cmp1. And a ninth inverter IV9 inverting and outputting the second comparison signal cmp2.

In addition, the comparison unit 135 outputs a high level signal when the potential of the first comparison signal cmp1 is higher than that of the second comparison signal cmp2, and the potential of the second comparison signal cmp2 is increased. The fourth to seventh transistors TR4 to TR7 outputting a low level signal when the voltage is higher than the potential of the first comparison signal cmp1.

Finally, the third driver 136 includes tenth and eleventh inverters IV11 and IV12 for non-inverting driving the output signal of the comparator 135.

In the active mode of the semiconductor memory device, the mat selection signal cms is enabled when data input / output operations are performed on a memory cell of a cell mat matching the cell mat insulation control circuit 10. When the mat selection signal cms is enabled, the first transistor TR1 of the second driver 131 is turned off and the second transistor TR2 is turned on. The potential of the first node N1 is at a low level. Thereafter, the potential of the first node N1 is stored by the latch unit 133, the first comparison signal cmp1 is maintained at a high level, and the second comparison signal cmp2 is at a low level. maintain. Accordingly, the isolation signal iso is enabled at a high level. Thereafter, when the mat selection signal cms is disabled, the first transistor TR1 of the second driver 131 is turned on and the second transistor TR2 is turned off. In this case, since the refresh signal rfsh input to the termination control means 110 is disabled, the termination signal fnsh is enabled and the third transistor TR3 of the controller 132 is turned on. Accordingly, a high level signal is stored in the latch unit 133 and the isolation signal iso is disabled.

In the refresh mode of the semiconductor memory device, when the refresh operation is performed on the cell mat, the mat selection signal cms is repeatedly enabled. In this case, even in the disable period of the mat selection signal cms, the potential level of the isolation signal iso is maintained to reduce the current consumption due to peak current generation. This is because the termination signal fnsh input to the controller 132 maintains a disabled state, and the latch unit 133 maintains a potential of a signal previously applied to the first node N1. However, when the redundancy operation to the adjacent cell mat is performed during the refresh operation of the cell mat or the refresh operation of the cell mat is completed, the isolation signal (iso) should be disabled. In the above two cases, the mat selection signal cms has a disable period, and the termination signal fnsh is enabled, so that the value of the signal stored in the latch unit 133 is changed. The signal iso is disabled.

That is, the cell mat isolation control circuit of the semiconductor memory device according to the present invention uses a latch circuit to generate an isolation signal, thereby continually maintaining the enable state of the isolation signal even during the disable period of the mat selection signal, thereby consuming current due to peak current. Decreases. In addition, when the redundancy operation to the adjacent cell mat is added, a circuit configuration is added to prevent side effects caused by sharing a sense amplifier with the adjacent cell mat to enable stable operation. Since a plurality of cell mats are provided in the semiconductor memory device, according to the present invention, the amount of current consumption reduced during the refresh operation is large, and thus the performance of the semiconductor memory device is improved.

As such, those skilled in the art will appreciate that the present invention can be implemented in other specific forms without changing the technical spirit or essential features thereof. Therefore, the above-described embodiments are to be understood as illustrative in all respects and not as restrictive. The scope of the present invention is shown by the following claims rather than the detailed description, and all changes or modifications derived from the meaning and scope of the claims and their equivalents should be construed as being included in the scope of the present invention. do.

The cell mat isolation control circuit and method of the semiconductor memory device of the present invention described above generate an isolation signal as a signal having a constant level to selectively insulate between the cell mat and the sense amplifier during a refresh operation to reduce current consumption. Therefore, there is an effect of preventing a malfunction by performing the insulation control operation in consideration of the redundancy operation.

Claims (23)

Termination control means for generating an termination signal after the last wordline of the cell mat is activated in the refresh mode; Latch control means for generating a latch control signal in response to the end signal and the redundancy signal; And Isolation signal generation means for generating an isolation signal in response to the latch control signal and the mat selection signal; Cell mat insulation control circuit of a semiconductor memory device comprising a. The method of claim 1, And the termination control means enables and outputs the termination signal when the final word line selection signal is enabled when the refresh signal is enabled, and outputs the termination signal. The method of claim 1, And the redundancy signal is a signal generated when a redundancy operation to an adjacent cell mat is performed. The method of claim 1, The isolation signal generating means maintains the enable state of the insulation signal even during the disable period of the mat select signal when the latch control signal is disabled, and disables the insulation signal when the latch control signal is enabled. A cell mat insulation control circuit of a semiconductor memory device. The method of claim 2, The termination control means, A signal combination unit combining the last word line selection signal and the refresh signal; And A delay unit for delaying an output signal of the signal combination unit by a predetermined time; Cell mat insulation control circuit of a semiconductor memory device comprising a. The method of claim 5, The signal combination unit, A first inverter receiving the last word line selection signal; A NAND gate receiving the last word line selection signal and the refresh signal; A first NOR gate receiving an output signal of the first inverter and an output signal of the NAND gate; A second inverter receiving the refresh signal; And A second NOR gate receiving an output signal of the first NOR gate and an output signal of the second inverter; Cell mat insulation control circuit of a semiconductor memory device comprising a. The method of claim 3, wherein And the latch control means comprises a NAND gate receiving the end signal and the redundancy signal and outputting the latch control signal. The method of claim 4, wherein The insulation signal generating means, A driver for non-inverting driving the mat selection signal; A control unit controlling an operation of the driving unit in response to an input of the latch control signal; A latch unit for latching an output signal of the driving unit; A signal generator configured to generate first and second comparison signals by inverting and non-inverting the output signal of the driver; And A comparison unit comparing the first comparison signal and the second comparison signal; Cell mat insulation control circuit of a semiconductor memory device comprising a. The method of claim 8, The control unit may include a transistor for inputting the latch control signal to a gate terminal, an external supply power to a source terminal, and a drain terminal to supply a power voltage to the driving unit as an output terminal. Insulation control circuit. Termination control means for generating an termination signal when the last wordline of the cell mat is activated in the refresh mode; And Insulation signal outputting the insulation signal as a level signal of a predetermined level using a latch circuit during an operation of generating an insulation signal corresponding to a mat selection signal, and an insulation signal for disabling the insulation signal when the termination signal is enabled or when a redundancy signal is input. Generating means; Cell mat insulation control circuit of a semiconductor memory device comprising a. The method of claim 10, And the termination control means enables and outputs the termination signal when the final word line selection signal is enabled when the refresh signal is enabled, and outputs the termination signal. The method of claim 10, And the redundancy signal is a signal generated when a redundancy operation to an adjacent cell mat is performed. The method of claim 10, The isolation signal generating means maintains the enable state of the insulation signal even in the disable period of the mat selection signal when the latch control signal is disabled as the end signal and the redundancy signal are disabled. And disabling the isolation signal when any one of redundancy signals is enabled and the latch control signal is enabled. The method of claim 11, The termination control means, A signal combination unit combining the last word line selection signal and the refresh signal; And A delay unit for delaying an output signal of the signal combination unit by a predetermined time; Cell mat insulation control circuit of a semiconductor memory device comprising a. The method of claim 14, The signal combination unit, A first inverter receiving the last word line selection signal; A NAND gate receiving the last word line selection signal and the refresh signal; A first NOR gate receiving an output signal of the first inverter and an output signal of the NAND gate; A second inverter receiving the refresh signal; And A second NOR gate receiving an output signal of the first NOR gate and an output signal of the second inverter; Cell mat insulation control circuit of a semiconductor memory device comprising a. The method of claim 13, The insulation signal generating means, A driver for non-inverting driving the mat selection signal; A control unit controlling an operation of the driving unit in response to an input of the latch control signal; A latch unit for latching an output signal of the driving unit; A signal generator configured to generate first and second comparison signals by inverting and non-inverting the output signal of the driver; And A comparison unit comparing the first comparison signal and the second comparison signal; Cell mat insulation control circuit of a semiconductor memory device comprising a. The method of claim 16, The control unit may include a transistor for inputting the latch control signal to a gate terminal, an external supply power to a source terminal, and a drain terminal to supply a power voltage to the driving unit as an output terminal. Insulation control circuit. a) generating a termination signal after the last wordline of the cell mat is activated in the refresh mode; b) generating a latch control signal in response to the end signal and the redundancy signal; And c) generating an isolation signal corresponding to the latch control signal and the mat selection signal; Cell mat insulation control method of a semiconductor memory device comprising a. The method of claim 18, And in the step a), when the final word line selection signal is enabled when the refresh signal is enabled, outputting by enabling the end signal. The method of claim 18, And the redundancy signal is a signal generated when a redundancy operation is performed to an adjacent cell mat. The method of claim 18, In the step c), when the latch control signal is disabled, the insulation signal is maintained in the disable period of the mat selection signal, and when the latch control signal is enabled, the insulation signal is disabled. Cell mat isolation control method of a semiconductor memory device. The method of claim 19, Step a) is a-1) combining the last word line selection signal and the refresh signal; And a-2) delaying the output signal of step a-1) by a predetermined time; Cell mat insulation control method of a semiconductor memory device comprising a. The method of claim 21, C), c-1) non-inverting driving the mat selection signal; c-2) controlling the operation of step c-1) in response to the input of the latch control signal; c-3) a latch unit for latching the output signal of step c-1); c-4) generating first and second comparison signals by inverting and non-inverting the output signal of step c-1); And c-5) comparing the first comparison signal with the second comparison signal; Cell mat insulation control method of a semiconductor memory device comprising a.

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