KR20080001281A - Non volatile memory device and method for manufacturing the same - Google Patents

Abstract

A nonvolatile memory device and a method for manufacturing the same are provided to increase trap density by performing SiH4 treatment to a Si3H4 layer as a charge storage layer, thereby increasing programming and erasing speed. A lower insulating layer(13) is formed on a substrate(11). A charge storage layer(17) is formed on the lower insulating layer. An upper insulating layer(18) is formed on the charge storage layer. A gate electrode(19) is then formed on the upper insulating layer. The charge storage layer further includes a first nitride layer(14) formed on the lower insulating layer, a silicon layer(15) formed on the first nitride layer, and a second nitride layer(16) formed on the silicon layer.

Description

Nonvolatile memory device and manufacturing method thereof {NON VOLATILE MEMORY DEVICE AND METHOD FOR MANUFACTURING THE SAME}

1 is a cross-sectional view of a silicon-oxide-nitride-oxide-semiconductor (SONOS) memory device according to the prior art;

2 is a cross-sectional view of a nonvolatile memory device according to an embodiment of the present invention.

3A to 3G are cross-sectional views illustrating a method of manufacturing the nonvolatile memory device shown in FIG. 2.

<Explanation of symbols for the main parts of the drawings>

1, 11: substrate

2, 12: device separator

3, 13: lower insulating film

4, 17: charge storage layer

5, 18: upper insulating film

6, 19: gate electrode

14: lower nitride film

15 silicon film

16: upper nitride film

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a manufacturing technology thereof, and more particularly, to a nonvolatile memory device having a silicon oxide nitride oxide (SONOS) structure or a metal oxide nitride oxide silicon (MONOS) and a method of manufacturing the same.

In general, semiconductor memory devices which are data memory devices in the information and communication field are classified into volatile memory devices and non-volatile memory devices. First, a volatile memory device is a memory device having a characteristic that data stored therein is lost when a power supply is cut off, such as RAM (Random Access Memory). On the other hand, nonvolatile memory devices include ROM (Read Only Memory) and the like that have a characteristic of not losing data stored even when the power supply is turned off.

Among the nonvolatile memory devices, charge-trapping devices may be used. For example, there is a floating gate type memory element, which is a field effect element in which charge is stored in an isolated conductor called a floating gate. The floating gate type memory device forms a floating gate, which is a conductor isolated by an insulating film formed between the substrate and the gate electrode, and performs a program by storing charge in the floating gate.

Since the floating gate type memory device uses a conductor floating gate, when a defect occurs in a portion of the tunnel insulating layer that separates the floating gate from the substrate, all of the charge stored in the floating gate may be lost. Accordingly, the floating gate type memory device requires a relatively thick tunnel oxide film as compared to the floating trap type memory device described later in the memory device in order to maintain reliability. In this case, as the thickness of the tunnel oxide film is increased, a high operating voltage is required, thereby requiring a complex peripheral circuit. As a result, there is a limit of device integration and high power consumption.

Meanwhile, another example of the charge trapping device is a floating trapping memory device that stores charge in an insulating bulk trap of the field effect device. The floating trap type memory device performs a program by a method of storing charge in a trap formed in an insulating charge storage layer provided between a gate electrode and a substrate. Examples of floating trapped memory devices include metal-nitride-oxide-semiconductor (MNOS), metal-alumina-oxide-semiconductor (MAOS), metal-alumina-semiconductor Oxide-Semiconductor (MAS), Silicon-Oxide-Nitride-Oxide-Semiconductor (SONOS) (hereinafter referred to as Sonos element), Metal-Oxide-Nitride And oxide-semiconductor (Metal Oxide Nitride Oxide Silicon (MONOS)).

1 is a cross-sectional view illustrating the structure of a sonos device according to the prior art.

As shown in FIG. 1, the sonos device includes a lower insulating film 3, a charge storage layer 4, an upper insulating film 5, and a gate electrode sequentially stacked on the substrate 1 on which the device isolation film 2 is formed. It consists of (6). In this case, the lower insulating film 3 and the upper insulating film 5 are formed of a CVD SiO ₂ film, and the charge storage layer 4 is formed of a silicon nitride film (Si ₃ N ₄ ).

Unlike the flash memory device, which is a floating gate type memory device, a sonoth device having such a structure is a floating trap type memory device and is formed on the nitride film interposed between the lower insulating film 3 and the upper insulating film 5, that is, the charge storage layer 4. The program is carried out in a manner that stores charge. However, there is a disadvantage in that the trap site in the nitride film used as the charge storage layer 4 is small so that a large amount of charge cannot be stored, and a program operation for storing charge in the trap site and an erase operation for removing the charge may be performed. There is a problem that the speed is reduced. This is because there is not enough trap site, and a high voltage is required in the program operation, and the charges trapped by the high voltage are trapped in a relatively deep trap site region or at the interface between the lower insulating film 3 and the charge storage layer 4. There is a problem that the erase is relatively difficult to trap, thereby reducing the erase operation speed.

Accordingly, an object of the present invention is to provide a nonvolatile memory device and a method of manufacturing the same, which have been proposed to solve the problems of the related art.

According to an aspect of the present invention, a lower insulating film formed on a substrate, a charge storage layer formed on the lower insulating film, an upper insulating film formed on the charge storage layer, and an upper insulating film And a gate electrode formed, wherein the charge storage layer includes a first nitride film formed on the lower insulating film, a silicon film formed on the first nitride film, and a second nitride film formed on the silicon film. Provided is an element.

According to another aspect of the present invention, there is provided a method of forming a lower insulating film on a substrate, forming a first nitride film on the lower insulating film, and forming a silicon film on the first nitride film. And forming a second nitride film on the silicon film, forming an upper insulating film on the second nitride film, and forming a gate electrode on the upper insulating film. Provided is a method for manufacturing a device.

The present invention intentionally performs a SiH ₄ gas treatment on the Si ₃ N ₄ layer, which is a charge storage layer, in order to increase the trap density, thereby creating a layer containing a large amount of silicon, thereby providing a program / The erase operation speed can be greatly improved.

DETAILED DESCRIPTION Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art may easily implement the technical idea of the present invention. In addition, in the drawings, the thicknesses of layers and regions are exaggerated for clarity, and in the case where the layers are said to be "on" another layer or substrate, they may be formed directly on another layer or substrate or Or a third layer may be interposed therebetween. In addition, the same reference numerals throughout the specification represent the same components.

Example

2 is a cross-sectional view illustrating the structure of a nonvolatile memory device according to an embodiment of the present invention.

As shown in FIG. 2, in the nonvolatile memory device according to the embodiment of the present invention, the charge storage layer 17 is formed in a stacked structure of the nitride film 14, the silicon film 15, and the nitride film 16. At this time, the nitride films 14 and 16 are made of a Si ₃ N ₄ film.

As described above, the charge storage layer 17 includes a silicon film 15 containing a large amount of silicon between the nitride films 14 and 16. The silicon film 15 containing a large amount of silicon has more trap sites than the stoichiometric Si ₃ N ₄ , so it is easy to program at a relatively low voltage, and trapped due to the programming operation by the low voltage. This can occur mainly at shallow trap sites to improve the speed of erase operations.

Hereinafter, a method of manufacturing a nonvolatile memory device according to an embodiment of the present invention having such a structure will be described with reference to FIGS. 3A to 3G. 3A to 3G are diagrams illustrating a manufacturing process of the method for manufacturing the nonvolatile memory device illustrated in FIG. 2.

First, as shown in FIG. 3A, a shallow trench isolation (STI) process is performed to form the device isolation layer 12 as an HDP (High Density Plasma) oxide film in the semiconductor substrate 11. At this time, the STI process consists of the following process. First, a pad oxide film and a pad nitride film, which are not shown, are sequentially deposited or formed on the substrate 11, and then a photolithography process is performed to have a predetermined depth in the substrate 11. Form a trench. Thereafter, the HDP oxide film is deposited to fill the trench, and then planarized through a chemical mechanical polishing (CMP) process, and the pad nitride film and the pad oxide film are removed to complete the device isolation film 12. Meanwhile, before forming the device isolation layer 12, a well ion implantation process is performed to form a well region (not shown) in the substrate 11. At this time, the well ion implantation process consists of the following process. First, a screen oxide layer (not shown) is formed on the substrate 11 and then a well ion implantation process is performed to form a well region. Here, the screen oxide film prevents the surface of the substrate 11 from being damaged during the well ion implantation process.

Subsequently, an ion implantation step for adjusting the threshold voltage may be performed. Of course, in some cases, the ion implantation process for adjusting the threshold voltage may be formed after the device isolation layer 12 is formed.

On the other hand, the screen oxide film is removed through a pre-cleaning process after the ion implantation process.

Subsequently, a lower insulating film 13 serving as a tunnel oxide film is formed on the substrate 11. In this case, the lower insulating layer 13 is formed by growing silicon of the substrate 11 through a thermal oxidation process, or is formed through a deposition process. The lower insulating film 13 is formed of a SiO ₂ film having a thickness of 20 or more.

Subsequently, as shown in FIG. 3B, a lower nitride film 14 is deposited on the lower insulating film 13. At this time, the lower nitride film 14 is formed to a thickness of 20 ~ 60Å by a Si ₃ N ₄ film using a CVD (chemical vapor deposition) or ALD (Automatic Layer Deposition) process.

Then, to form a lower nitride layer 14 (see Fig. 3b), SiH ₄ gas treatment (SiH ₄ gas treatment), the silicon film 15 is a silicon containing a large amount with respect to the embodiment as shown in Figure 3c. At this time, the SiH ₄ gas treatment is performed at a temperature of at least 400 ° C., preferably at 400 ° C. to 600 ° C., for 10 seconds to 10 minutes so that thermal decomposition occurs.

On the other hand, the SiH ₄ gas treatment may proceed in the process of forming the lower nitride film 14 and in-situ.

Next, as shown in FIG. 3D, an upper nitride film 16 is deposited on the silicon film 15. At this time, the upper nitride film 16 is formed to a thickness of 20 ~ 60Å by using a Si ₃ H ₄ film using a CVD or ALD process like the lower nitride film 14. As a result, the charge storage layer 17 having the structure in which the lower nitride film 14, the silicon film 15, and the upper nitride film 16 are stacked is completed.

Subsequently, as shown in FIG. 3E, the upper insulating film 18 is formed on the upper nitride film 16. At this time, the upper insulating film 18 is formed to a thickness of 50 ~ 300Å by using a silicon oxide film (SiO ₂ ) or an aluminum oxide film (Al ₂ O ₃ ). Here, the upper insulating film 18 isolates the charge storage layer 17 that stores charge from the gate electrode 19 (see FIG. 3F) to preserve charge stored in the charge storage layer 17, while the gate electrode 19 ) To form an electric field.

On the other hand, in the case of forming the upper insulating film 18 in the Al ₂ O ₃ film is subjected to RTP (Rapid Temperature Process) process by adding Al ₂ O ₃ film after deposition to cure film Al ₂ O _3. In addition, when the upper insulating film 18 is formed of a SiO ₂ film, it is formed using a CVD process.

Subsequently, as shown in FIG. 3F, the gate electrode 19 is formed on the upper insulating film 18.

In this case, the gate electrode 19 is formed of an undoped or low-doped polysilicon film having a low doping concentration when the sonos element is low. Here, the undoped polysilicon film is formed by using SiH ₄ gas by LPCVD (Low Pressure Chemical Vapor Deposition) method. In addition, the doped polysilicon layer is formed using Si ₂ H ₆ and PH ₃ gas by LPCVD, and the doping concentration is about 1E19 to 5E20 / cm 3 to minimize the gate depletion effect. In contrast, in the case of a monolith device, a work fucction is formed of a metal material having at least 4.5 eV, preferably 4.5 to 6 eV. For example, it is formed of TaN, TiN, WN and the like.

Subsequently, in the case of the sonos device, although not shown, a tungsten silicide (WSi) and a tungsten nitride film (WN) / tungsten silicide (WSi) film may be formed on the silicon silicon film to reduce the specific resistance of the polysilicon film. In the case of the monos device, a polysilicon film / WN / WSi film may be sequentially formed on the metal film, for example, in order to lower the specific resistance of the TaN film.

Subsequently, as illustrated in FIG. 3G, a hard mask (not shown) is deposited on the gate electrode 19, and then a photolithograpy process is performed to complete a gate having a stack structure.

Although the technical spirit of the present invention has been described in detail in the preferred embodiments, it should be noted that the above-described implementation is for the purpose of description and not of limitation. In addition, it will be understood by those skilled in the art that various embodiments are possible within the scope of the technical idea of the present invention.

As described above, according to the present invention, by intentionally performing SiH ₄ gas treatment on the Si ₃ N ₄ layer, which is a charge storage layer, a layer containing a large amount of silicon is locally formed, thereby increasing the trap density to program / erase It can greatly improve the operation speed.

Claims (20)

A lower insulating film formed on the substrate; A charge storage layer formed on the lower insulating film; An upper insulating film formed on the charge storage layer; And Including a gate electrode formed on the upper insulating film, The charge storage layer, A first nitride film formed on the lower insulating film; A silicon film formed on the first nitride film; And A second nitride film formed on the silicon film Nonvolatile memory device comprising a. The method of claim 1, And the gate electrode is formed of an undoped or doped polysilicon layer. The method of claim 2, And a tungsten silicide layer or a tungsten nitride / tungsten silicide layer formed on the gate electrode. The method of claim 1, And the gate electrode is made of a metal material having a work function of at least 4.5 eV. The method of claim 4, wherein And a polysilicon film / tungsten nitride film / tungsten silicide layer formed on the gate electrode. The method of claim 1, And the lower insulating film and the upper insulating film are made of a SiO ₂ film. The method of claim 1, The upper insulating layer is a nonvolatile memory device made of an Al ₂ O ₃ film. Forming a lower insulating film on the substrate; Forming a first nitride film on the lower insulating film; Forming a silicon film on the first nitride film; Forming a second nitride film on the silicon film; Forming an upper insulating film on the second nitride film; And Forming a gate electrode on the upper insulating film Method of manufacturing a nonvolatile memory device comprising a. The method of claim 8, And the silicon film is formed by performing a SiH ₄ gas treatment on the first nitride film. The method of claim 9, The SiH ₄ gas treatment is performed for 10 seconds to 10 minutes at 400 ~ 600 ℃ temperature method of manufacturing a nonvolatile memory device. The method of claim 9, The SiH ₄ gas treatment is performed in-situ with the first nitride film forming process. The method of claim 8, And the first and second nitride films are formed of a Si ₃ N ₄ film. The method of claim 8, And the gate electrode is formed of an undoped or doped polysilicon layer. The method of claim 13, And forming a tungsten silicide layer or a tungsten nitride film / tungsten silicide layer on the gate electrode. The method of claim 8, And the gate electrode is formed of a metal material having a work function of at least 4.5 eV. The method of claim 15, And forming a polysilicon film / tungsten nitride film / tungsten silicide layer on the gate electrode. The method of claim 8, And the lower insulating film and the upper insulating film are formed of a SiO ₂ film. The method of claim 8, The upper insulating film is a method of manufacturing a nonvolatile memory device formed of an Al ₂ O ₃ film The method of claim 8, Forming the upper insulating film, Depositing an Al ₂ O ₃ film on the second nitride film; And Curing the Al ₂ O ₃ film Method of manufacturing a nonvolatile memory device comprising a. The method of claim 19, Hardening the Al ₂ O ₃ film is a method of manufacturing a non-volatile memory device performed by the RTP process.

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