KR20080000780A - Fabrication method of a silicon substrate and method of forming a memory device using the same - Google Patents

Abstract

A method of manufacturing a silicon substrate and a method of forming a memory device using the same are provided to decrease a disturbance and a leakage current by minimizing a stress applied on a silicon substrate. An ion injection process is performed to inject fluorine ions into a P-type silicon substrate(100). The fluorine ions are injected, such that a thermal process is performed on the silicon substrate, on which defective crystals are formed. The ion injection process is performed by using a single-type ion injection device. The ion injection process is performed at a high energy between 1.2 and 2 MeV, such that a fluorine ion injection region(120) is formed on a lower layer of the silicon substrate.

Description

Fabrication method of a silicon substrate and method of forming a memory device using the same

1A and 1B are cross-sectional views illustrating a method of manufacturing a silicon substrate according to the present invention.

2 is a scanning electron microscope (SEM) photograph of a silicon substrate in which crystal defects are generated by lattice damage by a fluorine ion implantation process according to the present invention.

3 is a view showing the TED saturation time of boron according to the heat treatment temperature of the silicon substrate on which the crystal defect is formed according to the present invention.

4 is a schematic cross-sectional view illustrating a method of manufacturing a memory device using a silicon substrate according to the present invention.

<Explanation of symbols for the main parts of the drawings>

100, 200: silicon substrate 110, 210: boron

120, 220: fluorine ion implantation area 130: Defects

230: TN well or N well area 240: P well area

      250: gate oxide film pattern 260: polysilicon film pattern

The present invention relates to a method for manufacturing a silicon substrate, and more particularly, to a method for manufacturing a silicon substrate for forming a memory device that can minimize the stress of the silicon substrate.

In general, a silicon substrate used to manufacture a memory device is a P-type silicon substrate which is advantageous in terms of cost. P-type silicon substrate contains boron dopant from manufacture, and N-type of Phosphorus dopant is relatively low in stress due to boron, which lacks outermost atoms than silicon. Larger than a silicon substrate.

 Therefore, as the device becomes more integrated, there is a problem in that the performance of the transistor is degraded due to the occurrence of disturbance, threshold voltage shift and leakage current due to the stress of the P-type silicon substrate itself.

SUMMARY OF THE INVENTION An object of the present invention is to provide a method of manufacturing a silicon substrate for forming a memory device capable of improving the disturbance, threshold voltage shift and leakage current of a memory device by minimizing stress of the silicon substrate.

In order to achieve the above object, a method of manufacturing a silicon substrate according to the present invention includes: performing an ion implantation process for fluorine implantation in a P-type silicon substrate; And performing a heat treatment process on the silicon substrate in which the fluorine ions are implanted to generate crystal defects.

In order to achieve the above object, a method of forming a memory device according to the present invention comprises: performing an ion implantation process for fluorine implantation in a P-type silicon substrate; Performing a heat treatment process on the silicon substrate in which the fluorine ions are implanted to generate crystal defects; Performing an ion implantation process on the silicon substrate to form a TN well or an N well region; Performing an ion implantation process on the silicon substrate to form a P well region inside a TN well or N well region; Forming a patterned gate oxide layer on the silicon substrate; And forming a patterned polysilicon layer on the gate oxide layer.

Hereinafter, with reference to the accompanying drawings will be described an embodiment of the present invention in more detail.

1A and 1B are cross-sectional views illustrating a method of manufacturing a silicon substrate according to the present invention, and FIG. 2 is a scanning electron microscope of a silicon substrate in which crystal defects are generated by lattice damage by a fluorine ion implantation process according to the present invention. SEM (scanning electron microscope) photograph.

 Referring to FIG. 1A, a fluorine ion is injected into a predetermined region of the silicon substrate 100 by performing an ion implantation process for fluorine injection on the P-type silicon substrate 100 having the boron dopant 110 formed thereon. The injection region 120 is formed.

The fluorine ion implantation region 120 is formed in the lower layer of the silicon substrate 100 by heavy mass of fluorine.

The ion implantation process is performed using a single-type ion implantation device instead of a batch-type ion implantation device in order to prevent channeling due to a cone-angle effect.

The ion implantation process injects a dose of 1E12 to 1E15ions / cm 2 at a high energy of 1.2 to 2MeV.

Therefore, due to the high mass of fluorine ions implanted by the ion implantation process, the silicon substrate 100 is amorphized even at a low implantation amount, and crystal defects occur due to silicon lattice damage, for example, as shown in FIG. 2. The same {331} defect 130 behavior is seen.

  As described above, the silicon substrate 100 in which crystal defects are generated is blocked by fluorine ions as it becomes a structure that is vulnerable to transient enhanced diffusion (hereinafter referred to as 'TED') for obtaining a predetermined dopant distribution by crystal defects. The boron dopant is unable to diffuse impurities by TED.

Referring to FIG. 1B, the boron dopant in the silicon substrate 100 is gettered by performing a heat treatment process on the fluorine-infused silicon substrate 100.

The heat treatment process is carried out using a laser heat treatment (Raser anneal), Rapid Thermal Process (RTP) or Furnace (Furnace), and proceeds to 750 to 1000 ℃.

The heat treatment process may selectively run a laser source on the front side or the back side.

3 is a view showing the TED saturation time of boron according to the heat treatment temperature of the silicon substrate on which the crystal defect is formed according to the present invention.

As shown, it can be seen that the TED saturation time of the boron dopant increases as the heat treatment temperature of the silicon substrate on which the {311} defect such as a and b is formed increases.

That is, in the present invention, the crystal defects formed by the fluorine ions increase the TED of boron in the silicon substrate 100 when the heat treatment process is performed.

In the present invention, since the TED generation time increases due to the crystallization due to the heat treatment process, gettering of the boron dopant is generated for a long time to relieve stress of the silicon substrate 100.

Hereinafter, a method of forming a memory device using the silicon substrate manufactured by the present invention will be briefly described.

4 is a schematic cross-sectional view for describing a method of forming a memory device using a silicon substrate according to the present invention.

 First, the fluorine ion implantation region 220 is formed on the P-type silicon substrate 200 on which the boron 210 dopant is formed through a fluorine ion implantation process using a single ion implantation device, and then subjected to a heat treatment process. 210) The dopant is gettered to the fluorine ion implantation region 220.

The fluorine ion implantation process and the heat treatment process are the same as the method for producing a silicon substrate according to the present invention.

Thereafter, two impurity ion implantation processes are performed on the P-type silicon substrate 200 to form the TN well or N well region 230 on the fluorine implanted region 220, and the TN well or N well region 230. ) To form a P well region 240.

A gate oxide film (not shown) made of silicon oxide film (SiO ₂ ) and a polysilicon film (not shown) made of polysilicon are formed over the entire surface of the P-type silicon substrate 200 on which the P well region 240 is formed. .

The gate oxide film and the polysilicon film are formed by a chemical vapor deposition (CVD) method.

The gate oxide layer pattern and the polysilicon layer pattern are patterned using a mask (not shown) to complete a gate including the gate oxide layer pattern 250 and the polysilicon layer pattern 260.

In the present invention, since the concentration of the boron dopant of the P-type silicon substrate itself is reduced, it is possible to secure lower Rs when forming a TN well or N well of a subsequent process when forming a memory device using the same, thereby improving the disturbance and a stable threshold. The yield of memory devices can be improved by securing voltage, preventing leakage current, and improving latch-up.

Although the present invention has been described with respect to the preferred embodiment as described above, the present invention is not limited to this, and those skilled in the art to which the present invention pertains the claims and the detailed description of the invention and attached It is possible to carry out various modifications within the scope of the drawings and this also belongs to the scope of the present invention.

The present invention performs an ion implantation process for injecting fluorine with high ion implantation energy into a P-type silicon substrate, and then increases the TED generation time of the boron dopant by fluorine ions implanted through the heat treatment process to getter the boron dopant by The stress caused by the boron dopant of the -type silicon substrate can be minimized.

When forming a memory device using a silicon substrate manufactured by the present invention, it is possible to secure a low Rs when forming a subsequent TNW or NW, thereby improving the disturbance, securing a stable threshold voltage, preventing leakage current, and latching up. Through improved characteristics, the yield of the memory device may be improved.

Claims (9)

Performing an ion implantation process for fluorine implantation into the P-type silicon substrate; And And performing a heat treatment process on the silicon substrate in which the fluorine ions are implanted to generate crystal defects. The method of claim 1, The ion implantation process is a silicon substrate manufacturing method performed using a single-type ion implantation equipment. The method of claim 1, The ion implantation process is carried out at a high energy of 1.2 to 2MeV to form a fluorine ion implantation region in the lower layer of the silicon substrate. The method of claim 1, The ion implantation process is a method for producing a silicon substrate in which the ion implantation amount of 1E12 to 1E15ions / ㎠. The method of claim 1, The heat treatment process is a method of manufacturing a silicon substrate using a laser heat treatment, RTP heat treatment or furnace (Furnace). The method of claim 5, The heat treatment step is a method of manufacturing a silicon substrate to proceed at 750 to 1000 ℃. The method of claim 1, The heat treatment process is a method of manufacturing a silicon substrate to advance the laser source to the front or back. Providing a silicon substrate prepared by claim 1; And Forming a gate oxide pattern and a polysilicon layer pattern on the silicon substrate. The method of claim 8, And the silicon substrate has a fluorine ion implantation region deeper than a depth at which a well is formed.

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