KR20070122050A - Pattern forming method using double patterning process - Google Patents

Pattern forming method using double patterning process Download PDF

Info

Publication number
KR20070122050A
KR20070122050A KR1020060057023A KR20060057023A KR20070122050A KR 20070122050 A KR20070122050 A KR 20070122050A KR 1020060057023 A KR1020060057023 A KR 1020060057023A KR 20060057023 A KR20060057023 A KR 20060057023A KR 20070122050 A KR20070122050 A KR 20070122050A
Authority
KR
South Korea
Prior art keywords
hard mask
pattern
layer
exposure
mask layer
Prior art date
Application number
KR1020060057023A
Other languages
Korean (ko)
Inventor
김형수
Original Assignee
주식회사 하이닉스반도체
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 주식회사 하이닉스반도체 filed Critical 주식회사 하이닉스반도체
Priority to KR1020060057023A priority Critical patent/KR20070122050A/en
Publication of KR20070122050A publication Critical patent/KR20070122050A/en

Links

Images

Classifications

    • G—PHYSICS
    • G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
    • G03F7/0035—Multiple processes, e.g. applying a further resist layer on an already in a previously step, processed pattern or textured surface
    • G—PHYSICS
    • G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
    • G03F7/20—Exposure; Apparatus therefor
    • G03F7/2022—Multi-step exposure, e.g. hybrid; backside exposure; blanket exposure, e.g. for image reversal; edge exposure, e.g. for edge bead removal; corrective exposure
    • G—PHYSICS
    • G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
    • G03F7/70—Microphotolithographic exposure; Apparatus therefor
    • G03F7/70425—Imaging strategies, e.g. for increasing throughput or resolution, printing product fields larger than the image field or compensating lithography- or non-lithography errors, e.g. proximity correction, mix-and-match, stitching or double patterning
    • G03F7/70466—Multiple exposures, e.g. combination of fine and coarse exposures, double patterning or multiple exposures for printing a single feature
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/033—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers
    • H01L21/0334—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
    • H01L21/0337—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane characterised by the process involved to create the mask, e.g. lift-off masks, sidewalls, or to modify the mask, e.g. pre-treatment, post-treatment
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/033—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers
    • H01L21/0334—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
    • H01L21/0338—Process specially adapted to improve the resolution of the mask
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/308—Chemical or electrical treatment, e.g. electrolytic etching using masks
    • H01L21/3083—Chemical or electrical treatment, e.g. electrolytic etching using masks characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
    • H01L21/3086—Chemical or electrical treatment, e.g. electrolytic etching using masks characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane characterised by the process involved to create the mask, e.g. lift-off masks, sidewalls, or to modify the mask, e.g. pre-treatment, post-treatment
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/308—Chemical or electrical treatment, e.g. electrolytic etching using masks
    • H01L21/3083—Chemical or electrical treatment, e.g. electrolytic etching using masks characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
    • H01L21/3088—Process specially adapted to improve the resolution of the mask

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Inorganic Chemistry (AREA)
  • Preparing Plates And Mask In Photomechanical Process (AREA)
  • Exposure And Positioning Against Photoresist Photosensitive Materials (AREA)

Abstract

A method for forming a capacitor pattern using a double patterning process is provided to increase the surface area of a capacitor pattern by forming a quadrilateral capacitor pattern in a region where first and second masks cross each other. A first hard mask layer, an interlayer hard mask layer(112), a second hard mask layer and a first photoresist layer are sequentially formed on a semiconductor substrate. The second hard mask layer is etched by a lithography process using a first exposure mask made of a line/space type. After a second photoresist layer is coated on the front surface of the resultant structure, the interlayer hard mask layer is etched by a lithography process using a second exposure mask having pattern crossing a first exposure mask wherein the first and the second exposure masks form an angle of 0-179 degrees. A blanket etch process is performed on the second and first hard mask layers so that the first hard mask is patterned to form a quadrilateral capacitor pattern. The first and the second hard mask layers can be polysilicon layers, and the interlayer hard mask layer can be a silicon nitride layer.

Description

이중 패터닝 공정을 이용한 캐패시터 패턴 형성 방법{Pattern forming method using double patterning process}Pattern forming method using double patterning process

도 1 및 도 2a는 본 발명의 제1 노광 공정을 수행하는 공정도.1 and 2A are process diagrams for performing a first exposure process of the present invention.

도 2b는 도 2a에 도시된 제1 노광 공정과 제1 식각 공정을 수행한 후의 평면도.FIG. 2B is a plan view after performing the first exposure process and the first etching process illustrated in FIG. 2A.

도 3a는 제2 노광 마스크의 평면도.3A is a plan view of a second exposure mask.

도 3b는 도 3a의 노광 마스크를 이용하여 감광제를 현상한 후의 평면도.3B is a plan view after developing the photosensitive agent using the exposure mask of FIG. 3A.

도 4a는 도 3b의 감광제 패턴을 식각 마스크로 층간 하드마스크층을 식각한 후의 평면도.4A is a plan view after etching the interlayer hardmask layer with the photoresist pattern of FIG. 3B as an etch mask;

도 4b는 도 4a의 AA' 단면도.4B is a sectional view taken along line AA ′ of FIG. 4A;

도 4c는 도 4a의 BB' 단면도.4C is a cross-sectional view taken along line BB ′ of FIG. 4A.

도 5a는 도 4a의 층간 하드마스크를 이용한 전면 식각 후의 평면도.Figure 5a is a plan view after the front surface etching using the interlayer hard mask of Figure 4a.

도 5b는 도 5a의 AA' 단면도.FIG. 5B is a sectional view taken along line AA ′ of FIG. 5A;

도 5c는 도 5a의 BB' 단면도.FIG. 5C is a cross-sectional view taken along line BB ′ of FIG. 5A.

<도면의 주요 부분에 대한 부호의 설명><Explanation of symbols for the main parts of the drawings>

100: 반도체 기판 110: 제1 하드마스크층100: semiconductor substrate 110: first hard mask layer

112: 층간 하드마스크층 114: 제2 하드마스크층112: interlayer hard mask layer 114: second hard mask layer

110': 제1 하드마스크 패턴 112': 층간 하드마스크 패턴110 ': first hardmask pattern 112': interlayer hardmask pattern

114': 제2 하드마스크 패턴114 ': Second Hardmask Pattern

120: 제1 감광제 패턴 122: 제2 감광제 패턴120: first photosensitizer pattern 122: second photosensitizer pattern

130: 제1 노광 마스크 132: 제2 노광 마스크130: first exposure mask 132: second exposure mask

134: 광 차단층 136: 광 투과층134: light blocking layer 136: light transmitting layer

본 발명은 이중 노광 및 이중 식각 공정을 이용한 캐패시터 패턴 형성방법에 관한 것으로, 구체적으로는 라인/스페이스 (line and space) 형태의 노광 마스크를 이용하여 1차 노광 및 2차 노광시 노광 마스크가 서로 교차하도록 이중 노광 공정을 수행하는 이중 패터닝 공정을 적용함으로써 사각형의 캐패시터 패턴을 형성할 수 있는 방법에 관한 것이다.The present invention relates to a method of forming a capacitor pattern using a double exposure and a double etching process. Specifically, the exposure masks cross each other during the first exposure and the second exposure using a line-and-space exposure mask. The present invention relates to a method for forming a rectangular capacitor pattern by applying a double patterning process for performing a double exposure process.

캐패시터는 DRAM 메모리 소자의 집적화를 이루는 필수 패턴이며, 집적도가 높아질수록 패턴 크기가 작아져 충분한 용량의 축전 용량 확보가 매우 어려운 것으로 알려져 있다. 축전 용량을 증대시키기 위해서는 캐패시터 패턴의 표면적 증가가 필수적인데, 현재 80nm급 이하의 DRAM 메모리 소자는 대부분 원통형 모양을 갖는 실린더형 캐패시터 (cylindrical capacitor) 패턴을 채택하고 있다.Capacitors are an essential pattern for integrating DRAM memory devices, and as the degree of integration increases, the pattern size decreases, and it is known that it is very difficult to secure a sufficient capacitance. In order to increase the capacitance, it is necessary to increase the surface area of the capacitor pattern. Currently, DRAM memory devices of 80 nm or less adopt a cylindrical capacitor pattern having a mostly cylindrical shape.

실린더형 캐패시터 패턴 형성 공정의 큰 문제점은 통상적인 방법을 이용한 표면적의 증가가 한계에 달했다는 것과, 집적도가 증가할수록 각 패턴 간의 무너짐 (collapse) 또는 기울어짐 (leaning) 현상에 의해 캐패시터 브리지 (bridge)가 발생한다는 것이다.The big problem with the cylindrical capacitor pattern forming process is that the increase of the surface area using the conventional method has reached its limit, and as the degree of integration increases, the capacitor bridge is caused by the collapse or the leaning between the patterns. Will occur.

한편, 실린더형 캐패시터 패턴을 형성하기 위한 종래의 노광 기술은 콘택홀 형태의 마스크를 이용하는 것인데, 통상적으로 콘택홀 형태의 마스크는 라인/스페이스 형태의 마스크를 이용하는 것에 비해 해상력이 좋지 않기 때문에 보다 미세한 캐패시터 패턴을 형성하기 어렵다.On the other hand, a conventional exposure technique for forming a cylindrical capacitor pattern is to use a contact hole type mask, the contact hole type mask is typically a finer capacitor because the resolution is not as good as using a line / space type mask It is difficult to form a pattern.

이에, 본 발명의 목적은 캐패시터의 표면적을 증가할 수 있음과 동시에 패턴 간 무너짐 또는 기울어짐 현상이 발생하지 않는 캐패시터 패턴의 형성방법을 제공하는 것이다.Accordingly, an object of the present invention is to provide a method of forming a capacitor pattern which can increase the surface area of the capacitor and does not cause collapse or tilt between patterns.

상기와 같은 목적을 달성하기 위하여, 본 발명에서는 라인/스페이스 형태의 노광 마스크를 이용하여 1차 노광 및 2차 노광시 노광 마스크 패턴이 서로 교차하도록 이중 노광 공정을 수행하는 이중 패터닝 공정을 적용함으로써 사각형의 캐패시터 패턴을 형성할 수 있는 방법을 제공한다.In order to achieve the above object, in the present invention, by applying a double patterning process for performing a double exposure process so that the exposure mask pattern crosses each other in the first and second exposure using a line / space type exposure mask It provides a method that can form a capacitor pattern.

구체적으로 본 발명에서는 Specifically in the present invention

반도체 기판 상에 제1 하드마스크층, 층간 하드마스크층, 제2 하드마스크층 및 제1 감광제층을 순차적으로 형성하는 단계;Sequentially forming a first hard mask layer, an interlayer hard mask layer, a second hard mask layer, and a first photoresist layer on the semiconductor substrate;

라인/스페이스 형태로 구성된 제1 노광 마스크를 이용한 리소그라피 공정에 의해 제2 하드마스크층을 식각하는 단계;Etching the second hard mask layer by a lithography process using a first exposure mask configured in line / space form;

상기 결과물 전면에 제2 감광제층을 도포한 후 제1 노광 마스크와 0~179。의 각을 이루며 교차하는 패턴을 갖는 제2 노광 마스크를 이용한 리소그라피 공정에 의해 상기 층간 하드마스크층을 식각하는 단계; 및Etching the inter-layer hard mask layer by means of the resultant entire surface of the second lithography process after coating the photosensitive material layer using a second exposure mask having a pattern which crosses constitutes the first exposure of each of the mask and 0-179; And

제2 하드마스크층 및 제1 하드마스크층에 대한 전면 식각을 수행하여 상기 제1 하드마스크를 패터닝하여 사각형의 캐패시터 패턴을 얻는 단계를 포함하는 반도체 소자의 제조방법을 제공한다.A method of fabricating a semiconductor device, the method comprising: etching a second hard mask layer and a first hard mask layer to pattern the first hard mask to obtain a rectangular capacitor pattern.

이때, 제1 노광 마스크와 제2 노광 마스크는 공정의 목적에 따라, 임의의 각도로 교차할 수 있으며, 수직으로 교차하는 것이 바람직하다.In this case, the first exposure mask and the second exposure mask may intersect at an arbitrary angle, depending on the purpose of the process, and preferably cross vertically.

상기 제2 하드마스크층 및 제1 하드마스크층은 폴리실리콘층이고, 층간 하드마스크층은 실리콘 질화막으로 이루어진 것을 사용할 수 있다.The second hard mask layer and the first hard mask layer may be polysilicon layers, and the interlayer hard mask layer may be formed of a silicon nitride film.

상기 공정에서, 각각의 식각 공정은 건식 식각이자 이방성 식각 공정이다.In this process, each etching process is a dry etching and an anisotropic etching process.

이하, 본 발명의 이중 노광 공정 및 이중 식각 공정을 이용한 패턴 형성방법에 대하여 도면을 참조하여 설명한다.Hereinafter, a pattern forming method using the double exposure process and the double etching process of the present invention will be described with reference to the drawings.

반도체 기판 (100) 상에 제1 하드마스크층 (110), 층간 하드마스크층 (112), 제2 하드마스크층 (114) 및 제 1 감광제 (미도시)를 순차적으로 적층한다 (도 1 참조).The first hard mask layer 110, the interlayer hard mask layer 112, the second hard mask layer 114, and the first photosensitive agent (not shown) are sequentially stacked on the semiconductor substrate 100 (see FIG. 1). .

이때, 제2 하드마스크층 (114) 및 제1 하드마스크층 (110)은 폴리실리콘으로 형성하고, 층간 하드마스크층 (112)는 실리콘 질화막으로 형성한다.In this case, the second hard mask layer 114 and the first hard mask layer 110 are formed of polysilicon, and the interlayer hard mask layer 112 is formed of a silicon nitride film.

다음, 라인/스페이스 형태로 구성된 제1 노광 마스크 (130)로 노광 및 현상 하여 제1 감광제 패턴 (120)을 형성한 후 이를 식각 마스크로 제2 하드마스크층 (114)를 식각하여 제2 하드마스크 패턴 (114')을 라인/스페이스 패턴 형태로 형성한다 (도 2a 참조).Subsequently, the first photoresist pattern 120 is formed by exposing and developing the first exposure mask 130 having a line / space shape, and the second hard mask layer 114 is etched using the etching mask to etch the second hard mask. Pattern 114 ′ is formed in the form of a line / space pattern (see FIG. 2A).

도 2b는 상기 도 2a의 제1 노광 및 제1 식각 공정을 수행한 후 제1 감광제 패턴 (120)을 제거한 후의 평면도이다.FIG. 2B is a plan view after removing the first photoresist pattern 120 after performing the first exposure and first etching processes of FIG. 2A.

다음, 도 2b에 나타낸 구조 전면에 제2 감광제 (미도시)를 도포한 다음, 도 3a에 나타낸 바와 같이, 제1 노광 마스크 (130)의 마스크 패턴과 수직으로 교차하는 마스크 패턴을 갖는 제2 노광 마스크 (132)를 이용하여 제2 노광을 하고, 현상 공정을 수행한다.Next, a second photosensitive agent (not shown) is applied to the entire structure shown in FIG. 2B, and then, as shown in FIG. 3A, a second exposure having a mask pattern perpendicular to the mask pattern of the first exposure mask 130. The second exposure is performed using the mask 132, and a developing process is performed.

그 결과, 광 차단층 (134) 부위, 즉 비노광부에는 제2 감광제 패턴 (122)이 형성되고, 광 투과층 (136) 부위, 즉 노광부에는 층간 하드마스크층 (112)과 제2 하드마스크 패턴 (114')이 노출된다. 즉, 제1 노광마스크 (130)와 제2 노광 마스크 (132)가 교차되는 부위에는 실리콘 질화막 (112)이 노출됨을 알 수 있다 (도 3b 참조).As a result, the second photoresist pattern 122 is formed in the portion of the light blocking layer 134, that is, the non-exposed portion, and the interlayer hard mask layer 112 and the second hard mask are disposed in the portion of the light transmitting layer 136, that is, the exposed portion. Pattern 114 ′ is exposed. That is, it can be seen that the silicon nitride film 112 is exposed at a portion where the first exposure mask 130 and the second exposure mask 132 cross each other (see FIG. 3B).

다음, 상기 제2 감광제 패턴 (122)을 식각 마스크로 층간 하드마스크층 (112)을 식각하는데, 제1 하드마스크층 (110)이 노출되며, 제2 하드마스크층 패턴 (114') 하부에는 층간 하드마스크층 패턴 (112')이 형성된다. 즉, 제1 노광마스크 (130) 패턴과 제2 노광 마스크 (132) 패턴이 교차되는 부위에는 사각형의 패턴이 형성되고 제1 하드마스크 물질인 폴리실리콘 (110)이 노출됨을 알 수 있다 (도 4a 내지 도 4c 참조).Next, the interlayer hard mask layer 112 is etched using the second photoresist pattern 122 as an etch mask, and the first hard mask layer 110 is exposed, and the interlayer is disposed below the second hard mask layer pattern 114 ′. The hard mask layer pattern 112 'is formed. That is, it can be seen that a rectangular pattern is formed at a portion where the first exposure mask 130 pattern and the second exposure mask 132 pattern intersect, and the polysilicon 110, which is the first hard mask material, is exposed (FIG. 4A). To FIG. 4C).

다음, 3차 식각으로서 폴리실리콘을 전면 식각하면 노출된 폴리실리콘인 제2 하드마스크층 패턴 (114') 및 제1 하드마스크층 (110)이 식각되어, 두 마스크 패턴이 교차하던 부위의 제2 하드마스크와 제1 하드마스크는 완전히 제거되고 사각형 캐패시터 하부 전극이 형성됨을 확인할 수 있다 (도 5a 내지 도 5c 참조).Next, when the polysilicon is fully etched as the third etching, the second hard mask layer pattern 114 ′ and the first hard mask layer 110, which are exposed polysilicon, are etched to form a second portion of the portion where the two mask patterns cross each other. It can be seen that the hard mask and the first hard mask are completely removed and a rectangular capacitor lower electrode is formed (see FIGS. 5A to 5C).

상기 실시예에서는 제1 노광 마스크와 제2 노광 마스크 패턴이 수직으로 교차하는 경우를 예로 들었으나, 소자의 구조에 따라 제1 마스크와 제2 마스크 패턴은 임의의 각도로 교차할 수 있다. 즉, 패턴의 기울어짐을 방지하기 위하여 패턴 간의 최소 이격 거리를 증가시킬 목적으로 공정을 진행할 수도 있는데, 이 경우 실시예에서와 같이 90。로 교차하는 것이 아니라 +45。 및 -45。 등의 조합도 가능하다. 이러한 교차 각도에 따라 사각형 캐패시터 패턴의 모양도 정방형, 장방형 또는 마름모형 등 다양하게 형성될 수 있다.In the above embodiment, the case in which the first exposure mask and the second exposure mask pattern cross each other vertically is taken as an example, but the first mask and the second mask pattern may cross at an arbitrary angle according to the structure of the device. That is, there may proceed with the process for the purpose of increasing the minimum separation distance between the pattern to prevent tipping of the pattern, in this case, rather than intersecting with 90. As in the embodiment +45. And -45. Combination of Fig. It is possible. According to the crossing angle, the rectangular capacitor pattern may have various shapes such as square, rectangular or rhombus.

본 발명의 바람직한 실시예는 예시의 목적을 위한 것으로, 당업자라면 첨부된 특허청구범위의 기술적 사상과 범위를 통해 다양한 수정, 변경, 대체 및 부가가 가능할 것이며, 이러한 수정 변경 등은 이하의 특허청구범위에 속하는 것으로 보아야 할 것이다.Preferred embodiments of the present invention are for the purpose of illustration, and those skilled in the art will be able to make various modifications, changes, substitutions and additions through the spirit and scope of the appended claims, and such modifications may be made by the following claims. Should be seen as belonging to.

이상에서 살펴본 바와 같이, 본 발명에서는 라인/스페이스 패턴 형태로 제작된 제1 노광 마스크에, 소정의 각도로 교차되는 패턴을 갖는 제2 노광 마스크를 이용하여 이중 노광 및 이중 식각을 실시하여 제1 마스크와 제2 마스크가 교차되는 지역에 원통형이 아닌 사각형 캐패시터 패턴을 형성할 수 있었다. 이에 따라, 본 발명으로 얻어진 캐패시터 패턴은 종래의 원통형 패턴에 비해 표면적이 넓기 때문에 패턴 간의 거리를 이격시킬 수 있어 패턴 무너짐 및 기울어짐에 강한 장점을 갖는다.As described above, in the present invention, the first exposure mask fabricated in the form of a line / space pattern is subjected to double exposure and double etching using a second exposure mask having a pattern crossing at a predetermined angle to perform a first mask. It was possible to form a non-cylindrical rectangular capacitor pattern in the region where the and the second mask intersect. Accordingly, since the capacitor pattern obtained by the present invention has a wider surface area than the conventional cylindrical pattern, the distance between the patterns can be spaced apart, thereby having a strong advantage in pattern collapse and inclination.

Claims (4)

반도체 기판 상에 제1 하드마스크층, 층간 하드마스크층, 제2 하드마스크층 및 제1 감광제층을 순차적으로 형성하는 단계;Sequentially forming a first hard mask layer, an interlayer hard mask layer, a second hard mask layer, and a first photoresist layer on the semiconductor substrate; 라인/스페이스 형태로 구성된 제1 노광 마스크를 이용한 리소그라피 공정에 의해 제2 하드마스크층을 식각하는 단계;Etching the second hard mask layer by a lithography process using a first exposure mask configured in line / space form; 상기 결과물 전면에 제2 감광제층을 도포한 후 제1 노광 마스크와 0~179。의 각을 이루며 교차하는 패턴을 갖는 제2 노광 마스크를 이용한 리소그라피 공정에 의해 상기 층간 하드마스크층을 식각하는 단계; 및Etching the inter-layer hard mask layer by means of the resultant entire surface of the second lithography process after coating the photosensitive material layer using a second exposure mask having a pattern which crosses constitutes the first exposure of each of the mask and 0-179; And 제2 하드마스크층 및 제1 하드마스크층에 대한 전면 식각을 수행하여 상기 제1 하드마스크를 패터닝하여 사각형의 캐패시터 패턴을 얻는 단계를 포함하는 반도체 소자의 제조방법.And etching the second hard mask layer and the first hard mask layer to pattern the first hard mask to obtain a rectangular capacitor pattern. 제1항에 있어서,The method of claim 1, 상기 제2 노광 마스크 패턴은 제1 노광 마스크 패턴과 수직으로 교차하는 것을 특징으로 하는 반도체 소자의 제조방법.And the second exposure mask pattern perpendicularly intersects the first exposure mask pattern. 제1항에 있어서,The method of claim 1, 상기 제1 하드마스크층 및 제2 하드마스크층은 폴리실리콘층이고, 층간 하드 마스크층은 실리콘 질화막인 것을 특징으로 하는 반도체 소자의 제조방법.Wherein the first hard mask layer and the second hard mask layer are polysilicon layers, and the interlayer hard mask layer is a silicon nitride film. 제1항에 있어서,The method of claim 1, 상기 각각의 식각 공정은 건식 식각 및 이방성 식각인 것을 특징으로 하는 반도체 소자의 제조방법.Wherein each of the etching processes is dry etching and anisotropic etching.
KR1020060057023A 2006-06-23 2006-06-23 Pattern forming method using double patterning process KR20070122050A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1020060057023A KR20070122050A (en) 2006-06-23 2006-06-23 Pattern forming method using double patterning process

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1020060057023A KR20070122050A (en) 2006-06-23 2006-06-23 Pattern forming method using double patterning process

Publications (1)

Publication Number Publication Date
KR20070122050A true KR20070122050A (en) 2007-12-28

Family

ID=39139103

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1020060057023A KR20070122050A (en) 2006-06-23 2006-06-23 Pattern forming method using double patterning process

Country Status (1)

Country Link
KR (1) KR20070122050A (en)

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100968414B1 (en) * 2008-08-29 2010-07-07 주식회사 하이닉스반도체 Method for fabricating semiconductor device
US8198664B2 (en) 2009-02-12 2012-06-12 Samsung Electronics Co., Ltd. Semiconductor memory device having cylinder-type capacitor lower electrode and associated methods
US8308966B2 (en) 2009-03-31 2012-11-13 Hynix Semiconductor, Inc. Method for fabricating semiconductor device using a double patterning process
KR101469098B1 (en) * 2008-11-07 2014-12-04 삼성전자주식회사 Method for formation of capacitor of semiconductor memory device
CN109791874A (en) * 2016-09-22 2019-05-21 瓦里安半导体设备公司 The technology of user's tropism ion formation patterned features
CN112670245A (en) * 2019-10-15 2021-04-16 长鑫存储技术有限公司 Method for manufacturing semiconductor element

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100968414B1 (en) * 2008-08-29 2010-07-07 주식회사 하이닉스반도체 Method for fabricating semiconductor device
KR101469098B1 (en) * 2008-11-07 2014-12-04 삼성전자주식회사 Method for formation of capacitor of semiconductor memory device
US8198664B2 (en) 2009-02-12 2012-06-12 Samsung Electronics Co., Ltd. Semiconductor memory device having cylinder-type capacitor lower electrode and associated methods
US8308966B2 (en) 2009-03-31 2012-11-13 Hynix Semiconductor, Inc. Method for fabricating semiconductor device using a double patterning process
CN109791874A (en) * 2016-09-22 2019-05-21 瓦里安半导体设备公司 The technology of user's tropism ion formation patterned features
CN109791874B (en) * 2016-09-22 2022-11-29 瓦里安半导体设备公司 Methods of patterning a substrate and layers disposed thereon and forming device structures
CN112670245A (en) * 2019-10-15 2021-04-16 长鑫存储技术有限公司 Method for manufacturing semiconductor element

Similar Documents

Publication Publication Date Title
US7745339B2 (en) Method for forming fine pattern of semiconductor device
KR100876808B1 (en) Method for Pattern Formation of Semiconductor Device
KR100934836B1 (en) Micro pattern formation method of semiconductor device
JP6715415B2 (en) Method and system for forming a memory fin pattern
JP2005150333A (en) Method of manufacturing semiconductor device
US7651950B2 (en) Method for forming a pattern of a semiconductor device
US9069249B2 (en) Self aligned patterning with multiple resist layers
KR20070122050A (en) Pattern forming method using double patterning process
TWI665715B (en) Method for patterning a substrate using a layer with multiple materials
US7943521B2 (en) Method for patterning a semiconductor device
KR20120126442A (en) Method for forming pattern of Semiconductor Device
JPH06326061A (en) Formation method for minute pattern in semiconductor device
US6680163B2 (en) Method of forming opening in wafer layer
JP2007110069A (en) Method of forming contact hole
KR20090070686A (en) The method for manufacturing semiconductor device
JP6307851B2 (en) Stencil mask and manufacturing method thereof
CN116403889B (en) Patterning method and method for manufacturing semiconductor structure
JP2009295785A (en) Method of manufacturing semiconductor device
KR20090072681A (en) Method of forming semiconductor device
KR20030050172A (en) Method for forming a photo resist pattern of semiconductor device
KR101095060B1 (en) Method for Manufacturing Semiconductor Device
KR19990003882A (en) Fine Pattern Formation Method of Semiconductor Device
US20100055617A1 (en) Method of forming pattern in semiconductor device
KR101931799B1 (en) Vernier of semiconducor device and method of fabricating the same
JP2009283674A (en) Method of manufacturing semiconductor apparatus

Legal Events

Date Code Title Description
WITN Withdrawal due to no request for examination