KR20070120828A - Shift register and liquid crystal display using the same - Google Patents

Abstract

A shift register and a liquid crystal display device using the same are provided to suppress an abnormal output from an output buffer by turning off the output buffer, when the shift register is not activated. A shift register includes a controller(72), an output buffer(71) and a lock controller(73). The controller receives at least one driving voltage, charges/discharges a Q node in response to plural gate shift clocks, and charges a QB node. The output buffer generates a scan pulse in response to the voltages on the Q and QB nodes. The lock controller discharges at least one of the Q and QB nodes in response to a lock enable signal, which is generated during a disable period of the gate shift clocks. The controller receives a start pulse or output signals from previous and next stages.

Description

Shift Register and Liquid Crystal Display Using The Same}

1 is a view showing a conventional liquid crystal display device.

FIG. 2 is a diagram showing the configuration of the gate driving circuit shown in FIG. 1; FIG.

3 is a view showing a liquid crystal display device according to the present invention.

4 is a diagram showing the configuration of a gate driving circuit shown in FIG.

FIG. 5 is a diagram showing an example of the first stage circuit configuration shown in FIG. 4; FIG.

FIG. 6 is a drive waveform diagram of the circuit shown in FIG. 5; FIG.

7A and 7B show waveforms of a lock enable signal.

8A-8C illustrate embodiments of a portion A shown in FIG. 5.

<Brief description of symbols for the main parts of the drawings>

11, 51: data driving circuit 12: gate driving circuit

13, 53: liquid crystal display panel 54, 55: shift register

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a shift register and a liquid crystal display using the same, and more particularly, to a shift register capable of blocking an output buffer of a shift register not being driven and a liquid crystal display using the same.

Liquid crystal displays are widely used in display devices of office equipment, monitors of computers, and even large-screen televisions with the recent development of process and driving technologies. Such a liquid crystal display device displays an image by adjusting the light transmittance of the liquid crystal using an electric field. To this end, the liquid crystal display device includes a liquid crystal display panel in which liquid crystal cells are arranged in a matrix, and a driving circuit for driving the liquid crystal display panel.

Referring to FIG. 1, in the conventional LCD, m × n liquid crystal cells Clc are arranged in a matrix type, m data lines D1 to Dm and n gate lines G1 to Gn. Intersect with the liquid crystal display panel 13 to which the thin film transistor TFT is connected, and the data driver circuit 11 for supplying data to the data lines D1 to Dm of the liquid crystal display panel 13. And a gate driving circuit 12 supplying a scan pulse to the gate lines G1 to Gn.

The liquid crystal display panel 13 is formed by bonding a thin film transistor substrate on which a thin film transistor array is formed and a color filter substrate on which a color filter array is formed, with the liquid crystal layer interposed therebetween. The data lines D1 to Dm and the gate lines G1 to Gn formed on the thin film transistor substrate of the liquid crystal display panel 13 are perpendicular to each other. The thin film transistor TFT connected to the intersection of the data lines D1 to Dm and the gate lines G1 to Gn may connect the data lines D1 to Dn in response to a scan pulse of the gate lines G1 to Gn. The supplied data voltage is supplied to the pixel electrode of the liquid crystal cell Clc. A black matrix, a color filter, a common electrode, and the like are formed on the color filter substrate. Accordingly, in the liquid crystal cell Clc, the liquid crystal having dielectric anisotropy is rotated to adjust the light transmittance by a potential difference between the data voltage supplied to the pixel electrode and the common voltage supplied to the common electrode. On the thin film transistor substrate and the color filter substrate of the liquid crystal display panel 13, a polarizing plate having an optical axis orthogonal to each other is attached, and an alignment layer for determining the pretilt angle of the liquid crystal is further formed on the inner side of the liquid crystal layer. In addition, a storage capacitor Cst is further formed in each of the liquid crystal cells Clc. The storage capacitor Cst is formed between the pixel electrode and the front gate line, or is formed between the pixel electrode and a common line (not shown) to keep the data voltage charged in the liquid crystal cell Clc constant.

The data driving circuit 11 converts the input digital video data into an analog data voltage using a gamma voltage and supplies it to the data lines D1 to Dm.

The gate driving circuit 12 sequentially supplies scan pulses to the gate lines G1 to Gn to select a horizontal line of the liquid crystal cell Clc to which data is to be supplied.

Specifically, as shown in FIG. 2, the gate driving circuit 12 is first to first connected to the start pulse Vst input line in order to sequentially supply scan pulses to the gate lines G1 to Gn. a shift register having n stages and a dummy stage. The clock signals CLK are commonly supplied to the first to nth stages and the dummy stages shown in FIG. 2 together with the high potential and low potential driving voltages Vdd and Vss, and the start pulse Vst or the previous stage and the next stage. However, the output signal of the stage is supplied. The output signal of the first to n-th stages is reset due to the output signal of the next stage, and includes a dummy stage for resetting the n-th stage. The first stage outputs a scan pulse to the first gate line G1 in response to the start pulse Vst and the clock signal CLK. The second to nth stages sequentially output scan pulses to the second to nth gate lines G2 to Gn in response to the output signal and the clock signal CLK of the previous stage. In other words, the first to nth stages and the dummy stage have the same circuit configuration, and at least two clock signals having different phases are supplied to the clock signal CLK.

Each stage of the shift register includes an output buffer for supplying an output signal to an output terminal, including a pull-up transistor and a pull-down transistor, and a control unit for controlling the output buffer and including a Q node and a QB node.

The pull-up transistor is controlled by the Q node to supply the high or low voltage to the output terminal in response to the clock signal, and the pull-down transistor is controlled by the QB node to supply the low potential drive voltage (Vss) to the output terminal. do.

Such a shift register is divided into at least two parts and can be driven. In the case of driving by dividing the shift register into two, one of the two shift registers may be disposed on one side of the liquid crystal display panel 13 and the other may be disposed on the other side. At this time, the two shift registers are alternately driven with the same gate lines G1 to Gn. That is, when the first shift register supplies a signal to the gate lines G1 to Gn for a predetermined period, the second shift register is not driven. On the contrary, when the second shift register supplies a signal, the first shift register is not driven. Do not. The Q node and QB node of the shift register, which are not driven, of the two shift registers are floated to a low voltage state to block the output to the output terminal through the output buffer. However, since the output terminals of the two shift registers are connected to the same gate lines G1 to Gn, when the shift register being driven supplies a high voltage to the specific gate line, the specific terminal among the output terminals of the shift register not being driven is provided. The high voltage is supplied to the output terminal connected to the gate line. At this time, since the Q node and the QB node, to which the gate terminals of the pull-up and pull-down transistors are connected, respectively, remain in a floating state, they are likely to respond to the voltage change of the output terminal. Therefore, when a high voltage is supplied from the shift register being driven to the output terminal of the shift register that is not driven, the gate terminals of the pull-up and pull-down transistors, which should remain turned off, are turned on, so that the gate line The problem occurs that the high voltage of is discharged.

Accordingly, an object of the present invention is to provide a shift register capable of blocking an output buffer of a shift register not being driven and a liquid crystal display using the same.

In order to achieve the above object, a shift register according to the present invention includes a control unit configured to receive at least one driving voltage and charge / discharge a Q node and to charge / discharge a QB node in response to a plurality of gate shift clocks; An output buffer generating a scan pulse in response to the voltages of the Q node and the QB node; And a lock controller configured to discharge at least one of the Q node and the QB node in response to a lock enable signal generated during the disable period of the gate shift clocks.

The controller may further receive a start pulse or an output signal of a previous stage and an output signal of a next stage.

The lock enable signal outputs a high voltage for a predetermined period.

The lock enable signal alternately outputs a high voltage and a low voltage for a predetermined period.

The predetermined period is 10% to 100% of the disable period of the gate shift clocks.

The lock enable signal includes first and second lock enable signals.

The lock controller discharges the Q node in response to the first lock enable signal, and discharges the QB node in response to the second lock enable signal.

The driving voltage includes a high potential driving voltage and a low potential driving voltage.

The output buffer is controlled by the Q node and outputs any one of a high voltage and a low voltage according to the gate shift clock; And a pull-down transistor controlled by the QB node to output a low voltage.

The control unit may include a first transistor that is turned on by receiving a high voltage of the start pulse or a previous stage output signal and turns on the pull-up transistor by supplying a high voltage to the Q node; A fourth transistor receiving the high voltage of the gate shift clock and being turned on to supply the high potential driving voltage to the QB node; A third transistor that is turned on to receive the high voltage of the QB node to discharge the Q node; A third a transistor configured to receive the high voltage of the next stage output signal and to be turned on to discharge the Q node; A fifth transistor that is turned on to receive the high voltage of the start pulse or the previous stage output signal to discharge the QB node; And a fifth a transistor receiving the high voltage of the Q node and being turned on to discharge the QB node.

The lock controller may include: a first lock transistor configured to receive a high voltage of the lock enable signal and be turned on to discharge the Q node; And a second lock transistor supplied with the high voltage of the lock enable signal to be turned on to discharge the QB node.

A liquid crystal display device according to the present invention includes a liquid crystal display panel having an array area in which a plurality of gate lines and a plurality of data lines intersect and a plurality of liquid crystal cells are disposed; A control unit that charges / discharges Q nodes in response to a plurality of gate shift clocks and receives / discharges QB nodes, and generates scan pulses in response to voltages of the Q nodes and the QB nodes. An output buffer, and a lock controller configured to discharge at least one of the Q node and the QB node in response to a lock enable signal generated during the disable period of the gate shift clocks; A gate driving circuit which sequentially supplies scan pulses to the gate lines, including at least one shift register disposed at one side; And a data driver circuit for supplying data to the data lines.

The gate driving circuit may include a first shift register on one side of the liquid crystal display panel; And a second shift register disposed on the other side of the liquid crystal display panel.

One end of the gate line is connected to the first shift register, and the other end of the gate line is connected to the second shift register.

Other objects and advantages of the present invention in addition to the above object will be apparent from the description of the preferred embodiment of the present invention with reference to the accompanying drawings.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to FIGS. 3 to 8C.

3 is a schematic view of a liquid crystal display according to an exemplary embodiment of the present invention.

Referring to FIG. 3, a liquid crystal display according to an exemplary embodiment of the present invention includes a data driving circuit 51 for supplying data to the liquid crystal display panel 53 and the data lines D1 to Dm of the liquid crystal display panel 53. And a gate driving circuit for supplying a scan pulse to the gate lines G1 to Gn.

The liquid crystal display panel 53 is formed by arranging liquid crystal cells Clc in an active matrix form between an upper glass substrate and a lower glass substrate. On the lower glass substrate, a plurality of data lines D1 to Dm and a plurality of gate lines G1 to Gn are arranged to cross each other, and thin film transistors (TFTs) are formed at each crossing portion thereof. The TFT supplies data from the data lines D1 to Dm to the liquid crystal cell Clc in response to the scan pulses from the gate lines G1 to Gn. For this purpose, the gate electrodes of the TFTs are connected to the gate lines G1 to Gn, and the source electrodes are connected to the data lines D1 to Dm. The drain electrode of the TFT is connected to the pixel electrode Vpxl of the liquid crystal cell Clc. In addition, a storage capacitor Cst is formed on the lower glass substrate of the liquid crystal display panel 53 to maintain the voltage of the liquid crystal cell Clc. The storage capacitor Cst may be formed between the liquid crystal cell Clc and the front gate lines G1 to Gn, or may be formed between the liquid crystal cell Clc and a separate common line. A color filter, a common electrode Vcom, a black matrix, and the like are formed on the upper glass substrate of the liquid crystal display panel 53. In each of the upper and lower glass substrates, a polarizing plate for filtering linearly polarized light and an alignment layer for setting the pretilt angle of the liquid crystal molecules are formed. The liquid crystal molecules of the liquid crystal cell Clc are driven according to an electric field between the common electrode Vcom of the upper glass substrate and the pixel electrode Vpxl of the lower glass substrate to modulate the light incident from the backlight unit through the polarizer.

The data driving circuit 51 converts the input digital video data into an analog data voltage using a gamma voltage and supplies it to the data lines D1 to Dm.

The gate driving circuit includes first and second shift registers 54 and 55 disposed at one side and the other side of the liquid crystal display panel 53 to sequentially supply scan pulses to the gate lines G1 to Gn. The horizontal line of the liquid crystal cell Clc to which data from the driving circuit 51 is supplied is selected. In this case, the first and second shift registers 54 and 55 supply scan pulses to the same gate lines G1 to Gn, respectively, and alternately drive the predetermined periods.

Specifically, the first and second shift registers 54 and 55 have the same configuration, and as shown in FIG. 4, the start pulse Vst to sequentially supply scan pulses to the gate lines G1 to Gn. The first to nth stages S1 to Sn are connected to the input line. Each of these stages S1 to Sn is connected to an output terminal, and outputs an output buffer 71 for supplying an output signal, a controller 72 for controlling the output buffer 71, and a turn-on of the output buffer 71. It is comprised by the lock control part 73 for controlling an off state. The output buffer 71 is a pull-up transistor for outputting one of the clock signals CLK1 and CLK2 to an output terminal under the control of the Q node of the control unit 72, and a low potential drive under the control of the QB node of the control unit 72. And a pull-down transistor for outputting a voltage Vss to an output terminal. In addition, the control unit 72 receives the output signal of the next stage stage as a reset signal to reset the stage output signal, the S terminal receiving the start pulse (Vst) or the output signal of the previous stage stage to start driving the stage. A Q node connected to the R terminal, the gate terminal of the pull-up transistor to control the pull-up transistor, and a QB node connected to the gate terminal of the pull-down transistor to control the pull-down transistor. Finally, the lock controller 73 receives the first and second lock enable signals LE1 and LE2 from the signal generator 75 and discharges the Q and QB nodes. Lock transistors LT1 and LT2.

As such, the clock signal CLK is commonly supplied to the first to nth stages S1 to Sn illustrated in FIG. 4 together with the high potential driving voltage Vdd and the low potential driving voltage Vss, and a start pulse. (Vst) or the output signal of the previous stage and the output signal of the next stage are supplied. In response to these signals, the first to nth stages S1 to Sn sequentially generate scan pulses and supply the scan pulses to the respective gate lines, and the output signals of the first to nth-1 stages are output signals of the next stage. Due to the reset, and not shown in the figure, a dummy stage is further provided for resetting the n-th stage. The first to nth stages and the dummy stage have the same circuit configuration, and at least two clock signals having different phases are supplied to the clock signal.

The lock control unit 73 is not driven when the shift register is normally driven, but is driven when the shift register is not driven. That is, while the first shift register 54 shown in FIG. 3 is being driven, the lock enable signals LE1 and LE2 are generated from the signal generator 75 of the second shift register 54 to lock the 73. Is driven to maintain the turn-off state of the second shift register 54 output buffer 71 and from the signal generator 75 of the first shift register 53 while the second shift register 55 is being driven. The lock enable signals LE and LE2 are generated to drive the lock control unit 73 to maintain the turn-off state of the first shift register 53 output buffer 71. This solves the conventional problem of discharging the high voltage of the gate line by abnormally turning on the output buffers of the non-driving shift register.

In the shift register illustrated in FIG. 4, the first lock transistor LT1 discharging the Q node of each stage and the second lock transistor LT2 discharging the QB node of each stage are respectively the first and second lock enable signals. Although LE1 and LE2 are separately supplied, the first and second lock enable signals LE1 and LE2 may be supplied as the same signal to the first and second lock transistors LT1 and LT2 through the same wiring. In addition, the first and second lock enable signals LE1 and LE2 may be supplied through independent wirings for respective stages. In this case as well, the signal wires of the first and second lock enable signals LE1 and LE2 can be used as the same wires and can be used as different wires.

5 is a diagram illustrating an embodiment of a first stage circuit configuration used in the shift register of the present invention.

Referring to FIG. 5, the first stage has a low potential under the control of the pull-up transistor T6 and the QB node which output the first clock signal CLK1 to the first gate line G1 under the control of the Q node. An output buffer 71 composed of a pull-down transistor T7 for outputting a driving voltage Vss to the first gate line G1, and first to fifth a transistors T1 to T5a for controlling the Q node and the QB node. Lock control unit 73 composed of a control unit 72 composed of the first and second lock transistors LT1 and LT2 for controlling the turn-off of the pull-up transistor T6 and the pull-down transistor T7. It is provided. The lock controller 73 shown in FIG. 5 shows an example in which the first and second lock transistors LT1 and LT2 are supplied with the lock enable signal LE from the signal generator 75 through the same wiring.

The first stage is supplied with a high potential driving voltage Vdd, a low potential driving voltage Vss, and a start pulse Vst, and the first and second clock signals CLK1 having different phases as shown in FIG. 6. , CLK2) is supplied. Hereinafter, an operation process of the first stage shown in FIG. 5 will be described in detail with reference to the driving waveform shown in FIG. 6, and it will not operate when the shift register including the first stage shown in FIG. 5 operates. Explain when not to do each.

First, when the shift register including the first stage is operated, the supply of the lock enable signal LE is cut off from the signal generator 75 or the lock enable signal LE having a low voltage is generated and supplied. And the second lock transistors LT1 and LT2 are turned off to drive only the output buffer 71 and the controller 72.

5 and 6, in the period A, the first transistor T1 is turned on by the high voltage of the start pulse Vst so that the high voltage is pre-charged to the Q node. The pull-up transistor T6 is turned on by the high voltage pre-charged to the Q node, and the low voltage of the first clock signal CLK1 is supplied to the first gate line G1 as the output signal Vg_out1. . At this time, the QB node is in a low voltage state by the fifth transistor T5 turned on according to the high voltage of the start pulse Vst and the fifth a transistor T5a turned on according to the high voltage of the Q node. And the pull-down transistors T3 and T7 are turned off.

Since the first transistor T1 is turned off by the low voltage of the start pulse Vst in the period B, the Q node is floated to a high voltage state, and the pull-up transistor T6 remains turned on. At this time, due to the high voltage of the first clock signal CLK1, the Q node is bootstrapping under the influence of parasitic capacitance formed by overlapping the gate electrode and the drain electrode of the pull-up transistor T6, and thus more than the A period. Charged to high voltage Accordingly, the pull-up transistor T6 is reliably turned on so that the high voltage of the first clock signal CLK1 is rapidly supplied to the first gate line G1 as the output signal Vg_out1. Meanwhile, the QB node discharged through the 5a transistor T5a turned on by the Q node maintains a low voltage state.

In the C period, the third transistor T3a is turned on by the high voltage of the next second stage gate output signal Vg_out2, and the fourth transistor T4 is turned on by the high voltage of the second clock signal CLK2. The high potential driving voltage Vdd is supplied to the QB node to turn into a high voltage state and turn on the third and pull-down transistors T3 and T7. The Q node is quickly discharged by the turned-on third and third a transistors, and a low voltage is supplied to the first gate line G1 as the output signal Vg_out1 by the turned-on pull-down transistor T7.

In the D period, the QB node floated to the high voltage state in the C period maintains the floating state to turn on the third and pull-down transistors T3 and T7. As a result, the Q node is discharged to maintain the low voltage state, and the low voltage is supplied to the first gate line G1 as the output signal Vg_out1, and the low voltage output signal Vg_out1 is low during the frame period. Will be maintained.

At this time, since the first and second shift registers 54 and 55 shown in FIG. 3 are driven alternately for one frame or a predetermined period of time, a signal supplied to the shift register is blocked when the shift register is not driven. The Q and QB nodes are then floated to a low voltage state. Therefore, the pull-up transistor T6 and the pull-down transistor T7 having gate terminals connected to the Q node and the QB node, respectively, are turned off and do not output a signal to the gate line until the shift register is driven. .

In this way, when the shift register stops driving and the pull-up transistor T6 and the pull-down transistor T7 are turned off, the signal generation unit 75 generates the lock enable signal LE. As the high voltage is supplied through the enable signal LE, the lock controller 73 starts driving.

The lock enable signal LE has a waveform that maintains a high voltage state for a predetermined period as shown in FIG. 7A, or a pulse that repeats the high voltage state and the low voltage state for a predetermined period as shown in FIG. 7B. It may have a form. The lock enable signal LE shown in FIGS. 7A and 7B indicates when an operation period of two shift registers is one frame, and the high voltage holding periods H1 and H2 of the lock enable signal LE are one. Possible within about 10% to 100% of the frame period. 7A and 7B, the operation period is illustrated as one frame. However, even when the operation period is more than one frame, the lock enable signal LE may maintain a high voltage for a period of about 10% to 100% of the period.

In the first lock transistor LT1 of the lock control unit 73 shown in FIG. 5, a gate terminal is connected to a lock enable signal LE line, and source and drain terminals are connected to a Q node and a low potential driving voltage Vss. Each is connected. In addition, a gate terminal is connected to the lock enable signal LE line of the second lock transistor LT2, and a source and a drain terminal are respectively connected to the QB node and the low potential driving voltage Vss. Therefore, when the high voltage of the lock enable signal LE is supplied, the first and second lock transistors LT1 and LT2 are turned on, thereby maintaining the discharge state of the Q node and the QB node. In FIG. 4 and FIG. 5, there is only one lock transistor connected to the Q node and the QB node, but the number and circuit configuration of the lock transistor may be any structure capable of discharging the Q node and the QB node through the lock enable signal.

As described above, the shift register and the liquid crystal display using the shift register according to the embodiment of the present invention turn off the pull-up and pull-down transistors of the unused shift register when two shift registers are alternately used. The conventional problem that the pull-up and pull-down transistors of the shift resistors that are not used by the high voltage of the output terminal are turned on can be solved. In addition, the shift register according to the embodiment of the present invention may add lock transistors, which are turned on by the lock enable signal and turn off the pull-up and pull-down transistors, even if the shift register has any circuit configuration. It is applicable by doing so.

8A to 8C are diagrams illustrating various embodiments of a terminal receiving a driving start signal in the portion A illustrated in FIG. 5, that is, the first stage. Referring to this, referring to the driving waveform of FIG. 6, the first transistor T1 shown in FIG. 8A is turned on in the period A when the start pulse Vst has a high voltage and thus, Supply a high voltage to the Q node. The first transistor T1 shown in FIG. 8B is turned on in the period A when the start pulse Vst has a high voltage, and the first transistor T1a is high in the period A like the start pulse Vst. It is turned on by the fourth clock signal CLK4 having the high voltage of the start pulse Vst to the Q node. The first transistor T1 shown in FIG. 8C is turned on in the period A when the start pulse Vst has a high voltage, and the first transistor T1b applies the high voltage in the period A like the start pulse Vst. The branch is turned on by the fourth clock signal CLK4. At this time, the high voltage of the high potential driving voltage Vdd is supplied to the Q node by the first and first a transistors T1 and T1a.

8A to 8C are described with reference to the first stage with reference to the waveform diagram of FIG. 6, but when applied to a stage other than the first stage, the output signal of the previous stage is supplied instead of the start pulse Vst. Instead of the fourth clock signal CLK4, a clock signal having the same high voltage timing as the output signal of the previous stage may be supplied.

As each stage of the shift register according to the present invention can be applied through various circuit configurations, the portion A shown in FIG. 5 may also apply various circuit configurations in addition to the embodiments shown in FIGS. 8A to 8C.

As described above, the shift register and the liquid crystal display using the same basically include an output buffer for supplying an output signal to the output terminal and a control unit for controlling the output buffer, and the output buffer when the shift register is not driven. It further comprises a lock control unit for controlling the turn-off of. Accordingly, the shift register and the liquid crystal display using the same may block abnormal output of the output buffer when the shift register is not driven.

Those skilled in the art will appreciate that various changes and modifications can be made without departing from the technical spirit of the present invention. Therefore, the technical scope of the present invention should not be limited to the contents described in the detailed description of the specification but should be defined by the claims.

Claims (24)

A controller configured to receive at least one driving voltage and charge / discharge the Q node and to charge / discharge the QB node in response to the plurality of gate shift clocks; An output buffer generating a scan pulse in response to the voltages of the Q node and the QB node; And And a lock controller configured to discharge at least one of the Q node and the QB node in response to a lock enable signal generated during the disable period of the gate shift clocks. According to claim 1, The control unit, A shift register, characterized by further receiving a start pulse or an output signal of the previous stage and an output signal of the next stage. According to claim 1, And the lock enable signal outputs a high voltage for a predetermined period of time. According to claim 1, And the lock enable signal alternately outputs a high voltage and a low voltage for a predetermined period of time. The method according to claim 3 or 4, And the predetermined period is 10% to 100% of the disable period of the gate shift clocks. According to claim 1, And the lock enable signal includes first and second lock enable signals. The method of claim 6, The lock control unit, Discharge the Q node in response to the first lock enable signal, And discharging the QB node in response to the second lock enable signal. The method of claim 2, And the driving voltage comprises a high potential driving voltage and a low potential driving voltage. The method of claim 8, The output buffer, A pull-up transistor controlled by the Q node and outputting any one of a high voltage and a low voltage according to the gate shift clock; And And a pull-down transistor controlled by the QB node to output a low voltage. The method of claim 9, The control unit, A first transistor supplied with the high voltage of the start pulse or the previous stage output signal and turned on to supply the high voltage to the Q node to turn on the pull-up transistor; A fourth transistor receiving the high voltage of the gate shift clock and being turned on to supply the high potential driving voltage to the QB node; A third transistor that is turned on to receive the high voltage of the QB node to discharge the Q node; A third a transistor configured to receive the high voltage of the next stage output signal and to be turned on to discharge the Q node; A fifth transistor that is turned on to receive the high voltage of the start pulse or the previous stage output signal to discharge the QB node; And And a fifth a transistor configured to receive the high voltage of the Q node and to be turned on to discharge the QB node. The method of claim 10, The lock control unit, A first lock transistor supplied with a high voltage of the lock enable signal to be turned on to discharge the Q node; And And a second lock transistor configured to receive a high voltage of the lock enable signal and to be turned on to discharge the QB node. A liquid crystal display panel having an array region in which a plurality of gate lines and a plurality of data lines intersect and a plurality of liquid crystal cells are disposed; A control unit that charges / discharges Q nodes in response to a plurality of gate shift clocks and receives / discharges QB nodes, and generates scan pulses in response to voltages of the Q nodes and the QB nodes. An output buffer, and a lock controller configured to discharge at least one of the Q node and the QB node in response to a lock enable signal generated during the disable period of the gate shift clocks, and at least one side of the liquid crystal display panel. A gate driver circuit sequentially supplying scan pulses to the gate lines, the gate driver including at least one shift register disposed in the gate lines; And And a data driving circuit for supplying data to the data lines. The method of claim 12, The control unit, And a start pulse or an output signal of a previous stage and an output signal of a next stage. The method of claim 12, And the lock enable signal outputs a high voltage for a predetermined period of time. The method of claim 12, And the lock enable signal alternately outputs a high voltage and a low voltage for a predetermined period of time. The method according to claim 14 or 15, And the predetermined period is 10% to 100% of the disable period of the gate shift clocks. The method of claim 12, And the lock enable signal includes first and second lock enable signals. The method of claim 17, The lock control unit, Discharge the Q node in response to the first lock enable signal, And discharging the QB node in response to the second lock enable signal. The method of claim 13, The driving voltage includes a high potential driving voltage and a low potential driving voltage. The method of claim 19, The output buffer, A pull-up transistor controlled by the Q node and outputting any one of a high voltage and a low voltage according to the gate shift clock; And And a pull-down transistor controlled by the QB node to output a low voltage. The method of claim 20, The control unit, A first transistor supplied with the high voltage of the start pulse or the previous stage output signal and turned on to supply the high voltage to the Q node to turn on the pull-up transistor; A fourth transistor receiving the high voltage of the gate shift clock and being turned on to supply the high potential driving voltage to the QB node; A third transistor that is turned on to receive the high voltage of the QB node to discharge the Q node; A third a transistor configured to receive the high voltage of the next stage output signal and to be turned on to discharge the Q node; A fifth transistor that is turned on to receive the high voltage of the start pulse or the previous stage output signal to discharge the QB node; And And a fifth a transistor configured to receive the high voltage of the Q node and to be turned on to discharge the QB node. The method of claim 21, The lock control unit, A first lock transistor supplied with a high voltage of the lock enable signal to be turned on to discharge the Q node; And And a second lock transistor configured to receive the high voltage of the lock enable signal and to be turned on to discharge the QB node. The method of claim 12, The gate driving circuit, A first shift register on one side of the liquid crystal display panel; And And a second shift register on the other side of the liquid crystal display panel. The method of claim 23, wherein One end of the gate line is connected to the first shift register, And the other end of the gate line is connected to the second shift register.

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