KR20070118430A - Array substrate for liquid crystall display device and methode for fabricating the same - Google Patents

Abstract

An array substrate for an LCD(Liquid Crystal Display) and a method for fabricating the same are provided to enable the size of the LCD to be enlarged as signal delay by signal wiring is not generated even if the size of a display device is enlarged. A method for fabricating an array substrate for an LCD comprises the following steps of: depositing and patterning first metal substance(124) on a substrate(101) with a defined pixel area to form gate wiring extended in a direction and a gate electrode(105) in the pixel area; forming a gate insulating layer(109) in the upper part of the gate wiring and the gate electrode; forming a semiconductor pattern in correspondence with the gate electrode over the gate insulating layer; forming a sulfur substance layer(128) on the semiconductor pattern by performing first plasma processing of the substrate with the semiconductor pattern in an H2S(Hydrogen Sulfide) atmosphere; forming data wiring(130) of defining the pixel area while crossing the gate wiring and source/drain electrodes(135,137) being spaced to each other in the upper part of the sulfur substance layer in the pixel area by depositing and patterning copper alloy in the upper part of the sulfur substance layer; forming a protection layer with a drain contact hole exposing part of the drain electrode over the source/drain electrodes; and forming a pixel electrode which contacts the drain electrode through the drain contact hole over the protection layer.

Description

Array substrate for liquid crystal display device and method for manufacturing the same {Array substrate for Liquid Crystall Display Device and methode for fabricating the same}

1 is an exploded perspective view schematically showing a general liquid crystal display device.

2A to 2I illustrate cross-sectional views of manufacturing steps according to a four-mask process of an array substrate for a liquid crystal display device using a Cu-Mg alloy according to a first embodiment of the present invention. Cross-sectional view of one pixel region comprising a.

3 is a plan view schematically showing a part of an array substrate for a liquid crystal display device;

4A to 4G are cross-sectional views taken along the line IV-IV of FIG. 3 and shown in the process sequence of the present invention.

<Explanation of symbols for main parts of drawing>

101 substrate 105 gate electrode

107, 143: magnesium oxide film 109: gate insulating film

120: semiconductor layer 122: active layer

124: ohmic contact layer 125a, 125b: pure and impurity amorphous pattern

128: sulfide layer (copper sulfide layer) 130: data wiring

135 source electrode 137 drain electrode

150: protective layer 155: drain contact hole

160: pixel electrode

P: pixel area TrA: switching area

The present invention relates to an array substrate for a liquid crystal display device including a copper wiring and a manufacturing method thereof.

Recently, liquid crystal displays have been spotlighted as next generation advanced display devices having low power consumption, good portability, high technology value, and high added value.

Among the liquid crystal display devices, an active matrix liquid crystal display device having a thin film transistor, which is a switching element that can control voltage on and off for each pixel, has the best resolution and video performance. I am getting it.

In general, a liquid crystal display device forms an array substrate and a color filter substrate through an array substrate manufacturing process for forming a thin film transistor and a pixel electrode and a color filter substrate manufacturing process for forming a color filter and a common electrode, and between the two substrates. It completes through the liquid crystal cell process through liquid crystal in the process.

1 is an exploded perspective view schematically illustrating a configuration of a general liquid crystal display device.

As shown in the figure, the array substrate 10 and the color filter substrate 20 are faced to each other with the liquid crystal layer 30 interposed therebetween, wherein the lower array substrate 10 crosses each other. A plurality of gate wirings 14 and data wirings 16 are arranged to define a plurality of pixel regions P. Thin film transistors T, which are switching elements, are formed at the intersections of the two wirings 14 and 16. And a one-to-one correspondence with the pixel electrodes 18 provided in the pixel regions P.

In addition, the upper color filter substrate 20 facing the array substrate may cover a non-display area such as the gate line 14, the data line 16, and the thin film transistor T on the rear surface of the transparent substrate 22. Grid-like black matrix 25 is formed so as to border each pixel region P, and the red, green, and blue color filter layers 26 are sequentially arranged to correspond to each pixel region P in the grid. ) Is formed, and a transparent common electrode 28 is provided over the entirety of the black matrix 25 and the red, green, and blue color filter layers 26.

Although not shown in the drawings, these two substrates 10 and 20 are sealed with a sealant or the like along the edges to prevent leakage of the liquid crystal layer 30 interposed therebetween. In the boundary portion of each substrate (10, 20) and the liquid crystal layer 30 is interposed upper and lower alignment layer that provides reliability in the molecular alignment direction of the liquid crystal, and at least one outer surface of each substrate (10, 20) A polarizing plate is provided.

In addition, a back-light is provided on the outer surface of the array substrate to supply light. The on / off signals of the thin film transistor T are sequentially scanned by the gate wiring 14. When the image signal of the data wiring 16 is transmitted to the pixel electrode 18 of the pixel region P applied and selected, the liquid crystal molecules are driven by the vertical electric field therebetween, and thus the light transmittance is changed. Branch images can be displayed.

In the array substrate for a liquid crystal display device having the above-described configuration, the data line is made of a conductive metal such as chromium (Cr), molybdenum (Mo), or tantalum (Ta), and these metals have thermal stability. Excellent stability has the advantage that a defect such as hillock does not occur.

These metals are generally deposited on a substrate by sputtering, and the photo wiring is formed by applying, exposing, developing, and etching the photoresist to form the data line.

However, the metals have advantages such as thermal stability as described above, but as the liquid crystal display devices become larger and larger, the high specific resistance of these metals causes a signal delay.

Therefore, a metal material having a low specific resistance and not forming a hillock is essential for manufacturing an array substrate for a liquid crystal display device.

At present, copper (Cu) or aluminum (Al) is recognized as the most suitable wiring material due to the lowest resistivity, but in the case of aluminum (Al), it is a problem that the heel lock occurs, and the proposed aluminum to solve this problem. Alloys have a problem of high resistivity.

Therefore, in recent years, many studies have been conducted to form gates or data lines using copper. However, since copper has poor adhesion characteristics with other material layers, there is a possibility that defects may be separated from the substrate during etching. have.

In order to solve the above problems, the present invention provides an array substrate for a liquid crystal display device and a method of manufacturing the same, characterized in that the contact characteristics are improved by forming a data line, a source and a drain electrode using a copper alloy instead of a single copper material. It is for that purpose.

According to a first aspect of the present invention, there is provided a method of fabricating an array substrate for a liquid crystal display device, including: a gate wiring extending in one direction by depositing and patterning a first metal material on a substrate on which a pixel region is defined; Forming a gate electrode in the pixel region; Forming a gate insulating film on the gate wiring and the gate electrode; Forming a semiconductor pattern on the gate insulating layer corresponding to the gate electrode; Forming a sulfur material layer over the semiconductor pattern by first plasma treating the substrate on which the semiconductor pattern is formed in a hydrogen sulfide (H 2 S) atmosphere; Depositing and patterning a copper alloy on the sulfur material layer to form a data line crossing the gate line to define the pixel area, and forming source and drain electrodes spaced apart from each other on the sulfur material layer in the pixel area. Wow; Forming a protective layer having a drain contact hole exposing a portion of the drain electrode over the source and drain electrodes; Forming a pixel electrode contacting the drain electrode through the drain contact hole on the passivation layer.

The semiconductor pattern may include an active layer of pure amorphous silicon and an impurity amorphous silicon pattern. The semiconductor pattern may expose the active layer and be spaced apart from each other by removing the impurity amorphous silicon pattern between the source and drain electrodes spaced apart from each other. Forming a layer further.

In addition, a conductive copper sulfide (CuS) film is further formed between the sulfur material layer and the source and drain electrodes formed in contact with the sulfur material layer.

In another method of manufacturing an array substrate for a liquid crystal display device according to the second aspect of the present invention, a gate wiring extending in one direction by depositing and patterning a first metal material on a substrate in which a pixel region is defined and a gate electrode in the pixel region are provided. Forming; Forming a gate insulating film on the gate wiring and the gate electrode; Forming a layer of pure amorphous silicon and an impurity amorphous silicon over the gate insulating film; First plasma treating the substrate on which the impurity amorphous silicon layer is formed in a hydrogen sulfide (H ₂ S) atmosphere; Depositing a copper alloy on a plasma-treated impurity amorphous silicon layer in the hydrogen sulfide (H ₂ S) atmosphere to form a metal layer; By patterning the metal layer, the impurity amorphous silicon layer, and the pure amorphous silicon layer, source and drain electrodes spaced apart from each other from the uppermost layer corresponding to the gate electrode, an ohmic contact layer of impurity amorphous silicon, and a pure amorphous portion of which is partially exposed thereunder. Forming an active layer of silicon, and defining a pixel area on the gate insulating layer to define the pixel area, and forming a data line connected to the source electrode; Forming a protective layer having a drain contact hole exposing a portion of the drain electrode over the data line and a source and drain electrode; Forming a pixel electrode contacting the drain electrode through the drain contact hole on the passivation layer.

At this time, the copper sulfide (CuS) film is further formed between the metal layer and the impurity amorphous silicon layer.

In the liquid crystal display device according to the first and second features, the first metal material is preferably a copper magnesium alloy, and the copper alloy is preferably a copper magnesium alloy. .

In addition, a magnesium oxide (MgO) film is further formed on the gate wiring and the gate electrode, and after forming a protective layer having the drain contact hole, performing a second plasma treatment in a hydrogen sulfide (H ₂ S) atmosphere. Further, in this case, a copper sulfide (CuS) film is further formed between the drain electrode and the pixel electrode in the drain contact hole.

An array substrate for a liquid crystal display according to the present invention includes a gate wiring extending in one direction on a substrate on which a pixel region is defined, and a gate electrode branched from the gate wiring to the pixel region; A gate insulating film formed over the gate wiring and the gate electrode; A semiconductor layer formed on the gate insulating layer to correspond to the gate electrode; A copper sulfide (CuS) film formed on the semiconductor layer and spaced apart from each other; A source and drain electrode formed to be spaced apart from each other by a copper alloy on the copper sulfide (CuS) layer and the same material as the source and drain electrode, and formed to define the pixel region by crossing the gate wiring on the gate insulating layer. Data wiring; A protective layer formed on the data line and on the source and drain electrodes and having a drain contact hole exposing the drain electrode; And a pixel electrode formed on the passivation layer and in contact with the drain electrode through the drain contact hole.

At this time, the copper alloy is characterized in that the copper magnesium alloy (Cu-Mg alloy).

The semiconductor layer may include an active layer of amorphous silicon and an ohmic contact layer of impurity amorphous silicon spaced apart from each other in correspondence with the gate electrode in a state in which the semiconductor layer is connected to the gate electrode. The (CuS) film is formed on the ohmic contact layer spaced apart from each other.

In addition, a magnesium oxide (MgO) film is further formed between the data line, the source and drain electrodes, and the protective layer.

In addition, a copper sulfide (CuS) film may be further formed between the pixel electrode and the drain electrode in the drain contact hole, and the gate wiring and the gate electrode may be made of a copper magnesium alloy. And a magnesium oxide (MgO) film is further formed between the gate insulating film and the gate insulating film.

Hereinafter, exemplary embodiments of the present invention will be described with reference to the accompanying drawings.

<First Embodiment>

2A to 2I illustrate cross-sectional views of manufacturing steps according to a four-mask process of an array substrate for a liquid crystal display device using a Cu-Mg alloy according to a first embodiment of the present invention. A cross-sectional view of one pixel area including a. In this case, an area in which the thin film transistor is formed is defined as a switching area.

First, as shown in FIG. 2A, a copper-magnesium alloy (Cu-Mg alloy) in which copper and magnesium are properly mixed as a metal material having low resistance and excellent contact characteristics is deposited on a transparent insulating substrate 101. Forming a first metal layer (not shown), applying a photoresist over the first metal layer (not shown), and performing exposure and development using a mask to form a photoresist pattern (not shown) of a predetermined type; A gate wiring (not shown) extending in one direction by etching a first metal layer (not shown) made of a copper magnesium alloy (Cu-Mg alloy) exposed to the outside of the photoresist pattern (not shown) thus formed, and the gate wiring A gate electrode 105 having a branching shape to each pixel region P is formed in (not shown).

Next, as shown in FIG. 2B, an insulating material such as silicon oxide (SiO ₂ ) or silicon nitride (SiNx) is deposited on the gate wiring (not shown) and the gate electrode 105 to form a gate insulating layer 109. Form.

At this time, the surface of the gate wiring (not shown) and the gate electrode 105 disposed below the gate insulating layer 109 includes magnesium (Mg), which is a very reactive material among the metal materials forming the bar. ) Reacts with oxygen to form a magnesium oxide (MgO) film 107 along the interface between the gate wiring (not shown) and the gate electrode 105 and the substrate 101.

Therefore, the magnesium oxide (MgO) film 107 and the gate insulating film 109 are substantially formed on the gate electrode 105 and the gate wiring (not shown). Thus, the gate below the gate insulating film 109 is formed. The magnesium oxide (MgO) film 107 formed at the interface between the wiring (not shown) and the gate electrode 105 is formed even though its thickness is about tens of nanometers to several angstroms. In addition to the gate insulating film 109, the insulating properties are improved.

 Next, as shown in FIG. 2C, a pure amorphous silicon layer 115 and an impurity amorphous silicon layer 116 are formed over the gate insulating layer 109.

Subsequently, the substrate 101 on which the pure and impurity amorphous silicon layers 115 and 116 are formed is plasma treated in a hydrogen sulfide (H ₂ S) atmosphere.

Due to the characteristics of the present invention, a copper magnesium alloy (Cu-Mg alloy), which is a metal material used to form a gate or data wiring, includes magnesium (Mg) therein, and the magnesium (Mg) is highly reactive and thus the copper magnesium When a copper magnesium layer is formed by depositing an alloy (Cu-Mg alloy), a magnesium oxide (MgO) film is also formed at the interface of the lower layer including the surface of the copper magnesium layer, and the magnesium oxide is formed below the magnesium oxide layer. In order to suppress the formation of a (MgO) film, plasma treatment is performed in the hydrogen sulfide (H ₂ S) atmosphere.

When a gate wiring (not shown) is formed of the Cu-Mg alloy, the magnesium oxide (MgO) film is not a problem because it further improves the insulating properties of the gate insulating film 109 formed thereon. In the subsequent process, when the data line and the source and drain electrodes are formed of a Cu-Mg alloy, a semiconductor layer is formed on the ohmic contact layer made of amorphous silicon doped more precisely with impurities. In this case, the contact resistance is lowered to increase the contact resistance, thereby inhibiting the role of the ohmic contact layer.

Therefore, in the present invention, hydrogen sulfide (H ₂ S) atmosphere is applied to the surface of the impurity amorphous silicon layer 116 to improve contact characteristics by suppressing the formation of a magnesium oxide (MgO) film at an interface with a source and drain electrode to be formed later. Plasma treatment.

In the case of performing a plasma treatment on the impurity amorphous silicon layer 116 in the hydrogen sulfide (H ₂ S) atmosphere, sulfur having a thickness of about several tens of nanometers to several angstroms (strong) on the surface of the impurity amorphous silicon layer 116 The material layer 127 is formed, and the reactivity of sulfur with other materials is shown in Table 1 below (Table 1 shows the reactivity between sulfur and other materials (enthalpy). The lower the enthalpy value, the better the reaction occurs). For reference, copper (Cu)> silicon (Si)> magnesium (Mg) in order that the relative reactivity of sulfur (Mg) with magnesium (Mg) is lower than that of copper (Cu) or silicon (Si).

TABLE 1

Magnesium (Mg) Silicon (Si) Copper (Cu) Sulfur (S) 83 25 12-20

ΔH _f (enthalpy) at 293 ° C

Therefore, when a copper magnesium alloy (Cu-Mg alloy) is deposited on the impurity amorphous silicon layer 116 subjected to plasma treatment in the hydrogen sulfide (H ₂ S) atmosphere, a magnesium oxide (MgO) film is not formed at the interface thereof. The sulfur material layer 127 is reacted with copper (Cu) by the sulfur material layer 127 to form a copper sulfide (CuS) film. At this time, the resulting copper sulfide (CuS) film has a conductive property, unlike the magnesium oxide (MgO) film having the insulating properties, the copper magnesium alloy (Cu-Mg alloy) with the ohmic contact layer made of the impurity amorphous silicon Improves the ohmic characteristics of the source and drain electrodes.

Next, as shown in FIG. 2D, the second metal layer 129 is formed by depositing a Cu-Mg alloy on the plasma-treated impurity amorphous silicon layer 116 in an atmosphere of hydrogen sulfide (H ₂ S). do. At this time, a second magnesium oxide (MgO) film 143 is naturally formed on the surface of the second metal layer 129 by magnesium (Mg), but the second metal layer 129 and the lower portion thereof At the interface between the impurity amorphous silicon layer 116, a sulfide layer 128 such as copper sulfide (CuS) is formed instead of the magnesium oxide (MgO) film, thereby suppressing the formation of the magnesium oxide (MgO) film.

In addition, in this case, the Cu-Mg alloy also has excellent adhesion to other material layers, and thus, when the metal layer is formed of a single copper material, the problem of being separated from the substrate is also solved.

Next, a second photoresist layer 191 is formed by applying photoresist onto the second metal layer 129, and is formed as a blocking region BA, a transmissive region TA, and a semi-transmissive region HTA having a slit structure. The exposure mask 195 is positioned on the second photoresist layer 191.

In this case, the exposure position of the exposure mask 195 will be described in more detail. The exposure mask 195 allows the blocking area BA to correspond to the area where the source and drain electrodes are to be formed, including the data line. A semi-transmissive region HTA having a slit structure corresponds to a portion of the switching region TrA corresponding to the gate electrode 109, and a transmissive region may correspond to a portion where the data line and the source and drain electrodes are not formed. TA).

Next, as shown in FIG. 2E, as described above, the second photoresist layer 191 is exposed through the exposure mask 195 of FIG. 2D positioned corresponding to the second photoresist layer 191. By developing the exposed second photoresist layer 191, the second metal layer 129 to form the data line and the source and drain electrodes, more specifically, the second magnesium oxide formed on the surface of the second metal layer 129. A thick first photoresist pattern 191a is formed on the (MgO) film 143, and at the same time, the first photoresist pattern 191a is formed on the second metal layer 129 of the portion corresponding to the gate electrode 109. The second photoresist pattern 191b having a thinner thickness is formed, and the second magnesium oxide (MgO) film 143 is exposed on the other portions of the second metal layer 129.

The exposure that forms a photoresist pattern having a different thickness by performing one exposure using an exposure mask (195 in FIG. 2D) including the transflective region (HTA in FIG. 2D) is called diffraction exposure. In the case of the first embodiment, the number of mask processes is reduced through such diffraction exposure. In the method of forming a photoresist pattern having a different thickness, the semi-transmissive region (HTA of FIG. 2D) is configured to further include a plurality of coating layers for controlling the amount of light transmission instead of the slit. There is also halftone exposure using an exposure mask, and the same result can be obtained by performing such halftone exposure.

Further, in the case of the present invention, a portion of the photoresist layer corresponding to the transmissive region (TA in FIG. 2D) of the exposure mask (195 in FIG. 2D) is removed during development, using a positive type photoresist. As an example, it is apparent that a negative type photoresist may be used in which the opposite characteristic, ie, a portion of the light, is left after development, in which case the position of the transmission region and the blocking region of the exposure mask may be The same result can be obtained by exposing using the changed exposure mask.

Next, as shown in FIG. 2F, an etching process is performed on the substrate 101 on which the first and second photoresist patterns 191a having different thicknesses are formed, thereby forming the first and second photoresist patterns 191a, Not shown) Created at the interface between the second magnesium oxide (MgO) film 143 exposed to the outside, the second metal layer (129 in FIG. 2E) below and the impurity amorphous silicon layer (116 in FIG. 2D) below The sulfide layer (128 in FIG. 2D), the impurity amorphous silicon layer (116 in FIG. 2D), and the pure amorphous silicon layer (115 in FIG. 2D) below are sequentially etched to expose the gate insulating layer 109.

In this case, the second metal layer, the sulfide layer 128, the impurity amorphous silicon layer, and the pure amorphous silicon layer under the first and second photoresist patterns 191a (not shown) may be formed in the first and second photoresist patterns 181a and the like. H) acts as an etching mask and remains unetched, and the remaining second metal layer is connected to the source drain pattern 131 and the data line 130 in the connected state, and the impurity in the amorphous silicon layer is connected. The amorphous silicon pattern 123 and the pure amorphous silicon layer form the active layer 122. In this case, the patterns 125b and 125a of impurity amorphous silicon and pure amorphous silicon remain in the lower portion of the data line 130 due to process characteristics.

Next, dry etching is performed on the first and second photoresist patterns 191a (not shown) to form a thin second photoresist pattern (not shown) corresponding to the gate electrode 105. Remove it. At this time, the first photoresist pattern 191a formed thicker than the thickness of the second photoresist pattern (not shown) is also etched to reduce the thickness thereof.

Next, as shown in FIG. 2G, exposure between the first photoresist pattern (191a in FIG. 2F) of the switching region TrA using the remaining first photoresist pattern (191a in FIG. 2F) as a mask. The source drain pattern 131 of FIG. 2F is etched, and the sulfide layer 128 and the impurity amorphous silicon pattern 123 of FIG. 2F under the source drain pattern (131 of FIG. 2F) are removed by dry etching. The active layer 122 of pure amorphous silicon under the impurity amorphous silicon pattern 123 of FIG. 2F is exposed.

At this time, in the switching region TrA, the source drain pattern (131 of FIG. 2F) remaining without being etched by the first photoresist pattern (191a of FIG. 2F) is spaced apart from each other. 137).

In addition, the impurity amorphous silicon pattern 124 spaced apart from each other under the source and drain electrodes 135 and 137 forms an ohmic contact layer 124, which, together with the active layer 122 of pure amorphous silicon, is disposed thereunder. The semiconductor layer 124 is formed. In this case, the sulfide layer 128 formed at the interface between the source and drain electrodes 135 and 137 and the ohmic contact layer 124, more specifically, a copper sulfide (CuS) layer becomes the conductive material layer, and thus the ohmic contact layer ( In addition to further improving the characteristics of the 124, these two layers (source and drain electrodes 135 and 137) and the ohmic contact layer 124 also serves to improve the adhesive properties.

In addition, the second magnesium oxide (MgO) film 143 naturally formed on the source and drain electrodes 135 and 137 and the data line 130 may form an insulating layer even though its thickness is very thin.

In addition, the gate insulating layer 109, the semiconductor layer 120, the source and the drain including the gate electrode 109 and the first magnesium oxide film 107 sequentially formed in the switching region TrA from the surface of the substrate 101. The electrodes 135 and 137 form a thin film transistor Tr.

Thereafter, the second photoresist pattern (191a of FIG. 2F) remaining on the data line 130 and the source and drain electrodes 135 and 137 is stripped and removed.

Next, as shown in FIG. 2H, silicon oxide (SiO ₂ ) or silicon nitride (SiNx), which is an insulating material, is deposited on the data line 130 and the source and drain electrodes 135 and 137. The protective layer 150 is formed by applying photoacryl or benzocyclobutene (BCB), and the drain contact hole 155 exposing the drain electrode 137 is formed by patterning through a mask process.

 Next, as shown in FIG. 2I, an indium tin oxide (ITO) or indium zinc oxide (IZO), which is a transparent conductive material, is deposited on the passivation layer 150 having the drain contact hole 155 formed thereon. The array substrate 101 is completed by forming the pixel electrode 160 in contact with the drain electrode 137 through the drain contact hole 155 by patterning through a mask process.

At this time, a second magnesium oxide (MgO) film was formed on the surface of the drain electrode 137 made of a Cu-Mg alloy exposed through the drain contact hole 155, but this is very thin. The contact portion between the drain electrode 137 and the ohmic contact layer 124 causes a problem of deteriorating ohmic characteristics, but the drain electrode 137 and the pixel electrode 160 made of a metal or a conductive material are all formed therebetween. Since the thickness is formed so thin, the role of the insulating layer itself is insignificant, and thus the conduction between these two electrodes 137 and 160 has little effect.

However, as a modified example, FIGS. 3A and 3B (FIG. 3A and 3B) showing the cross-sectional view of the manufacturing process after forming the protective layer (the manufacturing process cross-sectional view of the same part as the cross-sectional view of the manufacturing process of the first embodiment are denoted by adding 100 to the same component. .), As illustrated, the second magnesium oxide (MgO) formed at an interface between the drain electrode 237 and the pixel electrode 260 in contact with each other in the drain contact hole 255 of the protective layer 250. Hydrogen sulfide (H ₂ ) before forming the pixel electrode 260 with respect to the passivation layer 250 having the drain contact hole 255 to suppress the generation of the film 243 and to remove the factors affecting the conduction. S) A plasma treatment in an atmosphere forms a second sulfur material layer (not shown) on the surface of the drain electrode 237 exposed through the drain contact hole 255 and then forms the pixel electrode 260. Capital have. In this case, the second sulfur material layer (not shown) and copper (Cu) react between the drain electrode 237 and the pixel electrode 260 in the drain contact hole 255 to form a second copper sulfide (CuS). Film 257 is formed, and the second copper sulfide (CuS) film 257 has a conductive property, although its level is insignificant, inside the drain contact hole (255 in FIG. 2I) of the first embodiment described above. Deterioration in conduction characteristics by the second magnesium oxide (MgO) film (143 in FIG. 2I) formed at the interface between the drain electrode (137 in FIG. 2I) and the pixel electrode (160 in FIG. 2I) can be further prevented.

As described above, the array substrate for a liquid crystal display device according to the present invention, which is completed through a total of four mask processes including diffraction exposure, has a low resistance metal material in which both the gate wiring and the gate electrode, and the data wiring and the source and drain electrodes are all formed. Formation using Cu-Mg alloy solves problems such as signal delay of wiring due to large area, and at the same time, it is weak substrate due to weak adhesion. It is characterized by solving the problem of separation from water.

In addition, a magnesium oxide (MgO) film is formed by a reaction of magnesium having a strong reactivity at the interface or surface with another material layer, that is, a problem caused when forming an electrode or a wiring from a Cu-Mg alloy. In particular, the problem of lowering ohmic characteristics by increasing the contact resistance between the source and drain electrodes and the ohmic contact layer disposed below the impurity amorphous silicon layer is deposited in a hydrogen sulfide (H ₂ S) atmosphere before deposition of the magnesium oxide (MgO). The treatment suppresses the formation of a magnesium oxide (MgO) film at the interface between the copper magnesium and the impurity amorphous silicon layer, and simultaneously forms a copper sulfide (CuS) film, thereby improving ohmic characteristics.

In the first embodiment described above, the gate wirings and the gate electrodes, the data wirings, the source and the drain electrodes are all formed of Cu-Mg alloy, but the gate wirings and the gate electrodes are made of aluminum or an aluminum alloy. It may be formed.

This is because the present invention causes a problem of deterioration of ohmic characteristics when the source and drain electrodes are formed of the Cu-Mg alloy, which is characteristic of a manufacturing method for improving the same.

Second Embodiment

A second embodiment of the present invention relates to a method of manufacturing an array substrate for a liquid crystal display device by a five mask process.

4A to 4I illustrate cross-sectional views of manufacturing steps according to a five-mask process of an array substrate for a liquid crystal display device using a Cu-Mg alloy according to a second embodiment of the present invention. A cross-sectional view of one pixel area including a. In this case, an area in which the thin film transistor is formed is defined as a switching area.

First, as shown in FIG. 4A, a Cu-Mg alloy is deposited on a transparent insulating substrate 301 to form a first metal layer (not shown), and then a first mask process is performed. By patterning, a gate wiring (not shown) extending in one direction and a gate electrode 305 having a form branching to each pixel region P from the gate wiring (not shown) are formed.

Next, as shown in FIG. 4B, an insulating material, for example, silicon oxide (SiO ₂ ) or silicon nitride (SiNx), is deposited on the gate wiring (not shown) and the gate electrode 305 to form a gate insulating layer 309. Form. In this case, the gate wiring (not shown) and the gate electrode 305 disposed under the gate insulating layer 309 include magnesium (Mg), which is a highly reactive material, in a copper magnesium alloy (Cu-Mg alloy). As the magnesium (Mg) reacts with oxygen, a first magnesium oxide (MgO) film 307 is naturally formed on the surface and the interface between the substrate 301.

Next, as shown in FIG. 4C, pure amorphous silicon and impurity amorphous silicon are sequentially deposited on the gate insulating layer 309 to form a pure amorphous silicon layer (not shown) and an impurity amorphous silicon layer (not shown). The second mask process is patterned to form the semiconductor pattern 320 having a double layer structure of pure and impurity amorphous silicon patterns 322 and 323 corresponding to the gate electrode 305 of the switching region Tr.

Next, as shown in FIG. 4D, the substrate 301 on which the double layer semiconductor pattern 320 is formed is subjected to plasma treatment in a hydrogen sulfide (H ₂ S) atmosphere, and thus, on the impurity semiconductor pattern 323, several tens of nanometers to The sulfur material layer 327 having a thin thickness of about a few angstroms is formed. The reason for the formation is described in detail in the first embodiment, and thus description thereof is omitted.

Next, as shown in FIG. 4E, a Cu-Mg alloy is deposited on the substrate 301 on which the sulfur material layer 327 of FIG. 4D is formed on the semiconductor pattern 320 of FIG. 4D. A data line 330 and a switching region TrA defining a pixel region P by forming a second metal layer (not shown) and patterning the same by performing a third mask process to intersect the gate line (not shown). Source electrode 335 branching from the data line 330 to contact the sulfur material layer 327 of FIG. 4D on the semiconductor pattern 320 of FIG. 4D and more precisely, 320 of FIG. 4D. And a drain electrode 337 spaced apart from the source electrode 335 to be in contact with the sulfur material layer 327 of FIG. 4D.

In this case, a second magnesium oxide (MgO) film 343 is naturally formed on the upper surfaces of the source and drain electrodes 335 and 337, and the lower portion of the sulfur material layer (327 in FIG. 4D) and copper (Cu) is formed. Reacts to form a copper sulfide (CuS) film 328 as a sulfide layer. That is, the sulfur material layer 327 of FIG. 4D reacts with a copper magnesium alloy (Cu-Mg alloy) formed thereon to change into a copper sulfide (CuS) film.

A second magnesium oxide (MgO) film 343 is formed on the upper surface of the data line 330, and a copper sulfide (CuS) film 328 is formed on the interface with the gate insulating film 309.

After the semiconductor pattern (320 of FIG. 4D) is formed, the semiconductor pattern (320) of the semiconductor pattern (320 of FIG. 4D) may be plasma-processed in the hydrogen sulfide (H ₂ S) atmosphere on the entire surface of the substrate 301. This is because the sulfur material layer 327 of FIG. 4D is formed on the gate insulating layer 309 exposed to the outside of the semiconductor pattern 320 of FIG. 4D as well as on the top of 320 of FIG. 4D.

In this case, the copper sulfide (CuS) layer 328 having the conductive property is formed on the entire surface of the lower portion of the second metal layer (not shown). However, the copper sulfide (CuS) layer 328 is patterned to form the data line 330 and the source and drain electrodes. It is etched and removed in the step of forming the 335 and 337, and finally is formed only under the data line 330 and the source and drain electrodes 335 and 337.

Next, an impurity amorphous silicon pattern (FIG. Dry etching of 4d 323 using the source and drain electrodes 335 and 337 as a mask forms an ohmic contact layer 324 of impurity amorphous silicon spaced apart from each other. At this time, the pure amorphous silicon pattern 322 remaining in the connected state forms the active layer 322.

Next, as shown in FIG. 4F, on the substrate 301 having a second magnesium oxide (MgO) film 343 formed on a surface thereof corresponding to the data line 330 and the source and drain electrodes 335 and 337. The protective layer 350 is formed by depositing silicon oxide (SiO ₂ ) or silicon nitride (SiNx), which is an inorganic insulating material, or by applying photoacryl or benzocyclobutene (BCB), which is an organic insulating material, on the front surface and through a mask process. By patterning, a drain contact hole 355 exposing the drain electrode 337 is formed.

 Next, as shown in FIG. 4G, an indium tin oxide (ITO) or an indium zinc oxide (IZO), which is a transparent conductive material, is deposited on the protective layer 350 on which the drain contact hole 355 is formed. The array substrate 301 is completed by forming the pixel electrode 360 in contact with the drain electrode 337 through the drain contact hole 355 by patterning through a mask process.

Similarly, the second embodiment described above also has a second magnesium oxide having a level of several tens of nanometers to several angstroms between the pixel electrode 360 and the drain electrode 337 which are in contact with each other in the drain contact hole 355. As the (MgO) film 343 is formed, the electrical conduction between the two electrodes 337 and 360 is insignificant but may affect it. Therefore, although not shown in the drawings as a modification, after forming the drain contact hole in the protective layer to expose the drain contact hole as in the modification of the first embodiment, the secondary plasma in a hydrogen sulfide (H ₂ S) atmosphere And forming a second sulfur material layer on the exposed drain electrode in the drain contact hole by forming a patterned pixel electrode for each pixel region, and then placing the exposed drain electrode in the drain contact hole and the upper portion of the drain electrode. Instead of the second magnesium oxide (MgO) film 343, a copper sulfide (CuS) film having conductive properties may be formed between the pixel electrodes to further improve conduction characteristics.

As described above, when the gate wiring, the gate electrode, the data wiring, the source and the drain electrode are formed of a Cu-Mg alloy having a relatively low resistance,

First, even if the area of the display device is increased, the signal delay due to signal wiring does not occur, so that the liquid crystal display device can have a large area.

Second, when the wiring is formed of pure copper, there is an effect of solving the problem of separation from the substrate due to the weak adhesive property of the copper, and further, by performing a plasma treatment in hydrogen sulfide (H2S) atmosphere, magnesium oxide due to the reactivity of magnesium By suppressing the (MgO) film formation, there is an effect of improving ohmic characteristics.

Third, when the signal wiring is used as copper magnesium, its resistivity is very low, so that the width of the signal wiring can be significantly reduced, thereby improving the aperture ratio.

Claims (19)

Depositing and patterning a first metal material on a substrate on which the pixel region is defined, and forming a gate wiring extending in one direction and a gate electrode in the pixel region; Forming a gate insulating film on the gate wiring and the gate electrode; Forming a semiconductor pattern on the gate insulating layer corresponding to the gate electrode; Forming a sulfur material layer over the semiconductor pattern by first plasma treating the substrate on which the semiconductor pattern is formed in a hydrogen sulfide (H 2 S) atmosphere; Depositing and patterning a copper alloy on the sulfur material layer to form a data line crossing the gate line to define the pixel area, and forming source and drain electrodes spaced apart from each other on the sulfur material layer in the pixel area. Wow; Forming a protective layer having a drain contact hole exposing a portion of the drain electrode over the source and drain electrodes; Forming a pixel electrode contacting the drain electrode through the drain contact hole on the passivation layer; Method of manufacturing an array substrate for a liquid crystal display device comprising a. The method of claim 1, And the semiconductor pattern comprises an active layer of pure amorphous silicon and an impurity amorphous silicon pattern. The method of claim 2, And forming an ohmic contact layer spaced apart from each other by exposing the active layer by removing the impurity amorphous silicon pattern between the spaced source and drain electrodes. The method of claim 1, A conductive copper sulfide (CuS) film is further formed between the sulfur material layer and the source and drain electrodes formed in contact with the sulfur material layer. Depositing and patterning a first metal material on a substrate on which the pixel region is defined, and forming a gate wiring extending in one direction and a gate electrode in the pixel region; Forming a gate insulating film on the gate wiring and the gate electrode; Forming a layer of pure amorphous silicon and an impurity amorphous silicon over the gate insulating film; First plasma treating the substrate on which the impurity amorphous silicon layer is formed in a hydrogen sulfide (H ₂ S) atmosphere; Depositing a copper alloy on a plasma-treated impurity amorphous silicon layer in the hydrogen sulfide (H ₂ S) atmosphere to form a metal layer; By patterning the metal layer, the impurity amorphous silicon layer, and the pure amorphous silicon layer, source and drain electrodes spaced apart from each other from the uppermost layer corresponding to the gate electrode, an ohmic contact layer of impurity amorphous silicon, and a pure amorphous portion of which is partially exposed thereunder. Forming an active layer of silicon, and defining a pixel area on the gate insulating layer to define the pixel area, and forming a data line connected to the source electrode; Forming a protective layer having a drain contact hole exposing a portion of the drain electrode over the data line and a source and drain electrode; Forming a pixel electrode contacting the drain electrode through the drain contact hole on the passivation layer; Method of manufacturing an array substrate for a liquid crystal display device comprising a. The method of claim 5, A copper sulfide (CuS) film is further formed between the metal layer and the impurity amorphous silicon layer. The method according to claim 1 or 5, The first metal material is a copper magnesium alloy (Cu-Mg alloy) manufacturing method of an array substrate for a liquid crystal display device. The method according to claim 1 or 5, The copper alloy is a copper magnesium alloy (Cu-Mg alloy) manufacturing method of an array substrate for a liquid crystal display device. The method according to claim 1 or 5, And a magnesium oxide (MgO) film is further formed on the gate wiring and the gate electrode. The method according to claim 1 or 5, And forming a second plasma process in a hydrogen sulfide (H ₂ S) atmosphere after forming the protective layer having the drain contact hole. The method of claim 10, A copper sulfide (CuS) film is further formed between the drain electrode and the pixel electrode in the drain contact hole. A gate wiring extending in one direction on the substrate on which the pixel region is defined, and a gate electrode branched from the gate wiring to the pixel region; A gate insulating film formed over the gate wiring and the gate electrode; A semiconductor layer formed on the gate insulating layer to correspond to the gate electrode; A copper sulfide (CuS) film formed on the semiconductor layer and spaced apart from each other; A source and drain electrode formed to be spaced apart from each other by a copper alloy on the copper sulfide (CuS) layer and the same material as the source and drain electrode, and formed to define the pixel region by crossing the gate wiring on the gate insulating layer. Data wiring; A protective layer formed on the data line and on the source and drain electrodes and having a drain contact hole exposing the drain electrode; A pixel electrode formed in contact with the drain electrode through the drain contact hole on the protective layer; Array substrate for a liquid crystal display device comprising a. The method of claim 12, The copper alloy is a copper magnesium alloy (Cu-Mg alloy) array substrate for a liquid crystal display device. The method of claim 12, The semiconductor layer, And an active layer of amorphous silicon and an ohmic contact layer of impurity amorphous silicon spaced apart from each other in correspondence with the gate electrode in a state connected to the gate electrode. The method of claim 14, And the copper sulfide (CuS) layer is formed on the ohmic contact layer spaced apart from each other. The method of claim 12, And a magnesium oxide (MgO) film is further formed between the data line, the source and drain electrodes, and the protective layer. The method of claim 12, And a copper sulfide (CuS) film is further formed between the pixel electrode and the drain electrode in the drain contact hole. The method of claim 12, And the gate wiring and the gate electrode are made of a copper magnesium alloy. The method of claim 18, A magnesium oxide (MgO) film is further formed between the gate wiring and the gate electrode and the gate insulating film.

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