KR101510900B1 - Method of fabricating the array substrate for liquid crystal display device using a oxidized semiconductor - Google Patents

Method of fabricating the array substrate for liquid crystal display device using a oxidized semiconductor Download PDF

Info

Publication number
KR101510900B1
KR101510900B1 KR20080122795A KR20080122795A KR101510900B1 KR 101510900 B1 KR101510900 B1 KR 101510900B1 KR 20080122795 A KR20080122795 A KR 20080122795A KR 20080122795 A KR20080122795 A KR 20080122795A KR 101510900 B1 KR101510900 B1 KR 101510900B1
Authority
KR
South Korea
Prior art keywords
semiconductor layer
photoresist pattern
forming
mask
substrate
Prior art date
Application number
KR20080122795A
Other languages
Korean (ko)
Other versions
KR20100064268A (en
Inventor
김대환
서현식
배종욱
Original Assignee
엘지디스플레이 주식회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 엘지디스플레이 주식회사 filed Critical 엘지디스플레이 주식회사
Priority to KR20080122795A priority Critical patent/KR101510900B1/en
Publication of KR20100064268A publication Critical patent/KR20100064268A/en
Application granted granted Critical
Publication of KR101510900B1 publication Critical patent/KR101510900B1/en

Links

Images

Classifications

    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L27/00Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/12Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1222Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer
    • H01L27/1225Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
    • GPHYSICS
    • G02OPTICS
    • G02FDEVICES OR ARRANGEMENTS, THE OPTICAL OPERATION OF WHICH IS MODIFIED BY CHANGING THE OPTICAL PROPERTIES OF THE MEDIUM OF THE DEVICES OR ARRANGEMENTS FOR THE CONTROL OF THE INTENSITY, COLOUR, PHASE, POLARISATION OR DIRECTION OF LIGHT, e.g. SWITCHING, GATING, MODULATING OR DEMODULATING; TECHNIQUES OR PROCEDURES FOR THE OPERATION THEREOF; FREQUENCY-CHANGING; NON-LINEAR OPTICS; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating, or modulating; Non-linear optics
    • G02F1/01Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating, or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating, or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362Active matrix addressed cells
    • G02F1/1368Active matrix addressed cells in which the switching element is a three-electrode device
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L27/00Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/12Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259Multistep manufacturing methods
    • H01L27/1288Multistep manufacturing methods employing particular masking sequences or specially adapted masks, e.g. half-tone mask
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76Unipolar devices, e.g. field effect transistors
    • H01L29/772Field effect transistors
    • H01L29/78Field effect transistors with field effect produced by an insulated gate
    • H01L29/786Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/7869Thin film transistors, i.e. transistors with a channel being at least partly a thin film having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate

Abstract

The present invention relates to a method of manufacturing an array substrate for a liquid crystal display using an oxide semiconductor layer, the method comprising the steps of: forming a source / drain electrode on a substrate using a first mask; Forming a semiconductor layer including an oxide, a gate insulating film, and a conductive layer for forming a gate on a substrate, forming a first photoresist pattern on the conductive layer for gate formation using a second mask, Exposing a region of the semiconductor layer by etching the photoresist pattern with an etch mask and performing a plasma process on one region of the exposed semiconductor layer to form a semiconductor layer having conductivity, To form a second photoresist pattern, etching the second photoresist pattern with an etching mask to form a gate electrode Forming a third photoresist pattern on the substrate on which the gate electrode is formed using a third mask, etching the third photoresist pattern with an etching mask to form a semiconductor pattern and a pixel electrode, Forming a protective film on the substrate having the pixel electrode and the semiconductor pattern formed thereon and forming a contact hole in the protective film exposing the pixel electrode using a fourth mask.
An oxide semiconductor layer, a top gate

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention [0001] The present invention relates to a method of fabricating an array substrate for a liquid crystal display using an oxide semiconductor layer,

The present invention relates to a method of manufacturing an array substrate for a liquid crystal display, and more particularly, to a method of manufacturing an array substrate for a liquid crystal display using an oxide semiconductor layer.

2. Description of the Related Art In recent years, the importance of flat panel displays (FPDs) has been increasing with the development of multimedia. In response to this, various kinds of devices such as a liquid crystal display (LCD), a plasma display panel (PDP), a field emission display (FED), an electroluminescence display device A flat display of a flat panel display has been put into practical use.

Among them, the liquid crystal display device is superior in visibility to a cathode ray tube, has a small average power consumption and a small calorific value, and has a response speed of 1 ms or less and a high response speed, Since it is self-luminous, there is no problem in the viewing angle, and it is attracting attention as a next generation flat panel display.

A passive matrix method and an active matrix method using a thin film transistor are used for driving the flat panel display device. In the passive matrix method, an anode and a cathode are formed so as to be orthogonal to each other and a line is selected and driven. In the active matrix method, a thin film transistor is connected to each pixel electrode and driven according to a voltage maintained by a capacitor capacitance connected to a gate electrode of the thin film transistor .

Thin film transistors for driving a flat panel display device are important not only in characteristics of basic thin film transistors such as mobility and leakage current but also durability and electrical reliability that can maintain a long lifetime. Here, the semiconductor layer of the thin film transistor is mainly formed of amorphous silicon or polycrystalline silicon. The amorphous silicon has a merit that the film forming process is simple and the production cost is low, but the electrical reliability is not secured. In addition, due to the high process temperature, polycrystalline silicon is very difficult to apply in a large area, and uniformity due to the crystallization method can not be secured.

On the other hand, when a semiconductor layer is formed with an oxide, a high mobility can be obtained even if the film is formed at a low temperature. Since the resistance varies depending on the content of oxygen, it is very easy to obtain desired physical properties. It is attracting great attention. In particular, examples thereof include zinc oxide (ZnO), indium zinc oxide (InZnO), indium gallium zinc oxide (InGaZnO4), and the like.

A thin film transistor substrate using such an oxide semiconductor layer is formed through a plurality of mask processes. One mask process includes a plurality of processes such as a thin film deposition process, a cleaning process, a photolithography process, an etching process, a strip process, an inspection process, and the like.

However, since a large number of mask processes are required, the fabrication process is complicated, leading to an increase in the manufacturing cost of flat panel display devices.

Accordingly, during the manufacturing process of the thin film transistor substrate using the oxide semiconductor layer, a first mask for forming source / drain electrodes, a second mask for forming a semiconductor layer, a third mask for forming a gate, a fourth mask for forming a contact hole, A total of 5 mask processes are used as in the fifth mask process for forming the electrodes. In the 5-mask process, a further reduction in the number of mask processes is required.

An object of the present invention is to provide a method of manufacturing a thin film transistor array substrate using an oxide semiconductor layer capable of reducing the number of masks and lowering the manufacturing cost.

According to an aspect of the present invention, there is provided a method of fabricating a thin film transistor array substrate using an oxide semiconductor layer, the method comprising: forming a source / drain electrode on a substrate using a first mask; Forming a semiconductor layer including an oxide, a gate insulating film, and a conductive layer for forming a gate on a substrate, forming a first photoresist pattern on the conductive layer for gate formation using a second mask, Exposing a region of the semiconductor layer by etching the photoresist pattern with an etch mask and performing a plasma process on one region of the exposed semiconductor layer to form a semiconductor layer having conductivity, To form a second photoresist pattern, etching the second photoresist pattern with an etching mask, Forming a third photoresist pattern on the substrate on which the gate electrode is formed by using a third mask and etching the third photoresist pattern with an etching mask to form a semiconductor pattern and a pixel electrode Forming a protective film on the substrate having the pixel electrode and the semiconductor pattern formed thereon and forming a contact hole in the protective film exposing the pixel electrode using a fourth mask.

The second mask is a diffraction exposure mask.

According to an aspect of the present invention, there is provided a method of fabricating a thin film transistor array substrate using an oxide semiconductor layer, the method comprising: forming a source / drain electrode on a substrate using a first mask; Forming a semiconductor layer including an oxide, a gate insulating film, and a conductive layer for forming a gate on a substrate, forming a first photoresist pattern on the conductive layer for gate formation using a second mask, Exposing a region of the semiconductor layer by etching the photoresist pattern with an etch mask and performing a plasma process on one region of the exposed semiconductor layer to form a semiconductor layer having conductivity, To form a second photoresist pattern, etching the second photoresist pattern with an etching mask, Forming a third photoresist pattern on the substrate on which the gate electrode is formed using a third mask and etching the third photoresist pattern with an etching mask to form a semiconductor pattern and a pixel electrode, Forming a fourth photoresist pattern on the pixel electrode of the substrate by etching the third photoresist pattern; forming a protective film on the substrate on which the fourth photoresist pattern is formed, And removing the fourth photoresist pattern to expose the pixel electrode.

The second and third masks are diffraction exposure masks.

The semiconductor layer including the oxide is a semiconductor layer containing an oxide having an oxygen concentration of 1 to 10%. The semiconductor layer containing the oxide may be any one of ZnO, CdO, GaO, InO, InO, and SnO Wherein the step of forming the semiconductor pattern and the pixel electrode comprises etching the semiconductor layer having conductivity and formed in one region of the semiconductor layer and the semiconductor layer with the third photoresist pattern to form a semiconductor layer having conductivity, The semiconductor layer and the pixel electrode are separately formed.

The method for fabricating a thin film transistor array substrate using the oxide semiconductor layer according to the present invention is performed through a 3-mask or 4-mask process, thereby reducing the number of masks and lowering the manufacturing cost compared to the 5-mask process.

A method of manufacturing a thin film transistor array substrate using the oxide semiconductor layer according to the present invention will now be described in detail with reference to the accompanying drawings.

FIGS. 1A to 1D illustrate a method of manufacturing a thin film transistor array substrate using an oxide semiconductor layer according to a first embodiment of the present invention using a 4-mask process. FIGS. A method of manufacturing a thin film transistor array substrate using an oxide semiconductor layer according to a second embodiment of the present invention is shown.

Hereinafter, a method of manufacturing a thin film transistor substrate using an oxide semiconductor layer according to the present invention will be described first by using a 4-mask process. The thin film transistor formed on the thin film transistor substrate is formed in a top-gate type.

1A to 1D are process flowcharts illustrating a method of manufacturing an array substrate for a liquid crystal display device using an oxide semiconductor layer according to the present invention.

First, source and drain electrodes 12 and 14 are formed on a substrate 10, as shown in FIG. 1A.

The source and drain electrodes 12 and 14 are formed by forming a first conductive layer for forming a source and a drain on a substrate 10 by a deposition method such as a sputtering method and then patterning the substrate by a photo etching process using a first mask .

1B, an active layer 16a, a gate insulating film 18, a second conductive layer 20a for forming a gate are formed on a substrate 10 on which source and drain electrodes 12 and 14 are formed, And a first photoresist pattern 200a are formed.

The first photoresist pattern 200a is formed by forming a photoresist on the second conductive layer 20a and arranging a second mask 202 to perform a photolithography process. Here, the second mask 202 includes a transmissive region 202a through which light is entirely passed, a diffraction exposure region 202b including a plurality of slits for transmitting a part of light and blocking a part of the light, 202c are used. In this case, the blocking region 202c corresponds to a region where a gate electrode is to be defined, the transmissive region 202a corresponds to a region where a pixel electrode will be defined later, and the diffraction exposure region 202b corresponds to a region where the gate electrode and the pixel electrode And corresponds to the remaining area excluding the area to be defined. Therefore, the thickness of the photoresist pattern formed in the diffraction exposure region 202b is smaller than the thickness of the photoresist pattern formed in the blocking region 202c, and the photoresist pattern is not formed in the transmissive region 202a.

The semiconductor layer 16c may include an oxide having an oxygen concentration of 1 to 10%, for example, at least one of ZnO, CdO, GaO, InO, InO, and SnO.

Next, as shown in FIG. 1C, the second conductive layer 20a for gate formation and the gate insulating film 18 are etched using the first photoresist pattern 200a formed on the substrate 10 as an etching mask, The second conductive layer 20a and the gate insulating film 18 are removed. At this time, the one region of the second conductive layer 20a and the gate insulating film 18 are removed, thereby exposing the one semiconductor layer 16a.

Next, a plasma process using hydrogen (H) is performed on the substrate 10 on which the second photoresist pattern 200b is formed, so that conductive electrical characteristics are transferred to the exposed semiconductor layer 16b. As a result, the exposed semiconductor layer 16b becomes conductive, and the unexposed semiconductor layer 16a remains in an oxide-containing state.

Then, the first photoresist pattern 200 is ashed to form a second photoresist pattern 200b remaining only in the region where the gate electrode is to be defined.

1D, the second conductive layer 20a for gate formation is etched using the second photoresist pattern 200b formed on the substrate 10 with the etching mask to form the gate electrode 20b .

Next, as shown in FIG. 1E, a third photoresist pattern 200c is formed on the substrate 10 on which the gate electrode 20b is formed.

The third photoresist pattern 200c is formed by forming a photoresist on a substrate 10 on which a gate electrode 20b is formed and then performing a photolithography process by disposing a third mask (not shown).

Next, as shown in FIG. 1F, the gate insulating film 18 and the semiconductor layer 16a are etched using the third photoresist pattern 200c formed on the substrate 10 as an etching mask. Thereby, the semiconductor pattern 16c forming the channel region is formed between the source electrode 12 and the drain electrode 14, and the pixel electrode 16d is formed.

The pixel electrode 16d and the semiconductor pattern 16c are formed by separating the semiconductor layer 16b having conductivity and the semiconductor layer 16a having the characteristics of the oxide semiconductor layer during the etching process through the third photoresist pattern 200c .

1G, a protective film 22 having a contact hole 24 exposing the pixel electrode 16d is formed on the substrate 10 on which the pixel electrode 16d and the semiconductor pattern 16c are formed. Thereby completing the present step.

By exposing the pixel electrode 16d by forming a contact hole on the pixel electrode 16d, driving of the liquid crystal formed on the pixel electrode 16d thereafter becomes easy.

The passivation layer 22 on which the contact hole 24 is formed is formed by forming a passivation layer on the substrate 10 on which the pixel electrode 16d and the semiconductor pattern 16c are formed and then patterning the passivation layer by a photolithography process using a fourth mask do.

Hereinafter, a method of manufacturing a thin film transistor substrate using an oxide semiconductor layer according to the present invention will be described using a three-mask process. The thin film transistor formed on the thin film transistor substrate is formed in a top-gate type.

FIGS. 2A to 2H are flowcharts illustrating a method of manufacturing a thin film transistor substrate using an oxide semiconductor layer according to a second embodiment of the present invention.

First, source and drain electrodes 32 and 34 are formed on the substrate 30, as shown in FIG. 2A.

The source and drain electrodes 32 and 34 are formed by forming a first conductive layer for forming a source and a drain on a substrate 30 by a deposition method such as a sputtering method and then patterning the photoresist using a photolithography process using a first mask .

2B, a semiconductor layer 36a, a gate insulating film 38, and a second conductive layer 40a for gate formation are formed on a substrate 30 on which the source and drain electrodes 32 and 34 are formed, And a first photoresist pattern 300a are formed.

The first photoresist pattern 300a is formed by forming a photoresist on the second conductive layer 40a and arranging a second mask 402 to perform a photolithography process. Here, the second mask 402 includes a transmissive area 402a through which light is entirely passed, a diffraction exposure area 402b including a plurality of slits for transmitting a part of light and blocking a part of the light, A diffraction exposure mask including a diffraction grating 402c is used. In this case, the blocking region 402c corresponds to a region where a gate electrode is to be defined, the transmissive region 402a corresponds to a region where a pixel electrode will be defined later, and the diffraction exposure region 402b corresponds to a region where the gate electrode and the pixel electrode And corresponds to the remaining area excluding the area to be defined. Therefore, the thickness of the photoresist pattern formed in the diffraction exposure region 402b is smaller than the thickness of the photoresist pattern formed in the blocking region 402c, and no photoresist pattern is formed in the transmissive region 402a.

The semiconductor layer 36c may include an oxide having an oxygen concentration of 1 to 10%, for example, ZnO, CdO, GaO, InO, InO or SnO.

Next, as shown in FIG. 2C, the second conductive layer 40a for gate formation and the gate insulating film 38 are etched using the first photoresist pattern 300a formed on the substrate 30 with an etching mask, The second conductive layer 40a and the gate insulating film 38 are removed.

At this time, the one region of the second conductive layer 40a and the gate insulating film 38 are removed, thereby exposing the one semiconductor layer 36a.

Then, the first photoresist pattern 300a is etched to form a second photoresist pattern 300b remaining only in the region where the gate electrode is to be defined.

Next, a plasma process using hydrogen (H) is performed on the substrate 30 on which the second photoresist pattern 300b is formed, so that electrical characteristics having conductivity are transferred to the exposed semiconductor layer 36b. As a result, the exposed semiconductor layer 36b becomes conductive, and the unexposed semiconductor layer 36a remains in an oxide-containing state.

2D, the second conductive layer 40a for gate formation is etched using the second photoresist pattern 300b formed on the substrate 30 with the etching mask to form the gate electrode 40b .

The etching process performed in the process of forming the gate electrode 40b is performed using an etchant having a selectivity ratio between the second conductive layer for gate formation and the semiconductor layer 36c.

As shown in FIG. 2E, a third photoresist pattern 300c is formed on the substrate 30 on which the gate electrode 40b is formed.

The third photoresist pattern 300c is formed by forming a photoresist on the substrate 10, arranging a third mask 204, and performing a photolithography process. Here, the third mask 204 includes a transmissive region 204a through which light is entirely passed, a diffraction exposure region 204b that includes a plurality of slits that transmit a portion of the light and block a portion of the light, and a blocking region 204c ) Is used as a diffraction exposure mask. In this case, the blocking region 204c corresponds to a region in which a pixel electrode is to be defined, the diffraction exposure region 204b corresponds to a region in which a semiconductor pattern is to be defined, and the transmissive region 204a corresponds to a region in which the semiconductor pattern and the pixel electrode And corresponds to the remaining area excluding the area to be defined. Therefore, the thickness of the photoresist pattern formed in the diffraction exposure region 204b is smaller than the thickness of the photoresist pattern formed in the blocking region 204c, and no photoresist pattern is formed in the transmissive region 204a.

Next, as shown in FIG. 2F, the gate insulating film 38 and the semiconductor layer 36a are etched using the third photoresist pattern 300c formed on the substrate 30 with the etching mask. As a result,

A semiconductor pattern 36c forming a channel region is formed between the source electrode 32 and the drain electrode 34 to form the pixel electrode 36d.

The pixel electrode 36d and the semiconductor pattern 36c are formed by separating the semiconductor layer 36b having conductivity and the semiconductor layer 36a having the characteristics of the oxide semiconductor layer during the etching process through the third photoresist pattern 300c .

Next, the third photoresist pattern 300c is etched to form a fourth photoresist pattern 300d remaining on the pixel electrode 36d.

Next, as shown in FIG. 2G, a protective film 42 is formed on the substrate 30 on which the fourth photoresist pattern 300d is formed.

2H, a lift-off process is performed on the substrate 30 on which the protective film 22 is formed, so that the fourth photoresist pattern 300d is removed.

When the fourth photoresist pattern 300d is removed as described above, the third photoresist pattern 300d is removed together with the protective film 22 formed on the fourth photoresist pattern 300d, 36d are exposed. By exposing the pixel electrode 36d as described above, driving of the liquid crystal formed on the pixel electrode 36d thereafter becomes easy.

FIG. 3A shows a SAM picture after the process of FIG. 2F is completed, that is, a fourth photoresist pattern formed on the pixel electrode. FIG. 3B shows a drawing after the process of FIG. 2H is completed, And an SMA photograph showing the exposed pixel electrode 36d after the pattern is removed is shown.

As shown in FIG. 2E, the etching process performed in the process of forming the gate electrode 40b uses an etchant having a selectivity ratio between the second conductive layer for gate formation and the semiconductor layer 36c. Therefore, When the pixel electrode having a line width narrower than the line width of the resist pattern is formed and when the fourth photoresist pattern is formed by ashing the third photoresist pattern only the thickness is reduced and the line width is not reduced, , A pixel electrode having a line width narrower than the line width of the fourth photoresist pattern can be formed.

When the fourth photoresist pattern and the fourth photoresist pattern are removed by performing a lift-off process after forming the protective film on the pixel electrode, the protective film is completely removed and only the pixel electrode So that it can remain.

4A and 4B, the thin film transistor formed through the method of fabricating the thin film transistor array substrate using the oxide semiconductor layer has excellent uniformity and reliability characteristics.

FIGS. 1A to 1D are cross-sectional views illustrating a method of manufacturing a thin film transistor array substrate using an oxide semiconductor layer according to a first embodiment of the present invention using a 4-mask process

FIGS. 2A to 2F are cross-sectional views illustrating a method of manufacturing a thin film transistor array substrate using an oxide semiconductor layer according to a second embodiment of the present invention,

FIGS. 3A and 3B are photographs showing the state of film formation and removal during the manufacturing process of the present invention

FIGS. 4A and 4B are graphs showing characteristics of a thin film transistor using an oxide semiconductor layer formed according to the present invention

Claims (10)

  1. Forming a source / drain electrode on the substrate using a first mask;
    Forming a semiconductor layer including an oxide, a gate insulating layer, and a conductive layer for forming a gate on the substrate on which the source / drain electrode is formed; forming a first photoresist pattern on the conductive layer for gate formation using a second mask; , ≪ / RTI &
    Exposing a region of the semiconductor layer by etching the first photoresist pattern with an etch mask and performing a plasma process on one region of the exposed semiconductor layer to form a semiconductor layer having conductivity,
    Etching the first photoresist pattern to form a second photoresist pattern, etching the second photoresist pattern with an etch mask to form a gate electrode,
    Forming a third photoresist pattern on the substrate on which the gate electrode is formed using a third mask, etching the third photoresist pattern with an etching mask to form a semiconductor pattern and a pixel electrode,
    Forming a protective film on the substrate having the pixel electrode and the semiconductor pattern formed thereon, and forming a contact hole in the protective film exposing the pixel electrode using a fourth mask, the thin film transistor array substrate using the oxide semiconductor layer ≪ / RTI >
  2. The semiconductor device according to claim 1, wherein the oxide-
    Wherein the oxide semiconductor layer is a semiconductor layer containing an oxide having an oxygen concentration of 1 to 10%.
  3. 3. The semiconductor device according to claim 2, wherein the oxide-
    ZnO, CdO, GaO, InO, InO, and SnO. The method of manufacturing a thin film transistor array substrate using the oxide semiconductor layer according to claim 1,
  4. The method of claim 1, wherein forming the semiconductor pattern and the pixel electrode comprises:
    A conductive semiconductor layer formed on one of the semiconductor layer and the semiconductor layer is etched into the third photoresist pattern to separate the conductive semiconductor layer and the oxide semiconductor layer into a semiconductor pattern and a pixel electrode, And forming an oxide semiconductor layer on the substrate.
  5. The method of manufacturing a thin film transistor array substrate according to claim 1, wherein the second mask is a diffraction exposure mask.
  6. Forming a source / drain electrode on the substrate using a first mask;
    Forming a semiconductor layer including an oxide, a gate insulating film, and a gate forming conductive layer on the substrate on which the source / drain electrode is formed; forming a first photoresist pattern on the conductive layer for gate formation using a second mask; ;
    Exposing a region of the semiconductor layer by etching the first photoresist pattern with an etch mask and performing a plasma process on one region of the exposed semiconductor layer to form a semiconductor layer having conductivity,
    Etching the first photoresist pattern to form a second photoresist pattern, etching the second photoresist pattern with an etch mask to form a gate electrode,
    Forming a third photoresist pattern on the substrate on which the gate electrode is formed using a third mask, etching the third photoresist pattern with an etching mask to form a semiconductor pattern and a pixel electrode,
    Forming a fourth photoresist pattern on the pixel electrode of the substrate by ashing the third photoresist pattern;
    Forming a protective film on the substrate having the fourth photoresist pattern formed thereon, performing a lift-off process on the substrate having the protective film formed thereon, and removing the fourth photoresist pattern to expose the pixel electrode, A method of manufacturing a transistor array substrate.
  7. 7. The method of claim 6, wherein the oxide-
    Wherein the oxide semiconductor layer is a semiconductor layer containing an oxide having an oxygen concentration of 1 to 10%.
  8. 8. The semiconductor device according to claim 7, wherein the oxide-
    ZnO, CdO, GaO, InO, InO, and SnO. The method of manufacturing a thin film transistor array substrate using the oxide semiconductor layer according to claim 1,
  9. 7. The method of claim 6, wherein forming the semiconductor pattern and the pixel electrode comprises:
    A conductive semiconductor layer formed on one of the semiconductor layer and the semiconductor layer is etched into the third photoresist pattern to separate the conductive semiconductor layer and the oxide semiconductor layer into a semiconductor pattern and a pixel electrode, And forming an oxide semiconductor layer on the substrate.
  10. The method of manufacturing a thin film transistor array substrate according to claim 6, wherein the second and third masks are diffraction exposure masks.
KR20080122795A 2008-12-04 2008-12-04 Method of fabricating the array substrate for liquid crystal display device using a oxidized semiconductor KR101510900B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR20080122795A KR101510900B1 (en) 2008-12-04 2008-12-04 Method of fabricating the array substrate for liquid crystal display device using a oxidized semiconductor

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR20080122795A KR101510900B1 (en) 2008-12-04 2008-12-04 Method of fabricating the array substrate for liquid crystal display device using a oxidized semiconductor

Publications (2)

Publication Number Publication Date
KR20100064268A KR20100064268A (en) 2010-06-14
KR101510900B1 true KR101510900B1 (en) 2015-04-10

Family

ID=42363961

Family Applications (1)

Application Number Title Priority Date Filing Date
KR20080122795A KR101510900B1 (en) 2008-12-04 2008-12-04 Method of fabricating the array substrate for liquid crystal display device using a oxidized semiconductor

Country Status (1)

Country Link
KR (1) KR101510900B1 (en)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP6014362B2 (en) * 2011-05-19 2016-10-25 株式会社半導体エネルギー研究所 Method for manufacturing semiconductor device
KR102056464B1 (en) 2013-03-05 2019-12-17 삼성디스플레이 주식회사 Touch Screen Panel
KR20150070491A (en) 2013-12-16 2015-06-25 삼성디스플레이 주식회사 Thin film transistor array panel and method of manufacturing the same

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20070118430A (en) * 2006-06-12 2007-12-17 엘지.필립스 엘시디 주식회사 Array substrate for liquid crystall display device and methode for fabricating the same
KR20080059801A (en) * 2006-12-26 2008-07-01 엘지디스플레이 주식회사 Liquid crystal display device and method of manufacturing the same
KR20080067562A (en) * 2007-01-16 2008-07-21 가부시키가이샤 히타치 디스프레이즈 Display device

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20070118430A (en) * 2006-06-12 2007-12-17 엘지.필립스 엘시디 주식회사 Array substrate for liquid crystall display device and methode for fabricating the same
KR20080059801A (en) * 2006-12-26 2008-07-01 엘지디스플레이 주식회사 Liquid crystal display device and method of manufacturing the same
KR20080067562A (en) * 2007-01-16 2008-07-21 가부시키가이샤 히타치 디스프레이즈 Display device

Also Published As

Publication number Publication date
KR20100064268A (en) 2010-06-14

Similar Documents

Publication Publication Date Title
US7629633B2 (en) Vertical thin film transistor with short-channel effect suppression
DE102009044337B4 (en) Array substrate for a display and method of making the same
US6617203B2 (en) Flat panel display device and method of manufacturing the same
US9515100B2 (en) Array substrate, manufacturing method thereof and display device
TWI467772B (en) Array substrate for fringe field switching mode liquid crystal display and method of manufacturing the same
JP2016194703A (en) Display device and manufacturing method thereof
JP2010041058A (en) Thin film transistor, substrate and manufacturing method thereof
US7989274B2 (en) Display device having oxide thin film transistor and fabrication method thereof
US8829511B2 (en) Hybrid thin film transistor, manufacturing method thereof and display panel having the same
US8062936B2 (en) Method of fabricating array substrate
JP3958605B2 (en) Active matrix display device using thin film transistor and manufacturing method thereof
US20150214373A1 (en) Thin film transistor and manufacturing method thereof, array substrate and display device
US7727824B2 (en) Liquid crystal display device and fabricating method thereof
KR101218090B1 (en) Oxide thin film transistor and method of fabricating the same
TW201327832A (en) Thin film transistor substrate and manufacturing method thereof, display
US8822995B2 (en) Display substrate and method of manufacturing the same
US9449995B2 (en) Array substrate and manufacturing method thereof, display device
US8241933B2 (en) Organic light emitting diode display and method of manufacturing the same
KR101280827B1 (en) Array substrate and method of fabricating the same
US20080225190A1 (en) Semiconductor structure and fabricating method thereof for liquid crystal display device
US20160141425A1 (en) Thin film transistor assembly, array substrate method of manufacturing the same, and display device
US8497147B2 (en) Array substrate and method of fabricating the same
US8883579B2 (en) Array substrate for organic electroluminescent display device and method of fabricating the same
US7061019B2 (en) Semiconductor circuit array substrate with a photo-electric sensor portion
JP2008028399A (en) Display with thin film transistor device having different electrical characteristics in pixel and driving regions, and method for fabricating the same

Legal Events

Date Code Title Description
A201 Request for examination
E701 Decision to grant or registration of patent right
FPAY Annual fee payment

Payment date: 20190318

Year of fee payment: 5