KR20070117222A - Method of ldpc encoding and ldpc decoding using a reference matrix - Google Patents

Abstract

A method of LDPC(Low Density Parity Check) encoding and LDPC decoding using a reference matrix is provided to reduce a memory of a system, by not increasing the size of the memory in extending encoding rate. According to a method for performing LDPC(Low Density Parity Check) encoding by using a model matrix including a specific information word and a parity part, the information word part includes at least one reference matrix and at least one conversion matrix by cyclic-shifting the reference matrix. The position of a component with weight included in the conversion matrix is determined by the position of a component with weight included in the reference matrix.

Description

Method of LDPC encoding and LDPC decoding using a reference matrix}

1 is a view showing the structure of a mobile communication channel to which the present invention and the prior art are applied.

2 is a diagram for explaining structured LDPC.

3 is a view showing a model matrix according to the prior art.

4 is a diagram illustrating a method of expressing a matrix according to a shift number.

5 is a diagram illustrating an LDPC decoding method.

6 is a diagram illustrating a structure of a parity check matrix of an LDPC code of a train structure according to the related art.

7 is a diagram illustrating a model matrix generated using a specific reference matrix according to the present embodiment.

8A is an example of a reference matrix according to the present embodiment.

8B to 8G show an example in which the reference matrix of FIG. 8A is modified.

9 is a diagram illustrating performance when encoding is performed using a parity check matrix according to the present embodiment.

The present invention relates to low density parity check (LDPC) encoding and decoding, and more particularly, to a method and an apparatus for performing efficient encoding and decoding using a small storage space.

1 is a view showing the structure of a mobile communication channel to which the present invention and the prior art are applied. Hereinafter, the structure of a mobile communication channel will be described with reference to FIG. 1. In order to transmit the data to be transmitted from the transmitter without loss or distortion in the radio channel, a channel coding procedure is performed. As the channel coding technique, there are various techniques such as convolutional coding, turbo coding, and LDPC coding. Data that has undergone the channel coding procedure may be transmitted as a single symbol by collecting a plurality of bits when transmitted through a wireless channel. In this case, a procedure in which several bits are mapped to one symbol is called modulation.

The modulated data is converted into a signal for multiplex transmission through a multiplexing process or a multiple access method. As the multiplexing method, various methods such as CDM, TDM, and FDM exist. In FIG. 1, an example of orthogonal frequency division multiplexing (OFDM) is illustrated. The signal that has passed through the multiplexing block is changed into a structure suitable for transmission to one or more multiple antennas and transmitted to a receiver through a radio channel. Data transmitted in the course of passing through the wireless channel may experience fading and thermal noise, which may cause distortion of the data.

The modulated data is transmitted to a receiver through a wireless channel. In this process, the transmitted data may experience fading and thermal noise, which may cause distortion of the data. After receiving the distorted data, the receiving end performs a series of procedures in the reverse order. A demodulation operation of converting the data mapped to the symbol into a bit string is performed, and the distorted data is restored to the original data through a channel decoding process.

The apparatus for performing channel coding generates a parity check derived from an H matrix or an H matrix, which is a parity check matrix used to generate parity bits to be added to input data (Systematic Bits). It stores G matrix, which is a parity check generate matrix. That is, the transmitting end includes an encoder for generating parity bits through the H or G matrix and the input data. The apparatus for performing channel decoding checks whether the inputted data (Systematic Bits) are properly recovered through the H matrix and the operation of the received data (distorted Systematic Bits + Parity Bits). Rerun

The modulation includes Binary Phase Shift Keying (BPSK), Quadrature Phase Shift Keying (QPSK), Quadrature Amplitude Modulation (16-QAM), 64-QAM, 256-QAM, and the like. For example, 16-QAM maps a sequence of data that has undergone a channel encoding procedure to one symbol in units of 4 bits during modulation. In demodulation, 16-QAM demaps one symbol of data received through a wireless channel into four bits.

Hereinafter, the LDPC code will be described. The concept of the LDPC code is as follows.

을 만족하도록 부호가 구성된다는 점이다. 이 선형 부호의 일종으로서, 최근에 주목받는 LDPC 부호는 1962년 Gallager에 의하여 처음 제안되었다. 이 부호의 특징으로는 패리티 체크 행렬의 성분이 대부분 0으로 이루어지고, 0이 아닌 성분의 개수는 부호 길이에 비하여 적은 수를 가지도록 하여 확률을 기반으로 한 반복적 복호가 가능한 점이다. 처음 제안된 LDPC 부호는 패리티 체크 행렬을 비체계적인(non-systematic) 형태로 정의하였고, 그것의 행과 열에 균일하게 적은 무게(weight)를 갖도록 설계되었다. The linear code can be described by the generation matrix G or parity check matrix H. The characteristic of linear code is that for all codewords c,

The sign is constructed to satisfy. As a form of this linear code, a recent notable LDPC code was first proposed by Gallager in 1962. The characteristic of this code is that the components of the parity check matrix are mostly 0, and the number of non-zero components has a smaller number than the code length so that iterative decoding based on probability is possible. The first proposed LDPC code defines the parity check matrix in a non-systematic form and is designed to have a uniformly low weight in its rows and columns.

Here, the weight means the number of 1s included in a column or a row in the matrix.

Since the density of nonzero components on the parity check matrix H of the LDPC code is small, the decoding complexity is low. In addition, the decoding performance is also better than the existing codes, showing a good performance close to Shannon's theoretical limit. The LDPC code, however, was a hardware technology that was difficult to implement at the time and has not attracted much attention for more than 30 years. In the early 1980s, a method of iterative decoding using a graph was developed, and various algorithms were developed to actually decode the LDPC code using the graph. The sum-product algorithm can be extracted as the representative algorithm.

Hereinafter, the features of the LDPC code will be described. LDPC codes have high error correction performance, which allows for improvements in communication speed and capacity. The LDPC code may be applied to a high speed wireless LAN capable of transmitting hundreds of Mbit / s in combination with a multiple input multiple output (MIMO) system, and may be applied to high speed mobile communication having a transmission speed of 1 Mbit / s or more at 250 km / h. It can also be applied to optical communication of 40Gbits / s or more. In addition, the high error correction performance of the LDPC code may improve the transmission quality, thereby enabling quantum encrypted communication that reduces the number of retransmissions in a low quality communication path. In addition, due to the low complexity and excellent loss compensation of the LDPC code, lost packets can be easily recovered, which makes it possible to transmit content of the same quality as TV quality through the Internet and mobile communication. Due to the wide coverage and large capacity of LDPC, 10GBASE-T transmissions up to the 100m range, previously considered impossible, are possible with LDPC codes. At the same time, the transmission capacity of a single satellite transmitter in the 36MHz band can be increased by 1.3 times to 80Mbit / s. These advantages are being adopted as the next generation channel coding method in IEEE802.16 system and IEEE802.11 system for high frequency efficiency.

The structured LDPC is described below.

In order to use the LDPC code includes a matrix H to use, uses a parity check matrix H is most 0 and part of one of the components (elemnet), the H matrix, since the size of the H matrix size by more than 10 ⁵ bits It requires a large amount of memory to represent. The structured LDPC technique is a method of expressing the components of the H matrix used for LDPC encoding and decoding into sub-blocks (or sub matrices) having a constant size as shown in FIG. 2. In IEEE802.16e, the subblock is represented by one integer index to reduce the size of memory required to store the H matrix. The subblock may be various matrices, for example, a permutation matrix of a constant size.

In the structured LDPC technique, instead of storing a matrix of 1 or 0 in a specific memory, only one integer (that is, an index) needs to be stored. Can be reduced.

For example, when the size of the codeword reflected in the IEEE802.16e standard is 2304 and the code rate is 2/3, the model matrix used for LDPC encoding / decoding is shown in FIG. Same as 3.

As shown in FIG. 3, the structured LDPC matrix of IEEE802.16e consists of -1, 0 and positive integer components. -1 is a zero matrix of all elements 0 and 0 represents an identity matrix. Positive integer components other than -1 and 0 are permutation matrices in which the identity matrix is shifted to the right by a positive integer. That is, if the component of the matrix is 3, it represents a permutation matrix having the unit matrix shifted three times to the right.

4 is a diagram illustrating a method of expressing a matrix according to the aforementioned positive integer, that is, a shift number. When a specific H matrix is structured and expressed as a matrix having a size of 4 * 4 (that is, a sub block), if the specific sub block is denoted as 3, the sub block becomes the matrix of FIG.

Hereinafter, the LDPC encoding method will be described.

In the general LDPC encoding method, a generation matrix G is derived from an LDPC parity check matrix H to encode an information bit. In order to derive the generation matrix G, the inspection matrix H is configured in the form of [P ^T : I] through a Gaussian Reduction method. When the number of information bits is k and the size of an encoded codeword is n, the P matrix is a matrix in which the number of rows is k and the number of columns is nk, and I is K is the identity matrix whose k column size is k.

The generation matrix G becomes a [I: P] matrix when the check matrix H is expressed as [P ^T : I]. If the encoded information bits of k-bit size are represented in a matrix, the number of rows is 1 and the number of columns is k. In this case, the code word c is described as follows.

In the above equation, x denotes a systematic part and xP denotes a parity part.

)을 이용하여, 상기 수학식 1에서 H^T을 곱하면, 하기 수학식 2 같은 수학식을 얻을 수 있다. 하기 수학식 2에 부합하는 패리티 비트를 정보 비트(x) 뒤에 추가하여 코드워드 c를 얻을 수 있다. On the other hand, in the case of encoding by the Gaussian Reduction method as described above, a large amount of calculation is performed, and a method of directly encoding the H matrix without inducing the G matrix by designing the shape of the H matrix into a special structure. Use That is, H ^{T in the} form of a transpose of the G matrix and the H matrix. The product of 0 (that is,

By multiplying H ^T by Equation 1, Equation 2 can be obtained. A codeword c may be obtained by adding a parity bit corresponding to Equation 2 after the information bit x.

Hereinafter, the LDPC decoding method will be described.

The coded data in the communication system includes noise in the process of passing through the wireless channel of FIG. 1, and the receiving end performs decoding of the data through the procedure of FIG. 5. The decoding block of the receiving end obtains the information bit (x) from the received signal (c ') with noise added to the coded code (c), and finds it using the property of cH ^T = 0. That is, when the received codeword is c ', the value of c'H ^T is calculated, and if the result is 0, the first k bits in c' are determined as the information bits x. If the value of c'H ^T is not 0, a decoding technique such as a sum-product algorithm through a graph is used to find c 'whose value of c'H ^T satisfies 0. recover (x)

Hereinafter, the code rate of the LDPC code will be described.

In general, a code rate (R) is as follows when the size of the information bit is k and the size of the codeword actually transmitted is n.

R = k / n

The code rate is as follows when the row size of the H matrix required for LDPC encoding and decoding is m and the size of the column is n.

R = 1-m / n

As described above, since the conventional LDPC code performs encoding and decoding by the H matrix, the structure of the H matrix is very important. That is, since the performance of encoding and decoding is greatly affected by the structure of the H matrix, the design of the H matrix is most important.

6 is a diagram illustrating a structure of a parity check matrix of an LDPC code of a train structure according to the related art. The train structured LDPC code is also referred to as a data punctured LDPC code or shortening LPDC code. The matrix of FIG. 6 shows a model matrix corresponding to the parity check matrix, and one block corresponds to one sub-matrix (or sub-block). The LDPC code of the train structured performs encoding by fixing a parity part and varying the size of the information word part. Since the size of the information word portion changes, the parity check matrix of FIG. 6 supports various code rates. In FIG. 6, the code rate according to the parity check matrix is changed from 1/3 to 5/6.

The parity check matrix for the LDPC code of the train structure is added with information word portions of various sizes to support various code rates. For example, to increase the code rate from 2/3 to 3/4, a 16 * 16 sub-matrix 601 may be added. In this case, the size of the model matrix corresponding to the parity check matrix is 16 * 64. In addition, when the model matrix of FIG. 6 supports a code rate of 4/5, a 16 * 16 sub-matrix 602 should be added. In this case, the size of the model matrix corresponding to the parity check matrix is 16 * 80.

The LDPC code of a train structure according to the prior art has an advantage of supporting various code rates when information bits have various sizes. However, the LDPC code of the train structure according to the prior art has the following problems.

In general, the LDPC code utilizes a very sparse specific gravity of nonzero elements of the parity check matrix. In addition, when based on the structured LDPC (LDPC) described above, a general LDPC encoder includes a position memory containing position information where a component having weight is located and a specific permutation index of the component having weight. That is, an index memory for storing the number of shifts) is provided. If the above-described train structure (Train structured) LDPC code is used as shown in Figure 6 the size of the information word portion of the matrix is very large. In this case, the size of the location memory becomes too large. That is, the size of the location memory increases linearly as each sub-matrix is added, such as regions 601 and 602 of FIG. 6. Table 1 below shows a change in the size of the location memory when using a train structured LDPC code. The location memory size of Table 1 below is a 16 * 16 sub-matrix added to increase the code rate, has a weight of 3 in terms of the check node of the model matrix, and a variable node. It is related to the case that the weight is 3 in the side.

Code rate Size of location memory additionally required according to the prior art 2/3 3 * 16 3/4 3 * 16 4/5 3 * 16 5/6 3 * 16 6/7 3 * 16 7/8 3 * 16 8/9 3 * 16 9/10 3 * 16 10/11 3 * 16 11/12 3 * 16 12/13 3 * 16 13/14 3 * 16 14/15 3 * 16 15/16 3 * 16 16/17 3 * 16 17/18 3 * 16 Total memory 3 * 16 * 16 = 768

As shown in Table 1, as the code rate increases by one step, an additional position memory of 3 * 16 is required. If all 16 code rates shown in Table 1 are supported, a total of 768 memories are required.

In summary, the conventional method using a train structured LDPC code has an advantage of supporting various code rates, but the size of the location memory that stores information about non-zero components of the parity check matrix increases linearly. There is a problem.

It is proposed to improve the above-described prior art of the present invention, and an object of the present invention is to propose an encoding and decoding method that requires a memory of a smaller size than the prior art.

Another object of the present invention is to propose an encoding and decoding method having improved performance.

Summary of the Invention

In order to achieve the above object, the present invention provides a method for performing LDPC encoding using a parity check matrix including a specific information word part and a parity part, which is extended from a model matrix consisting of first subblocks having a specific size. Performing encoding on information bits of a specific size using the generated parity check matrix; And transmitting the coded codeword, wherein the information word portion of the model matrix includes at least one reference matrix and at least one transform matrix for performing a cyclic shift on the reference matrix. Characterized in that it comprises a.

Another feature of the invention is that the position of the weighted component included in the at least one transformation matrix is determined according to the position of the weighted component included in the reference matrix.

The encoding method according to the present invention is a method for performing LDPC encoding using a parity check matrix including a specific information word part and a parity part, and is extended from a model matrix corresponding to a specific first code rate. Performing encoding on information bits of a specific size using the generated parity check matrix; Transmitting the coded codeword; Performing encoding on information bits of a specific size by using a parity check matrix generated by extending from a model matrix corresponding to a specific second code rate; And transmitting the coded codeword, wherein an information word portion of a model matrix corresponding to the first code rate and the second code rate includes at least one reference matrix and a cyclic shift with respect to the reference matrix. It characterized in that it comprises at least one transformation matrix performing a (cyclic shift).

In accordance with another aspect of the present invention, there is provided a decoding method comprising: receiving an LDPC coded codeword using a parity check matrix including a specific information word part and a parity part; And performing decoding on the codeword using a parity check matrix generated by extending from a model matrix of first subblocks having a specific size, wherein the information word portion of the model matrix includes at least: One reference matrix and at least one transform matrix for performing a cyclic shift (cyclic shift) with respect to the reference matrix.

The encoding and decoding according to the present invention is characterized by using a specific reference matrix. The reference matrix is preferably designed in consideration of cycle characteristics. In the encoding and decoding according to the present invention, encoding and decoding are performed using the above-described train structure LDPC code, but encoding and decoding are performed using a parity check matrix generated by extending the reference matrix. The parity check matrix used in the present invention is preferably generated by cyclic shifting a row of a specific reference matrix or by adding a matrix cyclically shifting the columns of the reference matrix to the information word portion of the parity check matrix. . Since the encoding and decoding method according to the present invention uses a modified matrix of the reference matrix, it is possible to support various code rates through a small memory.

One embodiment of the invention

The construction, operation and effects of the present invention will be embodied by one embodiment of the present invention described below. Hereinafter, with reference to the accompanying drawings will be described an embodiment of the present invention.

Hereinafter, a matrix representing a parity check matrix in a subblock (or sub-matrix) having a specific z * z size according to the structured LDPC described above is called a model matrix. Each sub block of the model matrix can be extended to various kinds of matrices by a specific index, and the model matrix has the index as a component. Each sub block of the model matrix may be determined in various ways according to the index. Hereinafter, it is assumed that the index is a shift number for a unit matrix of a specific size z * z. In addition, when the index is -1, the sub block having the index of -1 is a zero matrix of a specific size z * z.

Since the model matrix is extended to a specific parity check matrix according to the index, encoding and decoding by the model matrix means that encoding and decoding are performed by a specific parity check matrix generated by the model matrix. do.

7 is a diagram illustrating a model matrix generated using a specific reference matrix according to the present embodiment. The parity check matrix corresponding to the model matrix has a structure as shown in Equation 5 below.

When the model matrix of FIG. 7 is referred to as H _b , the H _b includes an information word part H _b1 and a parity part H _b2 corresponding to an information bit one-to-one. K _b represents the number of subblocks corresponding to the information word in the model matrix of FIG. 7. In addition, the m _b is the number of sub-blocks located in the column direction in the model matrix. That is, the information word portion of the model matrix has a size of m _b * k _b when expressed in units of sub-blocks. In addition, the parity portion of the model matrix has a size of m _b * m _b when expressed in units of sub-blocks.

The encoding and decoding method according to the present embodiment performs encoding and decoding using the model matrix of FIG. 7. The model matrix of FIG. 7 includes a specific reference matrix and at least one hybrid cyclic shift matrix obtained by converting the specific reference matrix. That is, the information word portion of the model matrix according to the present embodiment includes a specific reference matrix and matrices obtained by converting the reference matrix. Since the encoding and decoding method according to the present embodiment uses the above-described train structured LDPC code, the size of the parity portion H _b2 is fixed according to the code rate. However, the size of the information word portion H _b1 increases as the code rate increases. The parity check matrix or model matrix according to the present embodiment includes an information word part including the reference matrix when used for encoding and decoding at a low code rate. If the parity check matrix according to the present embodiment is used for encoding / decoding of a relatively high code rate, the parity check matrix includes an information word portion further including an additional sub-matrix. In this case, it is preferable that the additional sub-matrix converts the reference matrix. That is, it is preferable that the sub-matrix added as the code rate is increased by cyclic shifting the row or column of the reference matrix. In addition, the sub-matrix added as the code rate increases may adjust the order of the columns of the reference matrix. That is, the added sub-matrix may be an interleaving of a column of the reference matrix. After the cyclic shift of the rows of the reference matrix, additional cyclic shifts or interleaving of the columns may be performed to generate additional sub-matrices.

In the example of FIG. 7, the parity portion is composed of a 16 * 16 sub-matrix, and the information word portion corresponding to 1/3 code rate is composed of a 16 * 8 sub-matrix 705. In addition, the information word portion corresponding to the 1/2 code rate consists of submatrices 705 and 706 having a size of 16 * 16. In addition, a reference matrix 701 may be added to support the 2/3 code rate. Unlike the example of FIG. 7, the submatrices 705 and 706 of the information word portion corresponding to 1/3 or 1/2 code rate are set by using the reference matrix 701 as the information word part to support the 1/2 code rate. Can be configured. However, the information word portion corresponding to the 1/2 to 1/3 code rate corresponding to the relatively low code rate may have a larger weight of the row or column than the reference matrix 701. Accordingly, according to the present invention, the information word part corresponding to the 1/2 or 1/3 code rate is designed as a separate sub-matrix, and the information word part 701 additionally included for the 2/3 code rate is used as the reference matrix. It is more preferable to set it as. In order to support the improved 3/4 code rate compared to the 2/3 code rate, an additional sub-matrix must be included in the 702 region. In this case, a first hybrid cyclic shift matrix specific to the region 702 is included. In addition, to support an improved 4/5 code rate compared to the 3/4 code rate, an additional sub-matrix must be included in the 703 region. In this case, a second hybrid cyclic shift matrix specific to the region 703 is included. In addition, in order to support an improved 5/6 code rate compared to the 4/5 code rate, an additional sub-matrix must be included in the 704 region. In this case, a third hybrid cyclic shift matrix specific to the region 704 is included as described above. The first to third hybrid cyclic shift matrices are modified matrices of the reference matrix. That is, as described above, the matrix is a manipulation of the order of the rows or columns of the reference matrix.

Hereinafter, various methods for generating a hybrid cyclic shift matrix obtained by converting the reference matrix and the reference matrix will be described.

8A is an example of a reference matrix according to the present embodiment. The model matrix of FIG. 8A is 16 * 16 in size, and an index value not otherwise indicated is '-1'. In FIG. 8A, x1 to x48 represent indexes included in the reference matrix, that is, the number of shifts. Since the index values of x1 to x48 may be freely determined, they may be free integers within the z factor of each subblock. The reference matrix used in this embodiment is preferably designed in consideration of the characteristics of the cycle. That is, it is preferable to use a reference matrix that minimizes the number of cycles. An example of FIG. 8A is a matrix that contains only at least 6 cycles without 4 cycles. Four cycles, if you create a path that connects each position of weight in a parity check matrix in a straight line, the path from a particular bit node arrives at itself through four straight lines (ie, edges). It shows the structure of the matrix. Also, six cycles represent the structure of a matrix arriving at itself by six edges. For a particular parity check matrix, it is desirable to minimize the number of cycles. 8A is only an example of the reference matrix proposed in this embodiment, and the present invention is not limited to the matrix of FIG. 8A. Those skilled in the art can design reference matrices of various sizes having excellent cycle characteristics, and the present invention uses various kinds of reference matrices and at least one matrix modified from the reference matrices. Encoding and decoding can be performed.

8B to 8G show an example in which the reference matrix of FIG. 8A is modified. As described above, the information word portion of the parity check matrix according to the present embodiment includes a specific reference matrix and at least one hybrid cyclic shift matrix obtained by converting the specific reference matrix.

Hereinafter, a method of generating the hybrid cyclic shift matrix will be described with reference to FIGS. 8B to 8G.

The matrix of FIG. 8B is an example of modifying the reference matrix of FIG. 8A. The matrix of FIG. 8A performs a cyclic shift by one in a downward direction with respect to the reference matrix of FIG. 8A. Since the matrix of FIG. 8B performs a cyclic shift with respect to the matrix of FIG. 8A, the relative positions of the rows are the same. Therefore, the cycle characteristic of FIG. 8A can be maintained in FIG. 8B. If the matrix of FIG. 8A is used in the region 701 of FIG. 7, the matrix of FIG. 8B may be used in the region 702 of FIG. 7. As a result, by using the information word portion including the matrix of FIG. 8A and the matrix of FIG. 8B, encoding and decoding supporting various code rates may be performed while maintaining excellent cycle characteristics.

The matrix of FIG. 8C is an example of modifying the reference matrix of FIG. 8A. The matrix of FIG. 8A is a matrix in which 3 cyclic shifts are performed in the downward direction with respect to the reference matrix of FIG. 8A. The hybrid cyclic shift matrix according to the present embodiment may be a matrix in which cyclic shifts of various sizes are performed with respect to the reference matrix. In addition, the matrices of FIGS. 8A-8C can be used together. For example, when the matrix of FIG. 8A is used for the region 701 of FIG. 7, the matrix of FIG. 8B may be used for the region 702 of FIG. 7, and the matrix of FIG. 8C may be used for the region 703 of FIG. 7. Since the matrix of FIG. 8A is composed of a 16 * 16 sub-matrix, a total of 15 cyclic shifts may be applied. Accordingly, the matrix of FIG. 8A may be modified into 15 types. By performing a cyclic shift of the reference matrix by 1, a hybrid cyclic shift matrix to be added later without additional information may be generated, but the order in which cyclic shifts may be determined may be set in advance.

The matrix of FIG. 8D is a matrix in which two cyclic shifts are performed in the left direction with respect to the matrix of FIG. 8A. According to the present embodiment, in order to perform a cyclic shift while maintaining the cycle characteristics of the reference matrix, it is preferable to perform a cyclic shift for each row. However, it is also possible to perform a cyclic shift on the column, as in the example of FIG. 8D.

The matrix of FIG. 8E is a matrix that performs two cyclic shifts in the left direction with respect to the matrix of FIG. 8C. That is, cyclic shifts for rows and columns may be performed at the same time.

The matrix of FIG. 8F is a matrix in which the order of the columns of the matrix of FIG. 8C is adjusted. That is, the order of the columns of the matrix of FIG. 8C can be adjusted as {3, 4, 1, 5, 2, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16}.

The matrix of FIG. 8G is an example of modifying the reference matrix of FIG. 8A. The matrix of FIG. 8G is a matrix in which up to three cyclic shifts are performed with respect to the reference matrix of FIG. 8A.

The matrixes of FIGS. 8B-8G can be used with the reference matrix of FIG. 8A. Since the matrixes of FIGS. 8B-8G modify FIG. 8A, the position of the weighted component in the matrix of FIGS. 8B-8G is determined according to the position of the weighted component in the matrix of FIG. 8A. For example, in the matrix of FIG. 8B, there is a weight in the positions of x'1 to x'48. The positions of x'1 to x'48 in FIG. 8B depend on the positions of x1 to x48 in FIG. 8A. Is determined. However, the index (ie, the number of shifts) corresponding to x'1 to x'48 may be different from x1 to x48. This is because the indices of x'1 to x'48 may have various values to improve cycle characteristics. In addition, in the present exemplary embodiment, the reference matrix is 16 * 16 square, but the example may be 16 * 8, and may have various shapes.

As described above, a general LDPC encoder or decoder includes a position memory and an index memory. In this case, when using the reference matrix and the modified matrix according to the present embodiment, it is possible to prevent the size of the location memory from being linearly increased. That is, if the position of the component having weight in the reference matrix and the information on how much cyclic shift the reference matrix is known, the position of the component having the weight of the rest of the matrix except the reference matrix Can be. Therefore, even if the size of the information word portion of the parity check matrix is increased, the size of the location memory can be fixed according to the reference matrix.

In the example of FIG. 7, a case of using one reference matrix has been described, but a plurality of reference matrices may be used. That is, at least one cyclically shifted specific second reference matrix B and B together with a specific first reference matrix A and at least one transformed matrix A ₁ , A ₂ , ..., A _n which cyclically shifted A. The transformed matrix of B ₁ , B ₂ , ..., B _n may be included in one information word part.

In this embodiment, since the parity check matrix is extended using a matrix obtained by shifting at least one of a row and a column, the cycle characteristic can be maintained. That is, excellent cycle characteristics can be maintained between the reference matrix and the matrixes obtained by converting the reference matrix. In addition, the cycle characteristics between the matrices can be prevented from being poorly distributed.

As described above, the parity check matrix proposed in this embodiment supports various code rates. By using the parity check matrix according to the present embodiment, communication with different code rates may be performed according to channel phase shift. An example thereof is as follows.

In situations where the channel is good, the system can transmit and receive high code rates to handle high speed data. However, when the channel condition worsens, it is desirable to lower the code rate to make the data processing stable. In other words, supporting various channel code rates for various channel situations is advantageous for stably processing high-speed data. The example of FIG. 7 supports code rates 1/3 to 5/6. An example of a method of supporting various code rates required by one mother matrix in a system requiring rate compatibility is as follows.

When the environment of the channel is good, the transmitting end according to the present embodiment performs encoding using a parity check matrix including the entire information word portion of FIG. 7. That is, encoding is performed at a high code rate of 5/6. The receiving end according to the present embodiment performs decoding by using the parity check matrix including the entire information word part of FIG. 7. Since the transmitting end and the receiving end may generate a matrix of regions 704, 703, and 702 of FIG. 7 by using information about a reference matrix, communication supporting various code rates may be performed through a small sized location memory.

When the environment of the channel becomes worse and requires a code rate of 4/5 lower than 5/6, the transmitter performs encoding at a code rate of 4/5 using an area except for 704 in the entire information word portion of FIG. . The receiving end also performs decoding using the area used by the transmitting end.

When the environment of the channel becomes worse and requires a code rate of 3/4 lower than 4/5, the transmitting end encodes at a code rate of 3/4 using an area excluding the areas 704 and 703 in the entire information word portion of FIG. Perform The receiving end also decodes using the area used by the transmitting end.

When the environment of the channel becomes worse and requires a code rate of 2/3 lower than 3/4, the transmitting end uses a code rate of 2/3 using an area excluding the areas 704, 703, and 702 in the entire information word portion of FIG. Perform encoding with. The receiving end also decodes using the area used by the transmitting end.

When the environment of the channel becomes worse and requires a code rate of 1/2 lower than 2/3, the transmitter uses 1/2 of the entire information word in FIG. 7 except for the areas 704, 703, 702, and 701. Encoding is performed at the code rate. The receiving end also decodes using the area used by the transmitting end.

When the environment of the channel becomes worse and requires a code rate of 1/3 lower than 1/2, the transmitting end uses 1/3 of the code rate in the entire information word part of FIG. Perform encoding at rate. The receiving end also decodes using the area used by the transmitting end.

When the channel environment improves again, encoding may be performed using a matrix corresponding to a high code rate. In this case, the receiving end also decodes using the area used by the transmitting end.

Since the above-described model matrix or parity check matrices are merely examples for describing the present invention, the present invention is not limited to the specific numerical values used in the above-described examples.

Those skilled in the art through the above description can be seen that various changes and modifications can be made without departing from the spirit of the present invention. Therefore, the technical scope of the present invention should not be limited to the contents described in the detailed description of the specification but should be defined by the claims.

Hereinafter, the effect of the present invention will be described.

The LDPC code utilizes a property in which the specific gravity of the weighted component is very thin in the parity check order. In the structured LDPC code, a parity check matrix that extends from a sub-matrix and a location memory for storing positions of weighted components rather than converting the sub-matrix into a binary matrix for encoding or decoding. Encoding and decoding are performed using a binary memory that stores index values of components with weights. An advantage of the present invention is that it is not necessary to increase the size of the location memory when expanding the high code rate. That is, the memory of the system can be reduced. Table 2 below describes the effects of the present invention in terms of location memory.

Code rate The present invention Prior art 2/3 3 * 16 3 * 16 3/4 0 3 * 16 4/5 0 3 * 16 5/6 0 3 * 16 6/7 0 3 * 16 7/8 0 3 * 16 8/9 0 3 * 16 9/10 0 3 * 16 10/11 0 3 * 16 11/12 0 3 * 16 12/13 0 3 * 16 13/14 0 3 * 16 14/15 0 3 * 16 15/16 0 3 * 16 16/17 0 3 * 16 17/18 0 3 * 16 Total memory 3 * 16 = 48 3 * 16 * 16 = 768

As shown in Table 2, the encoding and decoding method according to the present invention does not increase the location memory even if the inefficiency increases. When performing encoding and decoding supporting up to code rate 17/18, the method according to the present invention requires a memory size of 6.25% of the prior art.

The encoding and decoding method according to the present invention shows not only an effect of saving memory but also an excellent encoding performance.

9 is a diagram illustrating performance when encoding is performed using a parity check matrix according to the present embodiment. That is, the result of FIG. 9 is a performance curve when the LDPC code of the train structure is generated using the parity check matrix according to the present embodiment. As shown, it can be seen that as the size of the information word portion of the parity check matrix increases, coding gain, which is a characteristic of the LDPC code, can be obtained. That is, when encoding and decoding are performed using the parity check matrix according to the present invention, not only the memory size but also the excellent code can be designed.

Claims (10)

In the method of performing LDPC encoding using a model matrix including a specific information word portion and a parity portion, And wherein the information word portion includes at least one reference matrix and at least one transform matrix cyclically shifting the at least one reference matrix. The method of claim 1, The position of the weighted component included in the at least one transformation matrix is determined according to the position of the weighted component included in the reference matrix. LPDC coding method using a reference matrix. The method of claim 1, The at least one transform matrix is a matrix obtained by performing a cyclic shift on a row of the at least one reference matrix. LPDC coding method using a reference matrix. The method of claim 3, The at least one transformation matrix is a matrix obtained by performing a cyclic shift on a column of the at least one reference matrix. LPDC coding method using a reference matrix. The method of claim 3, The at least one transformation matrix is a matrix in which the order of the columns of the at least one reference matrix is adjusted. LPDC coding method using a reference matrix. The method of claim 1, The size of the information word portion is variable using a reference matrix, characterized in that LPDC coding method using a reference matrix. The method of claim 6, The number of transform matrices included in the information word portion is determined according to a code rate. LPDC coding method using a reference matrix. The method of claim 1, The reference matrix is designed based on a cycle characteristic LPDC coding method using a reference matrix. In the method of performing LDPC encoding using a parity check matrix including a specific information word portion and a parity portion, Performing encoding on information bits of a specific size by using a parity check matrix generated by extending from a model matrix corresponding to a specific first code rate; Transmitting the encoded codeword; Performing encoding on information bits of a specific size by using a parity check matrix generated by extending from a model matrix corresponding to a specific second code rate; And Transmitting the encoded codeword Including but not limited to, The information word portion of the model matrix corresponding to the first code rate and the second code rate includes at least one reference matrix and at least one transform matrix for performing a cyclic shift on the reference matrix. LPDC coding method using a reference matrix. In the method of performing LDPC decoding using a parity check matrix including a specific information word portion and a parity portion, Receiving an LDPC coded codeword; And Decoding the codeword using a parity check matrix generated from a model matrix consisting of subblocks having a specific size; Including but not limited to, The information word portion of the model matrix includes at least one reference matrix and at least one transform matrix that performs a cyclic shift on the reference matrix. LPDC decoding method using reference matrix.

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