KR20070115311A - Memory devices having nano-cell structure and methods of fabrication the same - Google Patents

Abstract

A memory device having a nano cell structure and a manufacturing method thereof are provided to compose a semiconductor nano structure and an information storing nano structure by using nano wires, so that a size of the nano cell structure is minimized. A nano cell structure(16) consists of a semiconductor nano structure(10) and an information storing nano cell structure(15). The information storing nano structure is connected to the one end of the semiconductor nano structure, to be self-aligned with the semiconductor nano structure. The semiconductor nano structure is composed by a first nano wire and a second semiconductor nano wire which have a different conduction type.

Description

Memory devices having nano-cell structure and methods of fabrication the same

1 is a perspective view showing a nano cell structure according to an embodiment of the present invention.

2 is a perspective view showing a nano cell structure according to another embodiment of the present invention.

3 is a plan view illustrating a memory device according to still another embodiment of the present invention.

4A-4D are cross-sectional views taken along the line II ′ of FIG. 3.

5 is a plan view illustrating a memory device according to still another embodiment of the present invention.

6A through 6C are cross-sectional views taken along the line II-II 'of FIG. 5.

The present invention relates to a semiconductor device and a method of manufacturing the same, and more particularly to a memory device having a nano-cell structure and a method of manufacturing the same.

Nonvolatile memory devices have a feature that data stored therein is not destroyed even if their power is cut off. Among these nonvolatile memory devices, phase change memory devices have been proposed. The unit cell of the phase change memory elements includes one cell switching element and a phase change material layer connected to the switching element. The unit cells of the phase change memory devices have upper and lower electrodes connected to upper and lower portions of the phase change material layer, respectively. The switching element may be a MOS transistor or a diode formed using a conventional photo and etching process.

Recently, a phase change memory device using a vertical diode formed of semiconductor nanowires as a switching device has been described in US Patent Application Publication No. 2006/0034116 A1 "cross point array cell having a semiconductor diode and a phase change storage medium connected in series. series connected semiconductor diode and phase change storage media}, as described by Lam et al. According to the present invention, each storage cell includes a storage medium and a diode connected in series, and the storage medium is formed between the lower electrode and the upper electrode. Here, the diode is a vertical diode formed of semiconductor nanowires. By the way, in the memory element formed by RAM or the like, the phase change material film used as the information storage element is formed using a conventional photographic and etching process. As described above, there is a limit in reducing the area occupied by the phase change material film formed by using a conventional photographic and etching process.

In addition, as the recent trend toward higher integration of memory devices, as the contact area between the heater and the phase change material film, which serves as a heat source capable of phase shifting the phase change material film, becomes smaller in grain size, Cell scattering characteristics of the memory device may be degraded. That is, since the heating element of the phase change memory device is generally made of a polycrystalline metal material, the cell scattering characteristics may deteriorate as the contact area between the heater and the phase change material layer decreases.

Therefore, there is a need for a new device structure and a new device manufacturing method capable of suppressing such deterioration of cell scattering characteristics and realizing high integration.

An object of the present invention is to provide a nano cell structure and a method of manufacturing the same.

Another object of the present invention is to provide a memory device having the nano-cell structure and a method of manufacturing the same.

According to one aspect of the present invention, a nano cell structure is provided. The nano cell structure includes a semiconductor nano structure and an information storage nano structure connected to one end of the semiconductor nano structure to self-align with the semiconductor nano structure.

In some embodiments of the present invention, the semiconductor nanostructure may be formed of a first semiconductor nanowire connected in turn and a second semiconductor nanowire having a different conductivity type from the first semiconductor nanowire.

The semiconductor device may further include a gate pattern surrounding the second semiconductor nanostructure.

The semiconductor device may further include a third semiconductor nanostructure interposed between the second semiconductor nanostructure and the information storage nanostructure. Here, the third semiconductor nanostructure may have the same conductivity type as the first semiconductor nanostructure.

In another embodiment, the information storage nanostructure may be made of a phase change nanowire including a Ge element and a Te element.

In another embodiment, further comprising a buffer nanostructure interposed between the semiconductor nanowire and the information storage nanostructure, the buffer nanostructure may be a conductive nanowire.

In another embodiment, the semiconductor device may further include a conductive structure positioned opposite to the semiconductor nanostructure with the information storage nanostructure interposed therebetween and connected to one end of the information storage nanostructure to self-align with the information storage nanostructure. The conductive structure may be made of conductive nanowires.

According to another aspect of the present invention, a memory element is provided. The device includes a lower conductive pattern provided on the substrate. An insulating film is provided on the substrate having the lower conductive pattern. An upper conductive pattern having a directionality intersecting with the lower conductive pattern is provided on the insulating layer. And a nanostructure positioned in an area where the lower conductive pattern and the upper conductive pattern cross each other and penetrating the insulating layer, wherein the nanostructure is self-aligned with the semiconductor nanostructure and the semiconductor nanostructure in contact with the lower conductive pattern. It consists of linked information storage nanostructures.

In some embodiments of the present disclosure, the semiconductor nanostructure may include a first semiconductor nanowire sequentially connected and a second semiconductor nanowire having a different conductivity type from the first semiconductor nanowire.

Furthermore, the semiconductor device may further include a third semiconductor nanostructure interposed between the information storage nanostructure and the second semiconductor nanowire. Here, the third semiconductor nanostructure may be made of a semiconductor nanowire having the same conductivity type as the first semiconductor nanowire.

In addition, the insulating layer may further include a conductive line parallel to the lower conductive pattern. The conductive line may be provided to overlap the lower conductive pattern and surround the second semiconductor nanowire.

The gate dielectric layer may further include a gate dielectric layer interposed between the conductive line and the second semiconductor nanowire.

In another embodiment, the information storage nanostructure may be formed of a phase change nanowire including a Ge element and a Te element.

In another embodiment, further comprising a conductive structure interposed between the information storage nanostructure and the upper conductive pattern, the conductive structure may be made of a conductive nanowire.

In another embodiment, the semiconductor nanostructure further comprises a buffer nanostructure interposed between the information storage nanostructure, the buffer nanostructure may be made of a conductive nanowire.

According to another aspect of the present invention, a method for producing a Nassau cell is provided. The method includes forming a catalyst layer, forming a semiconductor nanostructure grown from the catalyst layer, and forming an information storage nanostructure grown from the semiconductor nanostructure.

In some embodiments of the present disclosure, the semiconductor nanostructure is formed of a first semiconductor nanowire growing from the catalyst layer and a second semiconductor nanowire growing from the first semiconductor nanowire, wherein the second semiconductor nanowire is The first semiconductor nanowire may have a different conductivity type.

The method may further include forming a third semiconductor nanowire growing from the second semiconductor nanowire after forming the second semiconductor nanowire, wherein the third semiconductor nanowire is the same as the first semiconductor nanowire. It may have a conductivity type.

In addition, after the forming of the second semiconductor nanowire, further comprising forming a buffer nanostructure growing from the second semiconductor nanowire, the buffer nanostructure may be formed of a conductive nanowire.

In another embodiment, the method may further include forming a conductive structure that grows from the information storage nanostructure, wherein the conductive structure may be formed of conductive nanowires.

In another embodiment, the information storage nanostructure may be formed of a phase change nanowire including a Ge element and a Te element.

According to still another aspect of the present invention, a method of manufacturing a memory device is provided. The method includes forming a lower conductive pattern on the substrate. Lower and upper insulating layers are sequentially formed on the substrate having the lower conductive pattern. The lower and upper insulating layers are patterned to form holes for exposing predetermined regions of the lower conductive pattern. A semiconductor nanostructure growing through the predetermined region of the exposed lower conductive pattern as a catalyst layer and an information storage nanostructure growing from the semiconductor nanostructure are formed in the hole. A conductive structure growing from the information storage nanostructure is formed. An upper conductive pattern covering the hole and electrically connected to the conductive structure is formed on the upper insulating layer.

In some embodiments of the present invention, the semiconductor nanostructure and the information storage nanostructure are formed of nanowires, wherein the semiconductor nanostructure is a first semiconductor nanowire and the first semiconductor nanowire growing from the lower conductive pattern. The semiconductor nanowire may be formed of a second semiconductor nanowire having a conductivity type different from that of the first semiconductor nanowire, and the information storage nanostructure may be formed of a phase change nanowire including a Ge element and a Te element.

Furthermore, after forming the lower insulating film, further comprising forming a conductive line on the lower interlayer insulating film, wherein the conductive line has a width larger than the diameter of the hole and is substantially the same level as the second semiconductor nanowire. And may be patterned together while patterning the lower and upper insulating layers.

In another embodiment, the conductive structure may be formed of conductive nanowires.

In another embodiment, after forming the conductive structure, the method may further include forming a dielectric film surrounding the semiconductor nanostructure.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. However, the present invention is not limited to the embodiments described herein and may be embodied in other forms. Rather, the embodiments introduced herein are provided to ensure that the disclosed subject matter is thorough and complete, and that the scope of the invention to those skilled in the art will fully convey. In the drawings, the thicknesses of layers and regions are exaggerated for clarity. Like numbers refer to like elements throughout.

1 is a perspective view showing a nano cell structure according to an embodiment of the present invention, Figure 2 is a perspective view showing a nano cell structure according to another embodiment of the present invention, Figure 3 according to another embodiment of the present invention 4A through 4D are cross-sectional views taken along the line II ′ of FIG. 3, FIG. 5 is a plan view illustrating a memory device according to still another embodiment of the present invention, and FIGS. 5 are cross-sectional views taken along the line II-II 'of FIG.

First, a nanocell structure according to an embodiment of the present invention will be described with reference to FIG. 1.

Referring to FIG. 1, a nano-structure 16 is provided. The nanostructure 16 may include a semiconductor nanostructure 10 and a data storage nanostructure 15 that are sequentially connected. The information storage nanostructure 15 may be connected to one end of the semiconductor nanostructure 10 so as to self-align with the semiconductor nanostructure 10. The semiconductor nanostructure 10 may be made of semiconductor nanowires having semiconductor characteristics, and the information storage nanostructure 15 may be made of phase-change nanowires having phase shift characteristics. For example, the semiconductor nanowires may be Si nanowires, Ge nanowires, GaAs nanowires, or InSb nanowires, and the phase change nanowires include Ge (germanium) elements and Te (tellurium) elements. It may be a GeTe nanowire.

The semiconductor nanostructure 10 may include a first semiconductor nanostructure 6 and a second semiconductor nanostructure 9 that are sequentially connected. The first semiconductor nanostructure 6 may be formed of a semiconductor nanowire having a first conductivity type, and the second semiconductor nanostructure 9 may be a semiconductor nanowire having a second conductivity type different from the first conductivity type. It may be made of. For example, the first semiconductor nanostructure 6 may be formed of Si nanowires having a first conductivity type, and the second semiconductor nanostructure 9 may have a second conductivity type different from the first conductivity type. It may be made of Si nanowires having. The first conductivity type may be n-type or p-type. For example, when the first conductivity type is n-type, the second conductivity type may be p-type. Therefore, the semiconductor nanostructure 10 including the first semiconductor nanostructure 6 and the second semiconductor nanostructure 9 may be defined as a diode.

A lower conductive pattern 3 may be provided opposite to the information storage nanostructure 15 with the semiconductor nanostructure 10 interposed therebetween. The lower conductive pattern 3 and the semiconductor nanostructure 10 may be electrically connected to each other. The surface of the lower conductive pattern 3 in contact with the semiconductor nanostructure 10 may include a catalyst layer. For example, the catalyst layer may include a nickel layer, a cobalt layer, an iron layer, a yttrium layer, a lanthanum layer, or a platinum layer. Can be.

A conductive structure 18 may be provided opposite to the semiconductor nanostructure 10 with the information storage nanostructure 15 interposed therebetween. The conductive structure 18 may be made of a conductive material electrically connected to the information storage nanostructure 15. For example, the conductive structure 18 may be made of conductive nanowires such as NiSi nanowires.

Meanwhile, a buffer nano-structure 12 interposed between the second semiconductor nanostructure 9 and the information storage nanostructure 15 may be provided. The buffer nanostructure 12 may be made of conductive nanowires such as NiSi nanowires. The buffer nanostructure 12 may improve electrical characteristics between the second semiconductor nanostructure 9 and the information storage nanostructure 15.

Accordingly, a nano cell structure including the components as described above with reference to FIG. 1 may be provided. The nano cell structure may be a phase change memory cell structure. In other words, the semiconductor nanostructure 10 serves as a diode, the lower conductive pattern 3 serves as a word line, the conductive structure 18 substantially serves as a bit line, and the information storage nanostructure. 15 may serve as an information storage medium having a phase change characteristic according to a current change.

Next, a nano cell structure according to other embodiments of the present invention will be described with reference to FIG. 2.

Referring to FIG. 2, a nanostructure 61 is provided. The nanostructure 61 may include a semiconductor nanostructure 58 and an information storage nanostructure 60 that are sequentially connected. The information storage nanostructure 60 may be connected to one end of the semiconductor nanostructure 58 so as to self-align with the semiconductor nanostructure 58. The semiconductor nanostructure 58 may be formed of semiconductor nanowires having semiconductor characteristics, and the information storage nanostructure 60 may be formed of phase-change nanowires having phase shift characteristics. For example, the semiconductor nanowires may be Si nanowires, Ge nanowires, GaAs nanowires, or InSb nanowires, and the phase change nanowires may be GeTe nanowires including Ge and Te elements.

The semiconductor nanostructure 58 may include a first semiconductor nanostructure 53 and a second semiconductor nanostructure 55 that are sequentially connected. In this case, the second semiconductor nanostructure 55 may have a different conductivity type from the first semiconductor nanostructure 53. For example, when the first semiconductor nanostructure 53 is n-type, the second semiconductor nanostructure 55 may be p-type.

A gate pattern 68 may be provided surrounding the second semiconductor nanostructure 55. The gate pattern 68 may include a gate dielectric layer 65 and a gate electrode 67 that sequentially surround the second semiconductor nanostructure 55. The gate dielectric layer 65 may be formed of a high-k dielectric layer. The gate electrode 67 may be formed of a conductive film such as a polysilicon film.

A lower conductive pattern 51 may be provided opposite to the second semiconductor nanostructure 55 with the first semiconductor nanostructure 53 interposed therebetween. The lower conductive pattern 51 and the first semiconductor nanostructure 53 may be electrically connected to each other. The surface of the lower conductive pattern 51 in contact with the first semiconductor nanostructure 53 may include a catalyst layer. For example, the catalyst layer may include a nickel layer, a cobalt layer, an iron layer, a yttrium layer, a lanthanum layer, or a platinum layer. Can be.

A conductive structure 63 may be provided opposite to the semiconductor nanostructure 58 with the information storage nanostructure 60 interposed therebetween. The conductive structure 63 may be made of a conductive material that can be electrically connected to the information storage nanostructure 60. For example, the conductive structure 63 may be made of conductive nanowires such as NiSi nanowires.

The third semiconductor nanostructure 57 may be provided between the second semiconductor nanostructure 55 and the information storage nanostructure 60. The third semiconductor nanostructure 57 may have the same conductivity type as the first semiconductor nanostructure 53.

Accordingly, a nano cell structure including the components as described above with reference to FIG. 2 may be provided. That is, the nano cell structure may be a phase change memory cell structure. In detail, the first semiconductor nanostructure 53 and the conductive structure 63 may be defined as a source and a drain, respectively, and the second semiconductor nanostructure 55 may be defined as a channel region. have. Accordingly, the first semiconductor nanostructure 53, the second semiconductor nanostructure 55, the conductive structure 63, and the gate pattern 68 may constitute a transistor. Here, the gate electrode 67 constituting the gate pattern 68 serves as a word line, the conductive structure 63 substantially serves as a bit line, and the information storage nanostructure 60 is in response to a current change. It can serve as an information storage medium having the phase change characteristics according to.

Hereinafter, memory devices adopting the nano cell structures as described above will be described.

First, a memory device according to an exemplary embodiment of the present invention will be described with reference to FIGS. 3 and 4D.

3 and 4D, a plurality of lower conductive patterns 106 parallel to each other may be provided on the substrate 100. Each of the lower conductive patterns 106 may include a lower conductive layer 103 and a catalyst layer 105 which are sequentially stacked. The catalyst layer 105 may include a nickel layer (Ni layer), a cobalt layer (Co layer), an iron layer (Fe layer), yttrium layer (Y layer), a lanthanum layer (La layer) or a platinum layer (Pt layer). have.

An interlayer insulating layer 109 may be provided on the substrate having the lower conductive patterns 106. A plurality of parallel upper conductive patterns 130 may be provided on the interlayer insulating layer 109 to have a direction crossing the lower conductive patterns 106.

Nanostructures 122 are provided at intersecting regions between the upper conductive patterns 130 and the lower conductive patterns 106 and penetrate the interlayer insulating layer 109. Each of the nanostructures 122 may include a semiconductor nanostructure 119 and an information storage nanostructure 121 that are sequentially connected to the lower conductive patterns 106. The information storage nanostructure 121 may be connected to one end of the semiconductor nanostructure 119 to self-align with the semiconductor nanostructure 119. The semiconductor nanostructure 119 may be formed of semiconductor nanowires having semiconductor characteristics, and the information storage nanostructure 121 may be formed of phase-change nanowires having phase shift characteristics. For example, the semiconductor nanowires may be Si nanowires, Ge nanowires, GaAs nanowires, or InSb nanowires, and the phase change nanowires may be GeTe nanowires including Ge and Te elements.

Hereinafter, for convenience of description, a structure in a region where one lower conductive pattern and one upper conductive pattern intersect will be described. Here, a region where one lower conductive pattern and one upper conductive pattern cross each other may be defined as a cell region.

The semiconductor nanostructure 119 may include a first semiconductor nanostructure 115 and a second semiconductor nanostructure 118 that are sequentially connected. The second semiconductor nanostructure 118 may have a different conductivity type from the first semiconductor nanostructure 115. For example, the first semiconductor nanostructure 115 may be formed of silicon nanowires of a first conductivity type, and the second semiconductor nanostructure 118 may be silicon nanowires of a second conductivity type different from the first conductivity type. It may be made of wire. Therefore, the semiconductor nanostructure 119 may constitute a vertical diode.

A conductive structure 124 interposed between the information storage nanostructure 121 and the upper conductive pattern 130 may be provided. In this case, the conductive structure 124 is on an extension line of the nanostructure 122 and may include metallic nanowires. For example, the conductive structure 124 may include NiSi nanowires.

The conductive structure 124 may extend into the upper conductive pattern 130. Therefore, electrical characteristics between the conductive structure 124 and the upper conductive pattern 130 may be improved.

Meanwhile, the buffer nanostructure 120 interposed between the second semiconductor nanostructure 118 and the information storage nanostructure 121 may be provided. The buffer nanostructure 120 may be made of conductive nanowires such as NiSi nanowires to improve electrical characteristics between the second semiconductor nanostructure 118 and the information storage nanostructure 121.

Regions in which the lower conductive patterns 106 and the upper conductive patterns 130 intersect may be defined as cell regions. In addition, the lower conductive patterns 106 may serve as a word line, the upper conductive patterns 130 may serve as a bit line, and the semiconductor nanostructure 119 may serve as a diode.

Next, a memory device according to another exemplary embodiment of the present invention will be described with reference to FIGS. 5 and 6C.

5 and 6C, a plurality of lower conductive patterns 206 parallel to each other may be provided on the substrate 200. Each of the lower conductive patterns 206 may include a lower conductive layer 203 and a catalyst layer 205 that are sequentially stacked. The catalyst layer 205 may include a nickel layer (Ni layer), a cobalt layer (Co layer), an iron layer (Fe layer), yttrium layer (Y layer), a lanthanum layer (La layer) or a platinum layer (Pt layer). have.

The lower insulating layer 209 may be provided on the substrate having the lower conductive patterns 206. Conductive lines 212 substantially overlapping the lower conductive patterns 206 may be provided on the lower insulating layer 209. The conductive lines 212 may include a polysilicon layer. An upper insulating layer 215 may be provided on the substrate having the conductive lines 212.

A plurality of parallel upper conductive patterns 236 may be provided on the upper insulating layer 215 to cross the conductive lines 212.

Located in intersection regions between the upper conductive patterns 236 and the lower conductive patterns 206, and sequentially pass through the upper insulating layer 215, the conductive lines 212, and the lower insulating layer 209. Nanostructures 228 are provided. Each of the nanostructures 228 may include a semiconductor nanostructure 226 and an information storage nanostructure 227 that are sequentially connected from the lower conductive patterns 206.

The information storage nanostructure 227 may be connected to one end of the semiconductor nanostructure 226 to self-align with the semiconductor nanostructure 226. The semiconductor nanostructure 226 may be formed of semiconductor nanowires having semiconductor characteristics, and the information storage nanostructure 227 may be formed of phase-change nanowires having phase shift characteristics. For example, the semiconductor nanowires may be Si nanowires, Ge nanowires, GaAs nanowires, or InSb nanowires, and the phase change nanowires may be GeTe nanowires including Ge and Te elements. Hereinafter, for convenience of description, a structure in a region where one lower conductive pattern and one upper conductive pattern intersect will be described. Here, a region where one lower conductive pattern and one upper conductive pattern cross each other may be defined as a cell region.

The semiconductor nanostructure 226 may include a first semiconductor nanostructure 221 and a second semiconductor nanostructure 223 that are sequentially connected. The second semiconductor nanostructure 223 may have a different conductivity type than the first semiconductor nanostructure.

The second semiconductor nanostructure 223 may be surrounded by the conductive line 212. That is, the conductive line 212 and the second semiconductor nanostructure 223 may be positioned at substantially the same level. A gate dielectric layer 233 may be provided between the conductive line 212 and the second semiconductor nanostructure 223. The gate dielectric layer 233 may be formed of a high dielectric layer.

Meanwhile, the third semiconductor nanostructure 225 may be provided between the second semiconductor nanostructure 223 and the information storage nanostructure 227. The third semiconductor nanostructure 225 may have the same conductivity type as the first semiconductor nanostructure 53.

The conductive structure 230 interposed between the information storage nanostructure 227 and the upper conductive pattern 236 may be provided. Here, the conductive structure 230 is on the extension line of the nanostructure 228, may include a metallic nanowire. For example, the conductive structure 230 may include NiSi nanowires. The conductive structure 230 may extend into the upper conductive pattern 236. Therefore, electrical characteristics between the conductive structure 230 and the upper conductive pattern 236 may be improved.

In the present invention, the first semiconductor nanostructure 221 and the conductive structure 230 is defined as a source (source) and drain (drain), respectively, and the second semiconductor nanostructure 223 is defined as a channel region The conductive line 212 is defined as a word line, the upper conductive pattern 236 is defined as a bit line, the lower conductive pattern 206 is defined as a ground line, and the data storage nano The structure 121 may be defined as an information storage medium having a phase change characteristic according to a current change. It is possible to provide a phase shift memory device composed of such components.

The operation principle of the phase change memory device is as follows. The phase change memory device may include a plurality of memory cell regions positioned at crossing regions of the upper conductive patterns 236 and the lower conductive patterns 206. First, the transistor is turned on by applying a voltage greater than a threshold voltage to the word line 212 of the selected memory cell region, and a writing current through the bit line 236 of the selected memory cell region. ; Force) Iw). Most of the bit line voltage applied to the bit line 236 is applied to the information storage nanostructure 227. The reason is that since the transistor of the selected cell region is turned on, the resistance of the second semiconductor nanostructure 223, that is, the channel region, is lower than that of the information storage nanostructure 227. Therefore, a write current Iw may be applied to the information storage nanostructure 227.

The electrical resistance of the information storage nanostructure 227 having the phase change characteristic may vary according to the amount of the write current Iw. For example, the data storage nanostructure 227 is heated by the write current Iw to a temperature between its crystallization temperature and the melting point and the heated information storage nanostructure 227 Is cooled, the data storage nanostructure 227 is transformed into a crystalline state. On the contrary, when the information storage nanostructure 227 is heated to a temperature higher than the melting point by the write current Iw and the molten information storage nanostructure 227 is quenched, the information storage nanostructure ( 227 changes to an amorphous state. The specific resistance of the information storage nanostructure 227 having the crystalline state is lower than that of the information storage nanostructure 227 having the amorphous state. Accordingly, by detecting current flowing through the information storage nanostructure 227 in a read mode, it is possible to determine whether the information stored in the information storage nanostructure 227 is a logic "1" or a logic "0". Can be.

On the other hand, in the unselected cell region among the plurality of cell regions, OV is applied to the word line 212 of the unselected cell region or OV is applied to the bit line 236 of the unselected cell region in order to turn off the transistor. Can be. Therefore, since no current flows in the information storage nanostructure 227 of the non-selected cell region, no phase shift due to the current occurs.

Hereinafter, methods of fabricating memory devices employing nano cell structures according to embodiments of the present invention will be described.

First, a method of manufacturing a memory device according to an exemplary embodiment of the present invention will be described with reference to FIGS. 3 and 4A to 4E.

3 and 4A, a substrate 100 is prepared. The substrate 100 may be a semiconductor substrate having an insulated surface. A plurality of lower conductive patterns 106 parallel to each other may be formed on the substrate 100. Each of the lower conductive patterns 106 may be formed of a lower conductive layer 103 and a catalyst layer 105 which are sequentially stacked. For example, the catalyst layer 105 may include a nickel layer, a cobalt layer, a iron layer, a yttrium layer, a lanthanum layer, or a platinum layer. It may include.

An interlayer insulating layer 109 may be formed on the substrate having the lower conductive patterns 106. The interlayer insulating film 109 may be formed of an insulating film such as a silicon oxide film. The interlayer insulating layer 109 may be patterned to form holes 112 exposing predetermined regions of the catalyst layers 105.

3 and 4B, nanostructures 122 may be formed in the holes 112. That is, one or more nanostructures 122 may be formed in each of the holes 122. Each of the nanostructures 122 may include a semiconductor nanostructure 119 growing from the catalyst layer 105 and an information storage nanostructure 121 growing from the semiconductor nanostructure 119.

The semiconductor nanostructure 119 may be formed using a vapor phase-liquid pahse-solid phase (VLS) process. The semiconductor nanostructure 119 may be formed of semiconductor nanowires having semiconductor characteristics. For example, the semiconductor nanowires may be formed of Si nanowires, Ge nanowires, GaAs nanowires, or InSb nanowires.

When the semiconductor nanostructure 119 is formed of Si nanowires, the Si nanowires may be formed by performing a VLS process using a gas containing a silicon element to expose the catalyst layers exposed by the holes 112 ( Growing Si nanowires from certain regions of 105. In this case, the VLS process may be performed in a reactor. In the present invention, the semiconductor nanostructure 119 is not limited to being formed by the VLS process. That is, various known methods may be used to form the semiconductor nanostructure 119.

The semiconductor nanostructure 119 may be formed of a first semiconductor nanostructure 115 and a second semiconductor nanostructure 118 having a conductivity type different from that of the first semiconductor nanostructure. That is, the first semiconductor nanostructure 115 may be formed of a semiconductor nanowire having a first conductivity type, and the second semiconductor nanostructure 118 may be formed of a semiconductor nanowire having a second conductivity type. have. The first conductivity type may be n-type or p-type. Thus, the semiconductor nanostructure 119 may form a vertical diode.

The information storage nanostructure 121 may be formed of a phase change nanowire having phase change characteristics. For example, the information storage nanostructure 121 may be formed of GeTe nanowires including Ge and Te elements. The information storage nanostructure 121 may be formed by growing from the semiconductor nanostructure 119. For example, the semiconductor nanostructure 119 is grown from the catalyst layer 105 by performing a VLS process using a gas containing a silicon element, and thereafter, a first element including a Ge element instead of a gas containing a silicon element. Nanowires including Ge and Te elements may be grown using a VLS process using a second gas containing gas and Te elements. That is, the semiconductor nanoline 119 and the information storage nanostructure 121 may be grown in order by sequentially changing the gas atmosphere in the reactor. For example, the VLS process may be performed by growing the semiconductor nanostructure 119, that is, the Si nanowire, using the gas atmosphere in the reactor as the gas atmosphere containing silicon, and the gas atmosphere in the reactor as the Ge element. It may include growing a GeTe nanowire including a Ge element and a Te element by sequentially changing the first gas and a second gas containing a Te element. Therefore, the information storage nanostructure 121 may be formed to be self-aligned in a direction perpendicular to the semiconductor nanostructure 119.

Meanwhile, after the semiconductor nanostructure 119 is formed, before the information storage nanostructure 121 is formed, the buffer nanostructure 120 grown from the semiconductor nanostructure 119 may be formed. For example, a buffer nanostructure 120 made of conductive nanowires such as NiSi nanowires is grown from the semiconductor nanostructures 119 using a VLS process, and subsequently, information storage nanostructures 121 are formed from the NiSi nanowires. ) Can grow.

The conductive structure 124 grown from the information storage nanostructure 121 may be formed. The conductive structure 124 may be formed of conductive nanowires such as NiSi nanowires. An end portion of the conductive structure 124 may be positioned at substantially the same level as the surface of the interlayer insulating layer 109 or at a level higher than the surface of the interlayer insulating layer 109.

3 and 4C, a buffer insulating layer 127 may be formed to fill a space between the nanostructure 122 and sidewalls of the holes 112. In detail, the forming of the buffer insulating layer 127 may include forming a conformal insulating layer on the substrate having the conductive structure 124 and etching the conformal insulating layer. As a result, a portion of the conductive structure 122 may be exposed.

3 and 4D, a plurality of upper conductive patterns 130 parallel to each other may be formed on a substrate having the buffer insulating layer 127. Here, the upper conductive patterns 130 may have a direction crossing the lower conductive patterns 106 and may be formed to cover the exposed conductive structure 124. As a result, the upper conductive patterns 130 may be electrically connected to the conductive structure 124.

As described above, while forming a vertical diode made of a semiconductor nanostructure, it is possible to form an information storage nanostructure self-aligned in the vertical direction with the vertical diode. Here, since the semiconductor nanostructure and the information storage nanostructure are formed of nanowires, a memory device having a highly integrated cell may be implemented, and the information storage nanostructure is formed by growing from the semiconductor nanostructure, In addition to minimizing the area occupied by the data storage nanostructures, cell scattering characteristics can be improved.

Next, a method of manufacturing a memory device according to another exemplary embodiment of the present invention will be described with reference to FIGS. 5 and 6A to 6C.

5 and 6A, the substrate 200 is prepared. The substrate 200 may be a semiconductor substrate having an insulated surface. A plurality of lower conductive patterns 206 parallel to each other may be formed on the substrate 200. Each of the lower conductive patterns 206 may be formed of a lower conductive layer 203 and a catalyst layer 205 that are sequentially stacked. For example, the catalyst layer 205 may include a nickel layer, a cobalt layer, an iron layer, a yttrium layer, a lanthanum layer, or a platinum layer. It may include.

The lower insulating layer 209 may be formed on the substrate having the lower conductive patterns 206. The lower insulating film 209 may be formed of an insulating film such as a silicon oxide film. A plurality of parallel conductive lines 212 may be formed on the lower insulating layer 209. The conductive lines 212 may include polysilicon layers. The conductive lines 212 may be formed to overlap the lower conductive patterns 206. An upper insulating layer 215 may be formed on the substrate having the conductive lines 212. The upper insulating film 215 may be formed of an insulating film such as a silicon oxide film.

The upper insulating layer 215, the gate lines 212, and the lower insulating layer 209 may be patterned in order to form holes 218 exposing predetermined regions of the catalyst layer 205. Here, the diameter of each of the holes 218 may be smaller than the width of each of the conductive lines 212.

5 and 6B, nanostructures 228 are formed in the holes 218. That is, one or more nanostructures 228 may be formed in the holes 228. Each of the nanostructures 228 may include a semiconductor nanostructure 226 growing from the catalyst layer 205 and an information storage nanostructure 227 growing from the semiconductor nanostructure 226. The semiconductor nanostructure 226 may be formed of semiconductor nanowires having semiconductor characteristics. For example, the semiconductor nanowires may be formed of Si nanowires, Ge nanowires, GaAs nanowires, or InSb nanowires.

When the semiconductor nanostructure 226 is formed of Si nanowires, the Si nanowires may be formed by performing a VLS process using a gas containing a silicon element to expose the catalyst layers exposed by the holes 228. Growing Si nanowires from certain regions of 205. In this case, the VLS process may be performed in a reactor. However, the formation of the semiconductor nanostructure 226 is not limited to the VLS process. That is, various known methods may be used to form the semiconductor nanostructure 226.

 The semiconductor nanostructure 226 may be formed of a first semiconductor nanostructure 221 connected in turn and a second semiconductor nanostructure 223 having a different conductivity type from the first semiconductor nanostructure 221. The first semiconductor nanostructure 221 may be formed of a semiconductor nanowire having a first conductivity type, and the second semiconductor nanostructure 223 may be formed of a semiconductor nanowire having a second conductivity type. The first conductivity type may be n-type or p-type. Here, the dopant concentration of the first semiconductor nanostructure 221 may be higher than the dopant concentration of the second semiconductor nanostructure 223.

The information storage nanostructure 227 may be formed of a phase change nanowire having phase change characteristics. For example, the information storage nanostructure 227 may be formed of GeTe nanowires including Ge and Te elements. The information storage nanostructure 227 may be formed by growing from the semiconductor nanostructure 226. For example, a VLS process using a gas containing a silicon element may be performed to grow the semiconductor nanostructure 226 such as Si nanowires from the catalyst layer 205, and then Ge element instead of a gas containing silicon element. The VLS process using the first gas including the second gas and the second gas including the Te element may be performed to grow GeTe nanowires including the Ge element and the Te element. That is, the semiconductor nanostructure 226 and the information storage nanostructure 227 may be sequentially formed by sequentially changing the gas atmosphere in the reactor. For example, the VLS process may be performed by growing the semiconductor nanostructure 226, that is, the Si nanowire, using the gas atmosphere in the reactor as a gas atmosphere containing silicon, and the gas atmosphere in the reactor as a Ge element. It may include growing a GeTe nanowire including a Ge element and a Te element by sequentially changing the first gas and a second gas containing a Te element.

The conductive structure 230 grown from the information storage nanostructure 227 may be formed. The conductive structure 230 may be formed of conductive nanowires such as NiSi nano wires.

5 and 6C, gate dielectric layers 233 may be formed to cover the surfaces of the nanostructures 228. In addition, the gate dielectric layers 233 may be formed to fill a space between sidewalls of the nanostructures 228 and the holes 218. For example, a conformal dielectric layer may be formed on the substrate having the conductive structures 230 by atomic layer deposition (ALD). The dielectric layer may be formed to fill a space between sidewalls of the nanostructures 228 and the holes 218. Subsequently, the dielectric layer may be etched to expose a portion of the conductive structures 230. As a result, the gate dielectric layers 233 may be formed.

A plurality of upper conductive patterns 236 parallel to each other may be formed on the substrate having the gate dielectric layers 233. The upper conductive patterns 236 may have a direction crossing the conductive lines 212 and may be arranged to cover the exposed conductive structures 230. As a result, the upper conductive patterns 236 may be electrically connected to the conductive structures 230.

As described above, according to the present invention, a memory device having a nano cell structure is provided. In the present invention, the nano cell structure may include a semiconductor nanostructure and an information storage nanostructure grown from the semiconductor nanostructure. The information storage nanostructure may be formed of nanowires growing from the semiconductor nanostructure. That is, since the semiconductor nanostructure and the information storage nanostructure are made of nanowires, the area occupied by the memory cell in the memory device may be minimized, and the cell scattering characteristics may be improved.

Claims (26)

Semiconductor nanostructures; And And an information storage nanostructure connected to one end of the semiconductor nanostructure to self-align with the semiconductor nanostructure. The method of claim 1, The semiconductor nanostructure is a nano cell structure, characterized in that consisting of a first semiconductor nanowire and a second semiconductor nanowire having a different conductivity type from the first semiconductor nanowire. The method of claim 2, The nano cell structure further comprising a gate pattern surrounding the second semiconductor nano structure. The method of claim 2, The semiconductor device may further include a third semiconductor nanostructure interposed between the second semiconductor nanostructure and the information storage nanostructure, wherein the third semiconductor nanostructure has the same conductivity type as the first semiconductor nanostructure. Cell structure. The method of claim 1, The information storage nanostructure is a nano cell structure, characterized in that consisting of phase-change nanowires containing a Ge element and a Te element. The method of claim 1, And a buffer nanostructure interposed between the semiconductor nanowire and the information storage nanostructure, wherein the buffer nanostructure is a conductive nanowire. The method of claim 1, A conductive structure positioned opposite to the semiconductor nanostructure with the information storage nanostructure interposed therebetween, the conductive structure being connected to one end of the information storage nanostructure so as to self-align with the information storage nanostructure, wherein the conductive structure is conductive Nano cell structure, characterized in that consisting of nano wires. A lower conductive pattern provided on the substrate; An insulating film provided on the substrate having the lower conductive pattern; An upper conductive pattern provided on the insulating layer and having an orientation intersecting with the lower conductive pattern; And And a nanostructure positioned in an area where the lower conductive pattern and the upper conductive pattern cross each other and penetrating the insulating layer, wherein the nanostructure is a semiconductor nanostructure in contact with the lower conductive pattern and the semiconductor nanostructure and self-alignment. Memory device, characterized in that consisting of information storage nanostructures connected to be. The method of claim 8, The semiconductor nanostructure comprises a first semiconductor nanowire connected in turn and a second semiconductor nanowire having a different conductivity type from the first semiconductor nanowire. The method of claim 9, Further comprising a third semiconductor nanostructure interposed between the information storage nanostructure and the second semiconductor nanowire, wherein the third semiconductor nanostructure is made of a semiconductor nanowire having the same conductivity type as the first semiconductor nanowire A memory device, characterized in that. The method of claim 9, And a conductive line positioned in the insulating layer and parallel to the lower conductive pattern, wherein the conductive line overlaps the lower conductive pattern and surrounds the second semiconductor nanowire. The method of claim 11, And a gate dielectric layer interposed between the conductive line and the second semiconductor nanowire. The method of claim 8, The information storage nanostructure is a memory device, characterized in that consisting of a phase change nanowire containing a Ge element and a Te element. The method of claim 8, And a conductive structure interposed between the information storage nanostructure and the upper conductive pattern, wherein the conductive structure is made of conductive nanowires. The method of claim 8, And a buffer nanostructure interposed between the semiconductor nanostructure and the information storage nanostructure, wherein the buffer nanostructure is made of conductive nanowires. To form a catalyst layer, Forming a semiconductor nanostructure grown from the catalyst layer, A method of manufacturing a nanocell comprising forming an information storage nanostructure grown from the semiconductor nanostructure. The method of claim 16, The semiconductor nanostructure is formed of a first semiconductor nanowire growing from the catalyst layer and a second semiconductor nanowire growing from the first semiconductor nanowire, wherein the second semiconductor nanowire is different from the first semiconductor nanowire. Nanocell manufacturing method characterized in that it has a mold. The method of claim 17, After forming the second semiconductor nanowire, Forming a third semiconductor nanowire growing from the second semiconductor nanowire, wherein the third semiconductor nanowire is characterized in that having the same conductivity type as the first semiconductor nanowire. The method of claim 17, After forming the second semiconductor nanowire, Forming a buffer nanostructures growing from the second semiconductor nanowires, wherein the buffer nanostructures are nano-cell manufacturing method characterized in that formed of conductive nanowires. The method of claim 16, Forming a conductive structure growing from the information storage nanostructures, wherein the conductive structure is a nano-cell manufacturing method characterized in that formed of conductive nanowires. The method of claim 16, The information storage nanostructure is a nano-cell manufacturing method, characterized in that formed with a phase-change nanowire containing a Ge element and a Te element. Forming a lower conductive pattern on the substrate, Forming lower and upper insulating layers sequentially stacked on the substrate having the lower conductive pattern, Patterning the lower and upper insulating layers to form a hole exposing a predetermined region of the lower conductive pattern; Forming a semiconductor nanostructure growing through the predetermined region of the exposed lower conductive pattern as a catalyst layer and an information storage nanostructure growing from the semiconductor nanostructure in the hole, Forming a conductive structure growing from the information storage nanostructure, Forming an upper conductive pattern covering the hole and electrically connecting the conductive structure to the upper insulating layer. The method of claim 22, The semiconductor nanostructure and the information storage nanostructure are formed of nanowires, wherein the semiconductor nanostructure is grown from the first semiconductor nanowire and the first semiconductor nanowire growing from the lower conductive pattern and the first semiconductor nano. And a second semiconductor nanowire having a conductivity type different from that of the wire, wherein the information storage nanostructure is formed of a phase-change nanowire containing a Ge element and a Te element. The method of claim 23, After forming the lower insulating film, And forming a conductive line on the lower interlayer insulating layer, wherein the conductive line has a width greater than the diameter of the hole and is located at substantially the same level as the second semiconductor nanowire, thereby patterning the lower and upper insulating layers. A method of manufacturing a memory device, characterized in that during the patterning together. The method of claim 22, The conductive structure is a method of manufacturing a memory device, characterized in that formed of conductive nanowires. The method of claim 22, After forming the conductive structure, And forming a dielectric film surrounding the semiconductor nanostructure.

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