KR20070114964A - Semiconductor memory device - Google Patents

Abstract

A semiconductor memory device is provided to assure gap between read commands by using a parallel compression test mode using a longer clock period than a normal mode, and to disperse simultaneous operation timing by generating a column signal controlling input/output operation between read commands. A command decoder(110) generates an operation signal. A read signal generator(120) outputs a first read signal in response to the operation signal, and outputs a second read signal in response to the operation signal and a test signal. A first and a second column signal generator(131,132) output a first and a second column signal as comprising two circuit parts in order to respond to the first and the second read signal. A first and a second column decoder(141,142) are constituted with two circuit parts in order to output a first and a second column address in response to the first and the second column signal. A memory cell array(160) stores data by being separated into two parts, in order to receive an address from a row decoder and the first and the second column decoder. A number of input/output sense amplifiers(171,172) output data amplified by sensing level difference of data applied from the memory cell array. A first and a second data comparison circuit(181,182) receive data through a first and a second local input/output line and output a first and a second comparison local signal in response to a test comparison signal in a test mode. A GIO(Global Input/Output) driver(190) outputs data through a first and a second global input/output line in response to the data and the first and the second comparison local signal. An output buffer(200) generates an output signal in response to the data applied through the first and the second global input/output line.

Description

Semiconductor memory device

1 is a schematic block diagram of a conventional semiconductor memory device.

FIG. 2 is a detailed circuit diagram of the read signal generator of FIG. 1.

3 is a timing diagram of signals related to data output of the semiconductor memory device of FIG. 1.

4 is a schematic block diagram of a semiconductor memory device of the present invention.

FIG. 5 is a detailed circuit diagram of the read signal generator of FIG. 4.

6 is a timing diagram of signals related to data output of the semiconductor memory device of FIG. 4.

<Explanation of symbols for the main parts of the drawings>

300: first signal generator 400: second signal generator

410: first control unit 430: second control unit

450: third control unit

The present invention relates to a semiconductor memory device, and more particularly to a semiconductor memory device capable of parallel compression test.

Currently, a parallel compress test mode is used to improve testing of semiconductor memory devices. Parallel compression test mode is a mode for the producer to run a large amount of tests in a shorter time to improve product productivity. That is, a serial test can be performed in parallel with a small number of input / output terminals (DQ) to simultaneously test for a short time. In the recent semiconductor data devices such as single data rate (SDR), double data rate (DDR), and DDR2, there are generally 16 input / output terminals and a plurality of banks. In this case, the internal cell array is called a bank, and it is divided into four banks up to 512 megabytes and eight banks after one gigabyte. At this time, since four or eight banks operate at the same time, this is called parallel. Since 16 input / output terminals in the normal mode are inputted and outputted by banks with four input / output terminals, it is called compression. The configuration of the parallel compression test mode will be described with reference to the accompanying drawings.

1 is a schematic block diagram of a conventional semiconductor memory device. The semiconductor memory device 10 includes a command decoder 11, a read signal generator 12, a column signal generator 13, a column decoder 14, a row decoder 15, a memory cell array 16, an input / output sense amplifier. (17), data comparison circuit 18, GIO driver 19, and output driver 20 are included.

FIG. 2 is a detailed circuit diagram of the read signal generator shown in FIG. 1. The read signal generator 20 includes a NAND gate 21 and an inverter 22. The NAND gate 21 generates an output signal in response to the external clock CLK and the operation signal RDS, and the output signal is inverted by the inverter 22 to output the read signal RDP. The read signal RDP is applied to the column signal generator 13 of FIG. 1 to generate a column signal YPR that becomes a basic signal of the column operation during read.

3 is a timing diagram of signals related to data output of the semiconductor memory device shown in FIG. 1. The timing diagram is an example of DDR2 synchronous DRAM (SDRAM) in which eight banks operate simultaneously. In the DDR2 SDRAM, the interval between read commands is two clocks, and the column signal YPR is generated by the read signal RDP. Data is applied to the global input / output lines GIO by the column signal YPR, and data is output to the output terminal DQ.

However, 64 global input / output lines (GIO) are required per bank, and in parallel compression test mode, four or eight bank read data results must be simultaneously outputted by four or eight output terminals (DQ). Therefore, the input and output amplifiers are 256 or 512 are operated at the same time, the power consumption is large, thereby increasing the peak (peak) current. This causes the power supply capacity of the memory device or the test device to be degraded and causes distortion by noise.

Accordingly, a technical problem to be achieved by the present invention is to secure a gap between read commands using a parallel compression test mode using a clock cycle longer than a normal mode, and to generate a column signal for controlling an input / output operation between read commands. This is to distribute the timing of simultaneous operation.

In accordance with another aspect of the present invention, a semiconductor device includes a command decoder for generating an operation signal, a first read signal in response to the operation signal, and a response to the operation signal and a test signal. A read signal generator for outputting a second read signal at a time difference from the first read signal, and having two circuit parts for responding to the first and second read signals to become a basic signal of a column operation during reading; First and second column signal generators for outputting first and second column signals, and first and second circuits comprising two circuit sections for outputting first and second column addresses in response to the first and second column signals. Memory cell array for storing data divided into at least two or more so as to receive an address from a two-column decoder, a row decoder and the first and second column decoders, respectively And a plurality of input / output sense amplifiers for detecting a level difference between data received from the memory cell array and outputting amplified data, receiving data through first and second local input / output lines in a test mode, and responsive to a test comparison signal. First and second data comparison circuits for outputting first and second comparison local signals, and a GIO driver for outputting data through first and second global input / output lines in response to the data and the first and second comparison local signals; And an output buffer configured to generate an output signal in response to data applied through the first and second global input / output lines.

Hereinafter, with reference to the accompanying drawings will be described a preferred embodiment of the present invention. However, the present invention is not limited to the embodiments disclosed below, but can be embodied in various other forms, and only the present embodiments make the disclosure of the present invention complete and the scope of the invention to those skilled in the art. It is provided to inform you completely.

4 is a schematic block diagram of a semiconductor memory device of the present invention. The semiconductor memory device 100 may include a command decoder 110, a read signal generator 120, first and second column signal generators 131 and 132, column decoders 141 and 142, a row decoder 150, and a first decoder. The first and second memory cell arrays 161 and 162, the first and second input / output sense amplifiers 171 and 172, the data comparison circuit unit 180, the GIO driver 190, and the output buffer 200 are included. The command decoder 110 outputs an operation signal RDS which is a state signal of a read operation in response to a signal input through an input pin. The read signal generator 120 outputs the first read signal RDP1 in response to the operation signal RDS and the first read signal RDP1 in response to the operation signal RDS and the test signal TPA. The second read signal RDP2 is output with a time difference therebetween to distribute the peak current. The first and second column signal generators 131 and 132 may include first and second column signals, which become basic signals of a column operation upon reading in response to the first and second read signals RDP1 and RDP2. YPR1, YPR2) are output. The first and second column decoders 141 and 142 output the plurality of first and second column addresses CADD1 and CADD2 in response to the first and second column signals YPR1 and YPR2. The row decoder 150 controls the row addresses LADD1 and LADD2 of the memory cell array 160. The memory cell array 160 stores data in the memory cells by the first and second column decoders 141 and 142 and the row decoder 150. The first and second input / output sense amplifiers 171 ˜ 172 detect and amplify level differences of data output from the memory cell array 160 and are output through the plurality of local input / output lines LIO1 and LIO2. The first and second data comparison circuits 181 and 182 output comparison local signals CLIO1 and CLIO2 in response to data transmitted through the plurality of local input / output lines LIO1 and LIO2 and the test comparison signal TPACMP. do. The GIO driver 190 transmits the data through the plurality of local I / O lines LIO1 and LIO2 and the first and second global I / O lines GIO1 and GIO2 in response to the comparison local signals CLIO1 and CLIO2. do. The output buffer 200 outputs the data to the output terminal DQ in response to the data transmitted through the first and second global input / output lines GIO1 and GIO2.

FIG. 5 is a detailed circuit diagram of the read signal generator of FIG. 4. The read signal generator 120 includes a first signal generator 300 and a second signal generator 400. The first signal generator 300 includes a NAND gate 301 and an inverter 302. The NAND gate 301 outputs the first logic signal L1 in response to the external clock CLK and the operation signal RDS and inverts the inverter 302 to output the first read signal RDP1. The second signal generator 400 includes a first controller 410, a second controller 430, and a third controller 450. The first controller 410 includes an inverter 411, a three-phase inverter 412, and a first latch circuit 420. The inverter 411 outputs the inverted external clock CLKb to the three-phase inverter 412 and the second controller 430. The three-phase inverter 412 receives the operation signal RDS, the inverted external clock CLKb, and the external clock CLK to output the first input signal RD1. The first latch unit 420 stores the first input signal RD1 and outputs the first latch signal LA1. The second control unit 430 includes a three phase inverter 442 and a second latch unit 440. The three-phase inverter 431 outputs the second input signal RD2 in response to the first latch signal LA1, the external clock CLK, and the inverted external clock CLKb. The second latch unit 440 latches the second input signal RD2 and outputs the second latch signal LA2. The third controller 450 includes second and third NAND gates 451 and 452 and a noah gate 453. The second NAND gate 451 outputs the second logic signal L2 in response to the test signal TPA, the external clock CLK, and the operation signal RDS inverted by the inverter 401. The third NAND gate 452 outputs the third logic signal L3 in response to the test signal TPA, the second latch signal LA2, and the external clock CLK. The NOR gate 453 outputs a second read signal RDP2 in response to the second and third logic signals L2 and L3. In the test mode, the test signal TPA is applied to a logic high state, and in the normal mode, the test signal TPA is applied to a logic low state. When the test signal TPA is logic high, the second read signal RDP2 is generated one clock after the first read signal RDP1. When the test signal TPA is logic low, the second read signal RDP2 is generated one clock after the first read signal RDP1. Therefore, the device is also separated into two parts by outputting the two operation signals RDP in the test mode.

6 is a timing diagram of signals related to data output of the semiconductor memory device of FIG. 4. For example, the generation of the first and second column signals YPR1 and YPR2 of the DDR2 SDRAM, and the data applied to the plurality of global input / output lines GIO0_Q0 to GIO7_Q3 and the operation of the plurality of output data DQ0 to DQ7. Indicated. In the present invention, since the read signal generator 120 outputs two read signals RDP1 and RDP2, the remaining conventional devices below the read signal generator 120 may be implemented as two devices. Therefore, only the signals directly related to the present invention are shown in the timing diagram.

In the T1 section, when the operation signal RDS is logic high, the first read signal RDP1 becomes logic high at the rising edge of the external clock CLK. The first column signal YPR1 is logic high while the first read signal RDP1 is logic high. The three-phase inverter 412 outputs the first input signal RD1 of the logic low when the external clock CLK of the logic high, the inverted external clock CLKb, and the operation signal RDS of the logic high are applied. The first latch circuit 420 latches the first input signal RD1 and outputs the first logic signal LA1 to logic high. The three-phase inverter 431 outputs the second input signal RD2 of the logic low in response to the first latch signal LA1 of the logic high, the external clock CLK of the logic low, and the inverted external clock CLKb. The second latch unit 440 latches the second input signal RD2 and outputs a second latch signal LA2 of logic high. In a period T2, the second NAND gate 451 is configured to respond to the test signal TPA of logic high, the second latch signal LA2 of logic high, and the second logic logic low in response to the external clock CLK in the logic high state. Generate a logic signal L2. The logic signal L2 is inverted by the inverter 452 and the second read signal RDP2 of logic high is output. Then, while the second read signal RDP2 is at a logic high state, the second column signal YPR2 is at a logic high state.

Data applied to the global even lines GIO0_Q0, GIO2_Q0, GIO4_Q0, GIO6_Q0, and GIO0_Q1 is output in synchronization with the logic high of the first column signal YPR1, and is synchronized with the logic high of the second column signal YPR2. Data applied to the lines GIO1_Q0, GIO3_Q0, GIO5_Q0, and GIO7_Q0 is output. In more detail, 'GIO0_Q0' represents one GIO in which data applied to 16 local input / output lines LIO are parallel-compressed and output as output data in synchronization with the first column signal YPR1. Even data signals 'GIO2_Qi', 'GIO4_Qi' and 'GIO6_Qi' (i = 0 to 3) are output in synchronization with the first column signal YPR1 like 'GIO0_Q0'. The odd data signals 'GIO1_Qi', 'GIO3_Qi', 'GIO5_Qi', and 'GIO7_Qi' are output in synchronization with the second column signal YPR2. The DQ output is set to be the same at T4 taking into account the GIO output timing of the odd bank.

Therefore, if 8 banks of DDR2 SDRAM have 16 input / output terminals, 4 quarters and 8 banks, 256 of the total 512 input / output amplifiers operate in synchronization with T1, T3, T5, and T7, and the remaining 256 units are T2, T4, It operates by operating on T6 and T8. Therefore, the peak current is dispersed.

Although the technical spirit of the present invention described above has been described in detail in a preferred embodiment, it should be noted that the above-described embodiment is for the purpose of description and not of limitation. In addition, the present invention will be understood by those skilled in the art that various embodiments are possible within the scope of the technical idea of the present invention.

As described above, the semiconductor memory device according to the present invention can further reduce column noise by distributing peak currents by varying the operating time of a signal applied to a global input / output line by further generating column signals, and paralleling the normal mode. Operational differences from the test mode can be reduced, which improves the reliability of the parallel test mode.

Claims (10)

A command decoder for generating an operation signal; A read signal generator outputting a first read signal in response to the operation signal and outputting a second read signal at a time difference from the first read signal in response to the operation signal and a test signal; First and second column signal generators comprising two circuit parts for responding to the first and second read signals and outputting first and second column signals serving as basic signals of a column operation during reading; First and second column decoders configured by two circuit parts to output first and second column addresses in response to the first and second column signals; A memory cell array configured to store data divided into at least two or more to receive an address from the row decoder and the first and second column decoders, respectively; A plurality of input / output sense amplifiers configured to output amplified data by sensing a level difference between data applied from the memory cell array; First and second data comparison circuits receiving data through the first and second local input / output lines in the test mode and outputting first and second comparison local signals in response to the test comparison signal; A GIO driver configured to output data through first and second global input / output lines in response to the data and the first and second comparison local signals; And And an output buffer configured to generate an output signal in response to data applied through the first and second global input / output lines. The method of claim 1, wherein the read signal generator, A first signal generator configured to output the first read signal in response to the operation signal and an external clock; And And a second signal generator configured to operate in a test mode and output the second read signal in response to the operation signal, an external clock, and a test signal. The method of claim 3, wherein the first signal generator, A NAND gate outputting a first logic signal in response to the operation signal and an external clock; And And an inverter outputting the first read signal by inverting the first logic signal. The method of claim 3, wherein the second signal generator, A first controller configured to output an inverted external clock and a first latch signal in response to the operation signal and the external clock; A second controller configured to output a second latch signal in response to the external clock, the inverted external clock, and a first latch signal; And And a third controller configured to output a second read signal in response to the external clock, the second latch signal, the operation signal, and the test signal. The method of claim 4, wherein the first control unit, An inverter for inverting the external clock; A first three-phase inverter outputting a first input signal in response to the operation signal, the external clock and the inverted external clock; And And a first latch unit configured to latch the first input signal and output the first latch signal. The method of claim 4, wherein the second control unit, A second three-phase inverter outputting a second input signal in response to the first latch signal, an external clock, and an inverted external clock; And And a second latch unit configured to latch the second input signal and output a second latch signal. The method of claim 4, wherein the third control unit, A first NAND gate outputting a first logic signal in response to the inverted test signal, the external clock, and the operation signal; A second NAND gate outputting a second logic signal in response to the test signal, the second latch signal, and the operation signal; And And a NOR gate outputting the second read signal in response to the first and second logic signals. The method of claim 7, wherein the test signal, A signal that distinguishes a normal mode from a test mode, is applied in a logic low state in a normal mode so that the second read signal is generated one clock after the first read signal, and is applied in a logic high state in a test mode, so that the second dock The semiconductor memory device of which the origin code is output in synchronization with the first read signal. The method of claim 1, wherein the read signal generator or lower column signal generator, column decoder, memory cell array, input / output sense amplifier, and data comparator circuit devices have two signals outputted from the read signal generator and are separated into two parts. And a semiconductor memory device. The memory cell array of claim 9, wherein the memory cell array comprises: A semiconductor memory device which is divided into two parts and operated in a data input / output operation.

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