KR20070109653A - Method for manufacturing semiconductor device - Google Patents

Method for manufacturing semiconductor device Download PDF

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KR20070109653A
KR20070109653A KR1020060042956A KR20060042956A KR20070109653A KR 20070109653 A KR20070109653 A KR 20070109653A KR 1020060042956 A KR1020060042956 A KR 1020060042956A KR 20060042956 A KR20060042956 A KR 20060042956A KR 20070109653 A KR20070109653 A KR 20070109653A
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layer
hard mask
photoresist pattern
pattern
semiconductor device
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KR1020060042956A
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Korean (ko)
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KR100827520B1 (en
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이기령
엄태승
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주식회사 하이닉스반도체
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31144—Etching the insulating layers by chemical or physical means using masks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/0271—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers
    • H01L21/0273—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers characterised by the treatment of photoresist layers
    • H01L21/0274—Photolithographic processes
    • H01L21/0276—Photolithographic processes using an anti-reflective coating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/033—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers
    • H01L21/0334—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
    • H01L21/0337—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane characterised by the process involved to create the mask, e.g. lift-off masks, sidewalls, or to modify the mask, e.g. pre-treatment, post-treatment
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31127—Etching organic layers
    • H01L21/31133—Etching organic layers by chemical means
    • H01L21/31138—Etching organic layers by chemical means by dry-etching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/32055—Deposition of semiconductive layers, e.g. poly - or amorphous silicon layers

Abstract

A method for manufacturing a semiconductor device is provided to simplify processes by abbreviating processes for forming and etching an amorphous carbon layer and a silicon oxide nitride layer using a hard mask as a polysilicon layer. An etched layer(110), a hard mask(120), a first anti-reflection barrier and a first photoresist pattern are formed on a semiconductor substrate(100). The first anti-reflection barrier and the hard mask are etched by using the first photoresist pattern as a mask. After removing the first photoresist pattern, a flattened polymer layer(150) is formed at the entire surface. A second anti-reflection barrier(160) and a second photoresist pattern(145) are formed on the polymer layer. The second anti-reflection barrier, the polymer layer and the hard mask are etched by using the second photoresist pattern as a mask. An ashing process is performed to remove the polymer layer, the second anti-reflection barrier and the second photoresist pattern. A pattern is formed by etching the etched layer by using the hard mask.

Description

반도체 소자의 제조 방법{METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE}Method for manufacturing a semiconductor device {METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE}

도 1a 및 도 1b는 종래기술에 따른 반도체 소자의 제조 방법의 문제점을 도시한 사진. 1A and 1B are photographs showing a problem of a method of manufacturing a semiconductor device according to the prior art.

도 2a 내지 도 2d는 종래 기술에 따른 반도체 소자의 제조 방법을 도시한 단면도.2A to 2D are cross-sectional views illustrating a method of manufacturing a semiconductor device according to the prior art.

도 3a 내지 도 3e는 본 발명의 제 1 실시예에 따른 반도체 소자의 제조 방법을 도시한 단면도.3A to 3E are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with a first embodiment of the present invention.

도 4a 내지 도 4c는 본 발명의 제 2 실시예에 따른 반도체 소자의 제조 방법을 도시한 단면도.4A to 4C are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with a second embodiment of the present invention.

본 발명은 반도체 소자의 제조 방법에 관한 것으로, 하드마스크층의 단차를 보상하기 위해 ArF 노광원에 의해 노광되지 않으며 식각 공정시 하부층에 손상이 없는 탄소 리치 폴리머를 형성하여 반사방지막의 두께 균일도 불량으로 인한 패턴 불량을 방지하며, 폴리실리콘층 하드마스크만을 사용하므로 비정질 탄소층 및 실리콘 산화질화막을 형성하고 식각하는 공정을 생략할 수 있어 공정이 단순화되는 기 술을 개시한다. The present invention relates to a method for manufacturing a semiconductor device, and to compensate for the step of the hard mask layer to form a carbon-rich polymer that is not exposed to the ArF exposure source and the damage in the lower layer during the etching process to the thickness uniformity of the anti-reflection film is poor Since a pattern defect is prevented and only a polysilicon layer hard mask is used, a process of forming and etching an amorphous carbon layer and a silicon oxynitride layer may be omitted, thereby simplifying the process.

최근 반도체 소자의 디자인 룰이 감소함에 따라 현재 NA 0.1 이하의 ArF 노광 장비의 한계로 인해 한 번의 노광으로는 50nm 이하의 라인/스페이스 패턴을 형성할 수 없다. 그래서, 노광 공정에서 해상도 향상을 위해 반도체 기판 상에 두 개의 마스크를 각각 노광한 후 현상하는 방법이 사용되는데 이는 미세 패턴과 고립형 패턴을 각각 노광하여 공정 마진을 확보하기 어려운 문제점이 있다.As the design rules of semiconductor devices decrease recently, a single exposure cannot form a line / space pattern of 50 nm or less due to the limitation of ArF exposure equipment of NA 0.1 or less. Thus, a method of exposing two masks onto a semiconductor substrate and then developing them in order to improve resolution in an exposure process is used, which is difficult to secure process margins by exposing the fine patterns and the isolated patterns, respectively.

상기와 같은 문제점을 해결하기 위해 두번의 노광 및 현상 공정과 두번의 식각 공정을 수행하는 공정이 사용되고 있다. In order to solve the above problems, a process of performing two exposure and development processes and two etching processes are used.

도 1a 및 도 1b는 종래 기술에 따른 반도체 소자의 제조 방법의 문제점을 도시한 사진이다. 1A and 1B are photographs showing a problem of a method of manufacturing a semiconductor device according to the prior art.

도 1a를 참조하면, 하드 마스크층(1)의 두께에 따른 반사방지막(5)의 코팅 균일도가 불량한 모습을 나타낸 TEM (Transmission Electron Microscope) 사진으로, 하드마스크층(1)의 두께가 두꺼울수록 패턴의 골과 마루부분의 반사방지막(5)의 두께 차이가 크게 발생하는 것을 알 수 있다. Referring to FIG. 1A, a TEM (Transmission Electron Microscope) photograph showing a poor coating uniformity of the anti-reflection film 5 according to the thickness of the hard mask layer 1. The thicker the thickness of the hard mask layer 1 is, the pattern It can be seen that the difference in the thickness of the antireflection film (5) of the valley and the floor portion is large.

도 1b를 참조하면, 이중노광 공정을 수행하여 형성한 라인 또는 스페이스 패턴을 나타낸 것으로, 반사방지막의 코팅 불량으로 인해 라인 패턴의 에지부 선폭이 균일하지 않게 형성된 것을 알 수 있다. Referring to FIG. 1B, the line or space pattern formed by performing the double exposure process is shown. It can be seen that the line width of the edge portion of the line pattern is not uniform due to the poor coating of the anti-reflection film.

도 2a 내지 도 2d는 종래 기술에 따른 반도체 소자의 제조 방법을 도시한 단면도이다. 2A to 2D are cross-sectional views illustrating a method of manufacturing a semiconductor device according to the prior art.

도 2a를 참조하면, 반도체 기판(10) 상부에 피식각층(20), 비정질 탄소 층(30), 실리콘 산화질화막(40), 하드마스크층(50), 제 1 반사방지막(60) 및 제 1 감광막 패턴(70)을 순차적으로 형성한다. Referring to FIG. 2A, an etched layer 20, an amorphous carbon layer 30, a silicon oxynitride layer 40, a hard mask layer 50, a first anti-reflection layer 60, and a first layer may be formed on the semiconductor substrate 10. The photosensitive film pattern 70 is sequentially formed.

여기서, 제 1 감광막 패턴(70)은 최종 패턴 피치의 두배의 피치를 가지는 것이 바람직하다.Here, the first photosensitive film pattern 70 preferably has a pitch twice the final pattern pitch.

다음에, 제 1 감광막 패턴(70)을 마스크로 반사방지막(60) 및 하드마스크층(50)을 식각한다.Next, the anti-reflection film 60 and the hard mask layer 50 are etched using the first photoresist pattern 70 as a mask.

도 2b를 참조하면, 제 1 감광막 패턴(70) 및 반사방지막(60)을 제거하고, 전체 표면에 제 2 반사방지막(65) 및 제 2 감광막 패턴(75)를 형성한다. Referring to FIG. 2B, the first photoresist film pattern 70 and the anti-reflection film 60 are removed, and the second anti-reflection film 65 and the second photoresist film pattern 75 are formed on the entire surface.

도 2c를 참조하면, 제 2 감광막 패턴(75)을 마스크로 제 2 반사방지막(65) 및 하드마스크층(50)을 식각하고, 제 2 반사방지막(65)을 제거하여 하드마스크층 패턴(55)을 형성한다. Referring to FIG. 2C, the second anti-reflection film 65 and the hard mask layer 50 are etched using the second photoresist pattern 75 as a mask, and the second anti-reflection film 65 is removed to remove the hard mask layer pattern 55. ).

도 2d를 참조하면, 하드마스크층 패턴(55)을 마스크로 실리콘산화질화막(40), 비정질 탄소층(30) 및 피식각층(20)을 순차적으로 식각하여 최종 패턴을 형성한다. Referring to FIG. 2D, the final pattern is formed by sequentially etching the silicon oxynitride layer 40, the amorphous carbon layer 30, and the etched layer 20 using the hard mask layer pattern 55 as a mask.

이때, 하드마스크층을 하부물질의 식각마스크로 사용하는 경우 식각 선택비 특성상 하드마스크층의 두께가 1000Å 이상이 되어야 하므로, 하부물질의 단차를 따라가는 컨포멀(Confomal)형 반사방지막으로는 단차가 형성된 하드마스크층 마루에 기판 반사율이 1.0% 이하가 되는 두께로 반사방지막을 형성할 수 없다. In this case, when the hard mask layer is used as an etch mask of the underlying material, the thickness of the hard mask layer should be 1000 Å or more due to the etching selectivity. Therefore, a step is formed by the conformal anti-reflection film that follows the step of the underlying material. An antireflection film cannot be formed on the hard mask layer floor with a thickness such that the substrate reflectance is 1.0% or less.

이때, 플래너(Plannar)형 반사방지막을 사용하게 되면, 이는 안정된 패터닝은 가능하지만 골 부분에 형성된 반사방지막 식각 공정시 하부층에 손상을 입힐 수 있다. In this case, if a planar antireflection film is used, this may allow stable patterning but may damage the lower layer during the antireflection film etching process formed on the valley portion.

상술한 종래 기술에 따른 반도체 소자의 제조 방법에서, 하드마스크층의 단차로 인해 후속 반사방지막의 두께 균일도 불량이 발생하며, 비정질 탄소층 및 실리콘 산화질화막을 하드마스크층으로 사용하는 경우 두 번의 증착 및 식각공정이 추가되어 공정이 복잡해지는 문제점이 있다. In the above-described method of manufacturing a semiconductor device according to the related art, a thickness uniformity defect of a subsequent anti-reflection film occurs due to the step of the hard mask layer, and when the amorphous carbon layer and the silicon oxynitride film are used as the hard mask layer, two depositions and The etching process is added, there is a problem that the process is complicated.

상기 문제점을 해결하기 위하여, 하드마스크층의 단차를 보상하기 위해 ArF 노광원에 의해 노광되지 않으며 식각 공정시 하부층에 손상이 없는 탄소 리치 폴리머를 형성하여 반사방지막의 두께 균일도 불량으로 인한 패턴 불량을 방지하며, 폴리실리콘층 하드마스크만을 사용하므로 비정질 탄소층 및 실리콘 산화질화막을 형성하고 식각하는 공정을 생략할 수 있어 공정이 단순화되는 반도체 소자의 제조 방법을 제공하는 것을 목적으로 한다. In order to solve the above problems, in order to compensate for the step difference of the hard mask layer, a carbon rich polymer which is not exposed by the ArF exposure source and forms no damage to the lower layer during the etching process prevents pattern defects due to poor thickness uniformity of the antireflection film. In addition, since only a polysilicon layer hard mask is used, a process of forming and etching an amorphous carbon layer and a silicon oxynitride layer can be omitted, and an object of the present invention is to provide a method of manufacturing a semiconductor device in which the process is simplified.

본 발명에 따른 반도체 소자의 제조 방법은 Method for manufacturing a semiconductor device according to the present invention

(a) 반도체 기판 상부에 피식각층, 하드마스크층, 제 1 반사방지막 및 제 1 감광막 패턴을 형성하는 단계; (b) 상기 제 1 감광막 패턴을 마스크로 상기 제 1 반사방지막 및 하드마스크층을 식각하는 단계; (c) 상기 제 1 감광막 패턴을 제거하고, 전체 표면에 평탄화된 폴리머층을 형성하는 단계; (d) 상기 폴리머층 상부에 제 2 반사방지막 및 제 2 감광막 패턴을 형성하는 단계; (e) 상기 제 2 감광막 패턴을 마스크로 상기 제 2 반사방지막, 폴리머층 및 하드마스크층을 식각하는 단계; (f) 애싱 공정을 수행하여 폴리머층, 제 2 반사방지막 및 제 2 감광막 패턴을 제거하는 단계; (g) 상기 하드마스크층을 마스크로 상기 피식각층을 식각하여 패턴을 형성하는 단계를 포함하는 것을 특징으로 한다. (a) forming an etched layer, a hard mask layer, a first anti-reflection film and a first photoresist pattern on the semiconductor substrate; (b) etching the first antireflection film and the hard mask layer using the first photoresist pattern as a mask; (c) removing the first photoresist pattern and forming a planarized polymer layer on an entire surface thereof; (d) forming a second anti-reflection film and a second photoresist pattern on the polymer layer; (e) etching the second anti-reflection film, the polymer layer, and the hard mask layer using the second photoresist pattern as a mask; (f) performing an ashing process to remove the polymer layer, the second antireflection film, and the second photoresist pattern; (g) forming a pattern by etching the etched layer using the hard mask layer as a mask.

이하에서는 본 발명의 실시예를 첨부한 도면을 참조하여 상세히 설명하기로 한다.Hereinafter, with reference to the accompanying drawings an embodiment of the present invention will be described in detail.

도 3a 내지 도 3e는 본 발명의 제 1 실시예에 따른 반도체 소자의 제조 방법을 도시한 단면도이다.3A to 3E are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with a first embodiment of the present invention.

도 3a를 참조하면, 반도체 기판(100) 상부에 피식각층(110), 하드마스크층(120), 제 1 반사방지막(130) 및 제 1 감광막 패턴(140)을 형성한다. Referring to FIG. 3A, an etched layer 110, a hard mask layer 120, a first anti-reflection film 130, and a first photoresist pattern 140 are formed on the semiconductor substrate 100.

다음에, 제 1 감광막 패턴(140)을 마스크로 제 1 반사방지막(130) 및 하드마스크층(120)을 식각한다.Next, the first anti-reflection film 130 and the hard mask layer 120 are etched using the first photoresist pattern 140 as a mask.

이때, 피식각층(110)은 2000 내지 3000Å의 질화막으로 형성하고, 하드마스크층(120)은 1000 내지 2000Å의 폴리실리콘층으로 형성하며, 제 1 감광막 패턴(140)의 피치는 최종 패턴의 피치의 2배인 것이 바람직하다. At this time, the etched layer 110 is formed of a nitride film of 2000 to 3000 GPa, the hard mask layer 120 is formed of a polysilicon layer of 1000 to 2000 GPa, and the pitch of the first photoresist pattern 140 is the pitch of the final pattern. It is preferable that it is 2 times.

도 3b를 참조하면, 제 1 감광막 패턴(140) 및 제 1 반사방지막(130)을 제거한 후 전체 표면에 평탄화된 폴리머층(150)을 형성하고, 제 2 반사방지막(160) 및 제 2 감광막 패턴(145)를 형성한다. Referring to FIG. 3B, after the first photoresist layer pattern 140 and the first antireflection layer 130 are removed, the planarized polymer layer 150 is formed on the entire surface, and the second antireflection layer 160 and the second photoresist layer pattern are formed. 145 is formed.

여기서, 제 2 반사방지막(160)은 193nm의 파장에서 1.3 내지 1.6의 굴절률을 가지고, 0.3 내지 0.8의 흡광계수를 가지며, 제 2 감광막 패턴(145)의 피치는 최종 패턴 피치의 2배이며, 제 1 감광막 패턴(140)의 중앙부가 노출되도록 형성하는 것 이 바람직하다.Here, the second anti-reflection film 160 has a refractive index of 1.3 to 1.6 at a wavelength of 193 nm, an extinction coefficient of 0.3 to 0.8, and the pitch of the second photoresist pattern 145 is twice the final pattern pitch. 1 It is preferable to form so that the central portion of the photosensitive film pattern 140 is exposed.

또한, 폴리머층(150)은 탄소 리치 폴리머(C-Rich Polymer)를 사용하며, 이는 하드마스크층(120)의 단차를 보상하기 위해 하드마스크층(120) 상부에 50 내지 200Å의 두께로 평탄하게 코팅한다. In addition, the polymer layer 150 uses a carbon-rich polymer (C-Rich Polymer), which is flat to a thickness of 50 to 200 μm on the hard mask layer 120 to compensate for the step difference of the hard mask layer 120. Coating.

상기 탄소 리치 폴리머는 탄소의 함량이 80 내지 90%인 폴리머로 ArF 노광원에 의해 노광되지 않고, 식각 후 제거 공정시 하부층에 손상을 주지 않는 장점이 있다. The carbon rich polymer is a polymer having a carbon content of 80 to 90% and is not exposed by an ArF exposure source, and has an advantage of not damaging an underlying layer during an etching and removing process.

도 3c를 참조하면, 제 2 감광막 패턴(145)를 마스크로 제 2 반사방지막(160), 폴리머층(150) 및 하드마스크층(120)을 식각하여, 제 2 반사방지막 패턴(165), 폴리머층 패턴(155) 및 하드마스크층 패턴(125)을 형성한다. Referring to FIG. 3C, the second anti-reflection film 160, the polymer layer 150, and the hard mask layer 120 are etched using the second photoresist pattern 145 as a mask to form the second anti-reflection film pattern 165 and the polymer. The layer pattern 155 and the hard mask layer pattern 125 are formed.

여기서, 제 2 반사방지막(160)은 CF4, O2 및 이들의 조합 중 선택된 어느 하나를 사용하여 식각하며, 폴리머층(150)은 O2. N2, H2 및 이들의 조합 중 선택된 어느 하나를 사용하여 식각하는 것이 바람직하다. Here, the second anti-reflection film 160 is etched using any one selected from CF 4 , O 2, and a combination thereof, and the polymer layer 150 may be formed of O 2 . It is preferable to etch using any one selected from N 2 , H 2 and combinations thereof.

도 3d를 참조하면, O2 가스를 사용한 애싱 공정을 수행하여 제 2 감광막 패턴(145)을 제거한다. 이때, 폴리머층 패턴(155) 및 제 2 반사방지막 패턴(165)도 같이 제거된다.Referring to FIG. 3D, an ashing process using O 2 gas is performed to remove the second photoresist pattern 145. At this time, the polymer layer pattern 155 and the second anti-reflection film pattern 165 are also removed.

도 3e를 참조하면, 하드마스크층 패턴(125)를 마스크로 피식각층(110)을 식각하여 미세 패턴(115)를 형성한다. Referring to FIG. 3E, the etching target layer 110 is etched using the hard mask layer pattern 125 as a mask to form a fine pattern 115.

도 4a 내지 도 4c는 본 발명의 제 2 실시예에 따른 반도체 소자의 제조 방법 을 도시한 단면도이다.4A through 4C are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with a second embodiment of the present invention.

도 4a를 참조하면, 상기 도 3a의 공정을 수행한 후 구조물 상부에 탄소 리치 폴리머층(230)을 형성한 후 전면 식각하여 폴리머층이 하드마스크층(220) 상부보다 낮은 두께로 매립되도록 한다. Referring to FIG. 4A, after the carbon rich polymer layer 230 is formed on the structure after performing the process of FIG. 3A, the polymer layer is buried in a lower thickness than the hard mask layer 220 by etching the entire surface.

이때, 폴리머층(230)이 하드마스크층(220) 사이에 매립되는 두께에 따라 마루와 골 사이의 반사방지막의 두께가 차이가 날 수 있는데, 이를 방지하기 위해 기판의 반사율이 1.0% 이하가 되도록 전면 식각 수행 시간의 조절이 필요하다. In this case, the thickness of the anti-reflection film between the floor and the valley may vary depending on the thickness of the polymer layer 230 embedded between the hard mask layer 220. To prevent this, the reflectance of the substrate is 1.0% or less. It is necessary to adjust the time of the front etching.

도 4b를 참조하면, 전체 표면에 반사방지막(240) 및 감광막 패턴(250)을 형성한다. Referring to FIG. 4B, an anti-reflection film 240 and a photoresist pattern 250 are formed on the entire surface.

도 4c를 참조하면, 감광막 패턴(250)을 마스크로 반사방지막(240) 및 하드마스크층(220)을 식각하여 반사방지막 패턴(245) 및 하드마스크층 패턴(225)를 형성한다. Referring to FIG. 4C, the anti-reflection film 240 and the hard mask layer 220 are etched using the photoresist pattern 250 as a mask to form the anti-reflection film pattern 245 and the hard mask layer pattern 225.

다음에, 후속 공정은 상기 도 3d 및 도 3e와 동일하게 진행한다. Next, the subsequent process proceeds in the same manner as in FIGS. 3D and 3E.

본 발명에 따른 반도체 소자의 제조 방법은 1차 식각 공정 후에 탄소 리치 폴리머층을 형성하여 폴리실리콘층으로 형성된 하드마스크층의 단차를 보상하며, 폴리실리콘층으로 하드마스크층을 사용하여 비정질 탄소층 및 실리콘 산화질화막을 형성하고 식각하는 공정을 수행하지 않아도 되므로 공정이 단순화되는 효과가 있다. In the method of manufacturing a semiconductor device according to the present invention, a carbon rich polymer layer is formed after the first etching process to compensate for the step difference of the hard mask layer formed of the polysilicon layer, and the amorphous carbon layer and the hard mask layer are used as the polysilicon layer. Since the process of forming and etching the silicon oxynitride layer does not have to be performed, the process is simplified.

아울러 본 발명의 바람직한 실시예는 예시의 목적을 위한 것으로, 당업자라 면 첨부된 특허청구범위의 기술적 사상과 범위를 통해 다양한 수정, 변경, 대체 및 부가가 가능할 것이며, 이러한 수정 변경 등은 이하의 특허청구범위에 속하는 것으로 보아야 할 것이다.In addition, the preferred embodiment of the present invention is for the purpose of illustration, those skilled in the art will be able to various modifications, changes, substitutions and additions through the spirit and scope of the appended claims, such modifications and modifications are the following patents It should be regarded as belonging to the claims.

Claims (12)

(a) 반도체 기판 상부에 피식각층, 하드마스크층, 제 1 반사방지막 및 제 1 감광막 패턴을 형성하는 단계; (a) forming an etched layer, a hard mask layer, a first anti-reflection film and a first photoresist pattern on the semiconductor substrate; (b) 상기 제 1 감광막 패턴을 마스크로 상기 제 1 반사방지막 및 하드마스크층을 식각하는 단계;(b) etching the first antireflection film and the hard mask layer using the first photoresist pattern as a mask; (c) 상기 제 1 감광막 패턴을 제거하고, 전체 표면에 평탄화된 폴리머층을 형성하는 단계;(c) removing the first photoresist pattern and forming a planarized polymer layer on an entire surface thereof; (d) 상기 폴리머층 상부에 제 2 반사방지막 및 제 2 감광막 패턴을 형성하는 단계;(d) forming a second anti-reflection film and a second photoresist pattern on the polymer layer; (e) 상기 제 2 감광막 패턴을 마스크로 상기 제 2 반사방지막, 폴리머층 및 하드마스크층을 식각하는 단계;(e) etching the second anti-reflection film, the polymer layer, and the hard mask layer using the second photoresist pattern as a mask; (f) 애싱 공정을 수행하여 폴리머층, 제 2 반사방지막 및 제 2 감광막 패턴을 제거하는 단계; 및(f) performing an ashing process to remove the polymer layer, the second antireflection film, and the second photoresist pattern; And (g) 상기 하드마스크층을 마스크로 상기 피식각층을 식각하여 패턴을 형성하는 단계;(g) forming a pattern by etching the etched layer using the hard mask layer as a mask; 를 포함하는 것을 특징으로 하는 반도체 소자의 제조 방법. Method of manufacturing a semiconductor device comprising a. 제 1 항에 있어서,The method of claim 1, 상기 피식각층은 2000 내지 3000Å의 질화막으로 형성하는 것을 특징으로 하 는 반도체 소자의 제조 방법. The etching layer is a semiconductor device manufacturing method, characterized in that formed by a nitride film of 2000 to 3000 내지. 제 1 항에 있어서, The method of claim 1, 상기 하드마스크층은 1000 내지 2000Å의 폴리실리콘층으로 형성하는 것을 특징으로 하는 반도체 소자의 제조 방법. The hard mask layer is a manufacturing method of a semiconductor device, characterized in that formed of a polysilicon layer of 1000 to 2000Å. 제 1 항에 있어서, The method of claim 1, 상기 폴리머층은 탄소 리치 폴리머(C-Rich Polymer)를 사용하는 것을 특징으로 하는 반도체 소자의 제조 방법. The polymer layer is a method of manufacturing a semiconductor device, characterized in that using a carbon-rich polymer (C-Rich Polymer). 제 1 항에 있어서, The method of claim 1, 상기 폴리머층은 상기 하드마스크층 상부에 50 내지 200Å의 두께로 형성하는 것을 특징으로 하는 반도체 소자의 제조 방법. The polymer layer is a method of manufacturing a semiconductor device, characterized in that formed on the hard mask layer to a thickness of 50 to 200Å. 제 1 항에 있어서,The method of claim 1, 상기 제 2 반사방지막은 193nm의 파장에서 1.3 내지 1.6의 굴절률을 가지고, 0.3 내지 0.8의 흡광계수를 가지는 것을 특징으로 하는 반도체 소자의 제조 방법. The second anti-reflection film has a refractive index of 1.3 to 1.6 at a wavelength of 193 nm, and has a light absorption coefficient of 0.3 to 0.8. 제 1 항에 있어서, The method of claim 1, 상기 (c) 단계는 상기 폴리머층 형성 후에 전면 식각 공정을 수행하여 소정 깊이만 매립되도록 할 수도 있는 것을 특징으로 하는 반도체 소자의 제조 방법. In the step (c), after the polymer layer is formed, the entire surface etching process may be performed to fill only a predetermined depth. 제 1 항에 있어서, The method of claim 1, 상기 (e) 단계의 제 2 반사방지막은 CF4, O2 및 이들의 조합 중 선택된 어느 하나를 사용하여 식각하는 것을 특징으로 하는 반도체 소자의 제조 방법.The second anti-reflection film of step (e) is etched using any one selected from CF 4 , O 2 and combinations thereof. 제 1 항에 있어서, The method of claim 1, 상기 (e) 단계의 폴리머층은 O2. N2, H2 및 이들의 조합 중 선택된 어느 하나를 사용하여 식각하는 것을 특징으로 하는 반도체 소자의 제조 방법.The polymer layer of step (e) is O 2 . Etching using any one selected from N 2 , H 2 and a combination thereof. 제 1 항에 있어서, The method of claim 1, 상기 애싱(Ashing) 공정은 O2 가스를 사용하여 수행하는 것을 특징으로 하는 반도체 소자의 제조 방법.The ashing process is a method of manufacturing a semiconductor device, characterized in that performed using O 2 gas. 제 1 항에 있어서, The method of claim 1, 상기 제 1 감광막 패턴 및 제 2 감광막 패턴의 피치는 상기 (g) 단계의 패턴 피치의 2배인 것을 특징으로 하는 반도체 소자의 제조 방법. The pitch of the first photosensitive film pattern and the second photosensitive film pattern is a manufacturing method of a semiconductor device, characterized in that twice the pattern pitch of the step (g). 제 1 항에 있어서, The method of claim 1, 상기 제 2 감광막 패턴은 상기 제 1 감광막 패턴의 중앙부가 노출되도록 형성하는 것을 특징으로 하는 반도체 소자의 제조 방법.The second photoresist pattern may be formed to expose a central portion of the first photoresist pattern.
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