KR20070109429A - Arrangement structure for flash memory device - Google Patents

Arrangement structure for flash memory device Download PDF

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KR20070109429A
KR20070109429A KR1020060042368A KR20060042368A KR20070109429A KR 20070109429 A KR20070109429 A KR 20070109429A KR 1020060042368 A KR1020060042368 A KR 1020060042368A KR 20060042368 A KR20060042368 A KR 20060042368A KR 20070109429 A KR20070109429 A KR 20070109429A
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South Korea
Prior art keywords
block
flash memory
memory
memory device
memory cell
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KR1020060042368A
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Korean (ko)
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윤인석
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주식회사 하이닉스반도체
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Priority to KR1020060042368A priority Critical patent/KR20070109429A/en
Publication of KR20070109429A publication Critical patent/KR20070109429A/en

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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/10—Programming or data input circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/26—Sensing or reading circuits; Data output circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/30—Power supply circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/34—Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
    • G11C16/3436—Arrangements for verifying correct programming or erasure
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C5/00—Details of stores covered by group G11C11/00
    • G11C5/02—Disposition of storage elements, e.g. in the form of a matrix array
    • G11C5/025—Geometric lay-out considerations of storage- and peripheral-blocks in a semiconductor storage device

Abstract

Arrangement structure for a flash memory device is provided to perform an optimum memory operation, by arranging a memory region to be optimized for the operation of the device, by arranging the memory region according to cell characteristics of a number of memory cells. Memory cells with same operation characteristics among a number of memory cells are arranged in the same region of a A, B, C, D memory cell block(11,12,13,14). A control block is arranged in one side of the A, B, C, D memory cell block, as controlling power used according to each operation characteristics of the A, B, C, D memory cell block. The A, B, C, D memory cell block are arranged according to program, read, erase and verify of a flash memory device.

Description

플래시 메모리 소자의 배치 구조{Arrangement structure for Flash memory device}Arrangement structure for flash memory device

도 1은 종래 기술에 따른 플래시 메모리 소자의 구조를 나타내는 배치도이다.1 is a layout view illustrating a structure of a flash memory device according to the related art.

도 2는 본 발명의 일실시 예에 따른 플래시 메모리 소자의 구조를 나타내는 배치도이다.2 is a layout view illustrating a structure of a flash memory device according to an embodiment of the present invention.

<도면의 주요 부분에 대한 설명>Description of the main parts of the drawing

11 : A 셀 영역 12 : B 셀 영역11: A cell area 12: B cell area

13 : C 셀 영역 14 : D 셀 영역13: C cell area 14: D cell area

15 : 논리 블락 16 : 고전압 블락15: Logic Block 16: High Voltage Block

17 : 아날로그 블락 18 : 페이지 버퍼17: analog block 18: page buffer

19 : 입출력 제어부19: input / output controller

본 발명은 플래시 메모리 소자의 구조에 관한 것으로, 특히 저전력 소모를 위한 플래시 메모리 소자의 구조에 관한 것이다.The present invention relates to a structure of a flash memory device, and more particularly to a structure of a flash memory device for low power consumption.

전기적으로 읽고 쓰기가 가능하며, 전원이 공급되지 않는 상태에서도 데이터를 저장하는 비휘발성 메모리(nonvolitile memory)이며, 리프레쉬(refresh)가 필요없는 저전력 소모의 플래시 메모리 장치(flash memory device)가 메모리 소자로서 각광받고 있다.Non-volatile memory that reads and writes electrically and stores data even when power is not supplied. Be in the spotlight.

한편, 플래시 메모리 소자는 점차 저전력화됨에 따라 저전력 특성을 강화하기 위한 연구가 활발히 진행되고 있다.On the other hand, as the flash memory devices are gradually lowered in power, researches for enhancing low power characteristics have been actively conducted.

도 1은 종래 기술에 따른 플래시 메모리 소자의 구조를 나타내는 배치도이다. 도 1을 참조하면, 플래시 메모리 소자는 다수의 메모리 셀들이 배치되어 있는 메모리 셀 영역(1)과 그 주변 영역에 데이터의 프로그램 또는 읽기 동작에 관여하는 X 디코더(2)와 페이지 버퍼 및 입출력 제어부(4)가 배치된다.1 is a layout view illustrating a structure of a flash memory device according to the related art. Referring to FIG. 1, a flash memory device includes an X decoder 2, a page buffer, and an input / output control unit that are involved in a program or read operation of data in a memory cell region 1 in which a plurality of memory cells are disposed, and a peripheral region thereof. 4) is arranged.

그러나 종래에는 동일한 트랜지스터들을 바탕으로 하여 동작 별로(프로그램 동작, 검증 동작, 소거 동작 등) 다른 전압 레벨을 적용하여 전체 메모리 셀의 동작을 제어하였다. 이 과정에서 셀의 특성이 각기 조금씩 다르기 때문에 슬로우 셀(slow cell)로부터 프로그램 속도가 길어지거나 소거 동작시 검증을 통한 타겟 블럭의 셀 상태를 재검증하는 등 추가적인 동작들이 필요하게 되어 이로부터 최적화된 파워 관리가 이루어지기 어렵다.However, in the related art, the operation of the entire memory cell is controlled by applying different voltage levels for each operation (program operation, verify operation, erase operation, etc.) based on the same transistors. In this process, since the characteristics of the cells are slightly different, additional operations are required, such as increasing the program speed from a slow cell or re-verifying the cell state of the target block through verification during an erase operation. Management is difficult to achieve.

본 발명이 이루고자 하는 기술적 과제는 다수의 메모리 셀들을 셀 특성 즉, 프로그램, 독출, 소거 또는 다른 동작에 따른 특성별로 분리 배치하여 소자의 동작에 최적화된 메모리 영역으로 나누어 배치함으로써, 최소의 전력 소모만으로 최적의 메모리 동작을 수행할 수 있는 플래시 메모리 소자의 구조를 제공하는 데 있다.The technical problem to be achieved by the present invention is to divide a plurality of memory cells by cell characteristics, that is, characteristics according to program, read, erase, or other operation, and divide them into memory regions optimized for operation of the device, thereby minimizing power consumption. The present invention provides a structure of a flash memory device capable of performing an optimal memory operation.

본 발명에 따른 플래시 메모리 소자의 구조는 다수의 메모리 셀들 중 동작 특성이 동일한 메모리 셀들이 동일한 영역으로 나뉘어 배치되는 A, B, C, D 메모리 셀 블럭, 및 상기 A, B, C, D 메모리 셀 블럭 각각의 동작 특성에 따라 사용되는 전력을 제어하며, 상기 상기 A, B, C, D 메모리 셀 블럭의 일측면에 배치되는 제어 블럭을 포함한다.The structure of a flash memory device according to the present invention includes A, B, C, and D memory cell blocks in which memory cells having the same operation characteristics among a plurality of memory cells are divided into the same area, and the A, B, C, and D memory cells. A control power is used according to the operation characteristics of each block, and includes a control block disposed on one side of the A, B, C, D memory cell block.

이하, 첨부된 도면을 참조하여 본 발명의 바람직한 실시 예를 설명하기로 한다. 그러나 본 발명은 이하에서 개시되는 실시 예에 한정되는 것이 아니라 서로 다른 다양한 형태로 구현될 수 있으며, 단지 본 실시 예는 본 발명의 개시가 완전하도록 통상의 지식을 가진자에게 발명의 범주를 완전하게 알려주기 위해 제공되는 것이다.Hereinafter, exemplary embodiments of the present invention will be described with reference to the accompanying drawings. As those skilled in the art would realize, the described embodiments may be modified in various different ways, all without departing from the spirit or scope of the present invention. It is provided to inform you.

도 2는 본 발명의 일실시 예에 따른 플래시 메모리 소자의 구조를 나타내는 배치도이다.2 is a layout view illustrating a structure of a flash memory device according to an embodiment of the present invention.

도 2를 참조하면, 플래시 메모리 소자의 메모리 셀 영역을 A 셀 영역(11), B 셀 영역(12), C 셀 영역(13), D 셀 영역(14)으로 나누어 배치한다. 또한 A 셀 영역(11), B 셀 영역(12), C 셀 영역(13), D 셀 영역(14)의 특성에 맞는 제어 회로 즉, 논리 블락(15), 고전압 블락(16), 아날로그 블락(17)을 배치한다. 이는 A 셀 영역(11), B 셀 영역(12), C 셀 영역(13), D 셀 영역(14)에서 사용되는 전력에 맞도록 배치한다.Referring to FIG. 2, a memory cell region of a flash memory device is divided into an A cell region 11, a B cell region 12, a C cell region 13, and a D cell region 14. In addition, a control circuit suitable for the characteristics of the A cell region 11, the B cell region 12, the C cell region 13, and the D cell region 14, that is, the logic block 15, the high voltage block 16, and the analog block. (17) is placed. This is arranged to match the power used in the A cell region 11, the B cell region 12, the C cell region 13, and the D cell region 14.

이는 각 플래시 메모리 소자의 동작에 적합한 영역으로 나누기 위함이다. 즉, 프로그램 동작, 검증 동작, 소거 동작에 따라 다수의 블럭으로 나누어 배치한다. 이는 다양한 특성(PVT)을 가지는 메모리 셀들을 세분화하여 동작별로 운용되도록 하기 위함이다. 따라서 메모리 성능면에서 전력 소모를 줄일 수 있다.This is to divide into areas suitable for the operation of each flash memory device. That is, it is divided into a plurality of blocks according to a program operation, a verify operation, and an erase operation. This is to subdivide memory cells having various characteristics (PVT) to operate for each operation. Therefore, power consumption can be reduced in terms of memory performance.

상기에서 설명한 본 발명의 기술적 사상이 바람직한 실시예에서 구체적으로 기술되었으나, 상기한 실시예는 그 설명을 위한 것이며 그 제한을 위한 것이 아님을 주의하여야 한다. 또한, 본 발명은 본 발명의 기술 분야의 통상의 전문가라면 본 발명의 기술적 사상의 범위 내에서 다양한 실시예가 가능함을 이해할 수 있을 것이다.Although the technical spirit of the present invention described above has been described in detail in a preferred embodiment, it should be noted that the above embodiment is for the purpose of description and not of limitation. In addition, the present invention will be understood by those skilled in the art that various embodiments are possible within the scope of the technical idea of the present invention.

본 발명의 일실시 예에 따르면, 다수의 메모리 셀들을 셀 특성 즉, 프로그램, 독출, 소거 또는 다른 동작에 따른 특성별로 분리 배치하여 소자의 동작에 최적화된 메모리 영역으로 나누어 배치함으로써, 최소의 전력 소모만으로 최적의 메모리 동작을 수행할 수 있다.According to an embodiment of the present invention, a plurality of memory cells are separately arranged according to cell characteristics, that is, characteristics according to program, read, erase, or other operations, and divided into memory regions optimized for operation of the device, thereby minimizing power consumption. Only the optimal memory operation can be performed.

Claims (3)

다수의 메모리 셀들 중 동작 특성이 동일한 메모리 셀들이 동일한 영역으로 나뉘어 배치되는 A, B, C, D 메모리 셀 블럭; 및An A, B, C, D memory cell block in which memory cells having the same operation characteristics among a plurality of memory cells are divided into the same area; And 상기 A, B, C, D 메모리 셀 블럭 각각의 동작 특성에 따라 사용되는 전력을 제어하며, 상기 A, B, C, D 메모리 셀 블럭의 일측면에 배치되는 제어 블럭을 포함하는 플래시 메모리 소자의 배치 구조.A control unit of the flash memory device comprising a control block disposed on one side of the A, B, C, D memory cell block to control the power used according to the operating characteristics of each of the A, B, C, D memory cell block. Layout structure. 제 1 항에 있어서, 상기 A, B, C, D 메모리 셀 블럭은The method of claim 1, wherein the A, B, C, D memory cell block is 플래시 메모리 소자의 프로그램 동작, 독출 동작, 소거 동작, 검증 동작에 따라 나뉘어 배치되는 플래시 메모리 소자의 배치 구조.An arrangement structure of a flash memory device, which is divided according to a program operation, a read operation, an erase operation, and a verification operation of the flash memory device. 제 1 항에 있어서, 상기 제어 블락은The method of claim 1, wherein the control block is 메모리 셀의 PVT 특성에 따라 논리 블락, 고전압 블락, 및 아날로그 블락으로 나뉘어 배치되는 플래시 메모리 소자의 배치 구조.An arrangement structure of a flash memory device divided into a logic block, a high voltage block, and an analog block according to a PVT characteristic of the memory cell.
KR1020060042368A 2006-05-11 2006-05-11 Arrangement structure for flash memory device KR20070109429A (en)

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Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10067825B2 (en) 2015-09-14 2018-09-04 Samsung Electronics Co., Ltd. Memory device and method of controlling ECC operation in the same
US10529407B2 (en) 2017-07-20 2020-01-07 Samsung Electronics Co., Ltd. Memory device including a plurality of power rails and method of operating the same
US10535394B2 (en) 2017-07-20 2020-01-14 Samsung Electronics Co., Ltd. Memory device including dynamic voltage and frequency scaling switch and method of operating the same
US10607660B2 (en) 2017-07-20 2020-03-31 Samsung Electronics Co., Ltd. Nonvolatile memory device and operating method of the same

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10067825B2 (en) 2015-09-14 2018-09-04 Samsung Electronics Co., Ltd. Memory device and method of controlling ECC operation in the same
US10529407B2 (en) 2017-07-20 2020-01-07 Samsung Electronics Co., Ltd. Memory device including a plurality of power rails and method of operating the same
US10535394B2 (en) 2017-07-20 2020-01-14 Samsung Electronics Co., Ltd. Memory device including dynamic voltage and frequency scaling switch and method of operating the same
US10607660B2 (en) 2017-07-20 2020-03-31 Samsung Electronics Co., Ltd. Nonvolatile memory device and operating method of the same

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