KR20070109029A - Semiconductor memory device - Google Patents

Abstract

A semiconductor memory device is provided to prevent bootstrapping due to coupling capacitance by supplying a bit line precharge voltage to a reference bit line for a constant time during a sensing operation of the semiconductor memory device. An equalization signal generation part(30) generates an equalization signal by inverting and delaying an inversion signal of the equalization signal. A precharge control part(40) supplies a bit line precharge voltage to one of a bit line and a bit bar line for a constant time during an active operation, by assembling a number of row address signals and the inversion signal of the equalization signal. A precharge part(50) is turned on by the equalization signal, and precharges the bit line and the bit bar line.

Description

Semiconductor Memory Device {SEMICONDUCTOR MEMORY DEVICE}

1 is a circuit diagram showing a semiconductor memory device according to the prior art.

2 is a circuit diagram illustrating a semiconductor memory device according to the present invention.

3 is a timing diagram showing an operation of a semiconductor memory device according to the present invention;

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device, and more particularly to a technique for controlling active and precharge operations in a memory product using a folded sense amplifier.

As semiconductor memory devices shrink, problems with bitline coupling have arisen. This bit line coupling is mainly caused by the narrowing of the bit line pairs, and is also caused by increasing the cell capacitance (Cs) and decreasing the bit line capacitance (Cb) to improve the refresh characteristics. .

1 is a circuit diagram illustrating a semiconductor memory device according to the prior art, and illustrates a semiconductor memory device having a folded bit line structure as an example.

The conventional semiconductor memory device includes a cell array unit 10 and a bit line precharge unit 20.

Here, the cell array unit 10 includes a plurality of cells 11 including cell transistors and capacitors. The bit line precharge unit 20 includes NMOS transistors N1 and N2. Here, the NMOS transistors N1 and N2 are connected in series between the bit line BL and the bit bar line / BL so that the equalization signal BLEQ is applied through the common gate terminal. The bit line precharge voltage VBLP is applied through the common drain terminals of the NMOS transistors N1 and N2.

The operation of the conventional semiconductor memory device having such a configuration will be described below.

First, when a precharge command is applied, the previously enabled word line WL is disabled, and the bit line BL and the bit bar line / BL are precharged to the bit line precharge voltage VBLP by the equalization signal BLEQ.

At this time, the bit line precharge voltage VBLP is a voltage having half the potential of the core voltage VCORE.

Next, when an active command is applied, the equalization signal BLEQ is turned low before the new wordline WL0 is enabled, thereby turning off the NMOS transistors N1 and N2 of the precharge unit 20, thereby turning off the bitline BL and bitbar. The line / BL is floating. Then, when word line WL0 is enabled, data of cell 11 connected to selected word line WL0 is loaded on bit bar line / BL.

At this time, the capacitance of the selected cell 11 capacitor is added to the capacitance of the bit bar line / BL to distribute charge. This causes a voltage difference of ΔV on the bit bar line / BL.

In the conventional semiconductor memory device, since the bit line BL and the bit bar line / BL are floating at the same time by the equalization signal BLEQ, bootstrapping occurs at all times, and charge is also introduced into the bit line BL, thereby providing a voltage of ΔV '. A difference occurs. As a result, a voltage difference of ΔV−ΔV ′ occurs between the bit line BL and the bit bar line / BL. Here, the value of ΔV 'becomes larger as the interval between the bit line BL and the bit bar line / BL becomes smaller.

Thereafter, the bit line sense amplifier (not shown) operates to sense and amplify the data carried on the bit bar line / BL and output it to the outside.

As such, ΔV ′ acts as a load during the sensing operation, thereby lowering the sensing margin.

SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and prevents bootstrapping due to coupling capacitance by supplying a bit line precharge voltage to a reference bit line for a predetermined time during a sensing operation of a semiconductor memory device. There is a purpose.

According to an aspect of the present invention, there is provided a semiconductor memory device including: an equalization signal generator configured to generate an equalization signal by applying an inversion signal of an equalization signal and delaying an inversion for a predetermined time; A precharge control unit receiving a plurality of row address signals and an inversion signal of the equalization signal and performing logical combination to supply a bit line precharge voltage to any one of a bit line and a bit bar line during an active operation for a predetermined time; And a precharge unit which is turned on by the equalization signal to precharge the bit line and the bit bar line.

Hereinafter, with reference to the accompanying drawings will be described in detail an embodiment of the present invention.

2 is a circuit diagram illustrating a semiconductor memory device according to the present invention.

The semiconductor memory device of the present invention includes a cell array unit 10, an equalization signal generator 30, a precharge control unit 40, and a precharge unit 50. Here, the precharge control unit 40 includes an address combination unit 41, a bit line precharge voltage supply control unit 43, and a bit line precharge voltage supply unit 45.

The cell array unit 10 includes a plurality of cells 11 formed of cell transistors and capacitors.

The equalization signal generator 30 includes inverters IV1 to IV3. The inverter IV1 receives the inversion signal / BLEQ of the equalization signal and inverts the output, the inverter IV2 receives the output of the inverter IV1 and inverts the output, and the inverter IV3 receives the output of the inverter IV2 and outputs the equalization signal BLEQ. That is, the equalization signal generator 30 includes an odd number of inverter chains and inverts the inversion signal / BLEQ of the equalization signal to output the equalization signal BLEQ.

The address combination unit 41 includes an exclusive or gate XOR. The exclusive OR gate XOR receives the address signals XA0 and XA1 in a row, and outputs an exclusive OR operation.

The bit line precharge voltage supply control unit 43 includes an inverter IV4 and an AND gate AND1 and AND2.

Here, the inverter IV4 receives the output of the exclusive OR gate XOR and inverts the output, and the AND gate AND1 receives and outputs the inversion signal / BLEQ of the exclusive OR gate XOR and the equalization signal, and outputs the AND operation. The AND gate AND2 receives and outputs the inverted signal / BLEQ of the output of the inverter IV4 and the equalization signal, and outputs the AND operation.

The bit line precharge voltage supply part 45 includes the PMOS transistors P1 and P2. Here, the PMOS transistor P1 is connected between the precharge unit 50 and the bit line precharge voltage VBLP applying terminal, and the output of the AND gate AND1 is applied through the gate terminal. In addition, the PMOS transistor P2 is connected between the precharge unit 50 and the bit line precharge voltage VBLP applying terminal, and an output of the AND gate AND2 is applied through the gate terminal.

The precharge unit 50 includes NMOS transistors N3 and N4. Here, the NMOS transistor N3 is connected between the bit line BL and the PMOS transistor P1 so that the equalization signal BLEQ is applied through the gate terminal. The NMOS transistor N4 is connected between the bit bar line / BL and the PMOS transistor P2 so that the equalization signal BLEQ is applied through the gate terminal.

An operation process of the semiconductor memory device of the present invention having such a configuration will be described below with reference to the timing diagram of FIG. 3.

First, when the precharge command PCG is applied, the inversion signal / BLEQ of the equalization signal is enabled after being delayed for a predetermined time in synchronization with the rising edge of the clock CLK.

As a result, the outputs of the AND gates AND1 and AND2 go low to turn on the PMOS transistors P1 and P2.

At this time, when the equalization signal BLEQ is enabled after a predetermined time delay by the inversion signal / BLEQ of the equalization signal, the NMOS transistors N3 and N4 are turned on, and the bit line precharge voltage VBLP is applied to the bit line BL and the bit bar line / BL. Is approved.

Then, when the active command ACT is applied, the inversion signal / BLEQ of the equalization signal is disabled after being delayed for a predetermined time in synchronization with the rising edge of the clock CLK.

At this time, one of the word lines WL0 to WL3 is selected according to the state of the row address signals XA0 and XA1. For example, if the row address signals XA0 and XA1 are '00', the word line WL0 is selected, and if it is '10', the word line WL1 is selected. Here, the case where the word line WL0 is selected will be described as an example.

As a result, the output of the AND gate AND1 becomes low, the output of the AND gate AND2 becomes high so that the PMOS transistor P1 is turned on, and the PMOS transistor is turned off.

At this time, since the NMOS transistors N3 and N4 are turned on, the bit line precharge voltage VBLP is applied to the bit line BL, and the bit bar line / BL is floating.

Then, when word line WL0 is enabled, data of the cell 11 connected to the selected word line WL0 is loaded on the bit bar line / BL so that the capacitance of the capacitor is added to the capacitance of the bit bar line / BL to distribute charge. This causes a voltage difference of ΔV on the bit bar line / BL.

Here, an example will be described in which a line in which charge distribution is not performed among the bit line BL and the bit bar line / BL is set as the reference bit line, and the data stored in the selected cell 11 is at a low level.

Then, after a predetermined time delay by the inversion signal / BLEQ of the equalization signal, the equalization signal BLEQ is disabled to turn off the NMOS transistors N3 and N4.

Thereafter, the bit line sense amplifier (not shown) operates to sense and amplify the data carried on the bit bar line / BL and output it to the outside.

Here, when the bit bar line / BL is floating, since the precharge voltage VBLP is applied to the bit line BL during the T1 period, a bootstrapping operation is not generated. Thus, as in the prior art, the bit line BL and the bit bar line / BL are simultaneously floated to prevent the charge from flowing into the bit line BL, thereby ensuring a sensing margin.

As described above, in the semiconductor memory device of the present invention, a sensing margin can be secured by supplying a bit line precharge voltage to a reference bit line for a predetermined time to prevent bootstrapping due to coupling capacitance. Provide effect.

In addition, a preferred embodiment of the present invention is for the purpose of illustration, those skilled in the art will be able to various modifications, changes, substitutions and additions through the spirit and scope of the appended claims, such modifications and changes are the following claims It should be seen as belonging to a range.

Claims (7)

An equalization signal generator that receives an inversion signal of the equalization signal and generates an equalization signal by delaying inversion for a predetermined time; A precharge controller configured to receive a plurality of row address signals and inverted signals of the equalization signal and logically combine the same to supply a bit line precharge voltage to any one of a bit line and a bit bar line during an active operation; And A precharge unit which is turned on by the equalization signal to precharge the bit line and the bit bar line A semiconductor memory device comprising a. The semiconductor memory device of claim 1, wherein the precharge controller is configured to apply the bit line precharge voltage to a reference bit line in which charge distribution is not performed between the bit line and the bit bar line. The method of claim 1, wherein the precharge control unit An address combination unit which receives the plurality of row address signals and logically combines them and outputs them A bit line precharge voltage supply controller configured to receive the output of the address combination unit and the inverted signal of the equalization signal and logically combine and output the received signal; And A bit line precharge voltage supply unit supplying the bit line precharge voltage to the bit line and the bit bar line according to an output of the precharge voltage supply controller A semiconductor memory device comprising a. The semiconductor memory device of claim 3, wherein the address combination unit comprises an exclusive ora gate configured to receive the plurality of row address signals and perform an exclusive ora operation to output the oracle. The method of claim 3, wherein the bit line precharge voltage supply control unit A first inverter receiving the output of the address combination unit and inverting the output; A first AND gate receiving and outputting the output of the address combination unit and an inverted signal of the equalization signal and outputting the AND; And A second AND gate that receives and outputs the output of the first inverter and the inverted signal of the equalization signal, and outputs the AND; A semiconductor memory device comprising a. The method of claim 5, wherein the bit line precharge voltage supply unit A first driving element enabled by the output of the first AND gate to supply the bit line precharge voltage to the bit line; And A second driving element enabled by an output of the second and gate to supply the bit line precharge voltage to the bit bar line A semiconductor memory device comprising a. The semiconductor memory device of claim 1, wherein the equalization signal generator comprises an inverter chain configured to delay an inversion by receiving an inversion signal of the equalization signal.

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