KR20070109003A - Driving circuit for liquid crystal display device and method for driving the same - Google Patents

Abstract

A driving device for a liquid crystal display device and a driving method thereof are provided to maintain the quality of an image when changing a resolution by storing a Standard Pixel Per Inch to a EDID installed in the driving device and using the same. A driving device for a liquid crystal display device comprises a graphic card(150), an EDID(Extend Display Identification Data)(160), and a timing controller(140). The graphic card comprises a determining part(151), a synchronous signal generating part(152), and an image processing part(153). The determining part outputs a first selecting signal according to a resolution changing signal inputted from the outside. The synchronous signal generating part generates and outputs a synchronous signal according to a Standard Pixel Per Inch provided from the EDID. The image processing part arranges and outputs an image data according to the Standard Pixel Per Inch. The EDID provides the Standard Pixel Per Inch to the graphic card according to the first selecting signal. The timing controller generates a data controlling signal and a gate controlling signal and supplies them to a data driver and a gate driver by using the synchronous signal outputted from the graphic card.

Description

Driving device for liquid crystal display and driving method thereof {Driving circuit for liquid crystal display device and method for driving the same}

1 is a configuration diagram showing a driving device of a conventional liquid crystal display device.

2 is a block diagram showing a driving device of the liquid crystal display device according to the first embodiment of the present invention.

FIG. 3 is a diagram illustrating in detail the graphic card and the EDID illustrated in FIG. 2; FIG.

4A to 4C illustrate image display regions and non-display regions implemented in the liquid crystal display;

5 is a timing diagram for explaining a modulation method of a synchronization signal.

6 is a configuration diagram showing a driving device of a liquid crystal display according to a second embodiment of the present invention.

The present invention relates to a driving apparatus and a driving method of a liquid crystal display device capable of adjusting an image display area and maintaining an image quality while changing a resolution according to a user's convenience.

Recently, various flat panel display devices that can reduce weight and volume, which are disadvantages of cathode ray tubes, have emerged. Such flat panel displays include a liquid crystal display, a field emission display, a plasma display panel, a light emitting display, and the like.

Among the flat panel displays, a liquid crystal display includes a thin film transistor (TFT), which is a plurality of pixel electrodes disposed in a pixel region defined by a plurality of data lines and a plurality of gate lines, and a switch element at each pixel electrode. ) And a color filter substrate on which a color filter is formed are maintained at regular intervals and includes a liquid crystal layer formed therebetween.

1 is a configuration diagram showing a driving device of a conventional liquid crystal display.

As shown in FIG. 1, a driving device of a liquid crystal display includes a liquid crystal display including n gate lines GL1 to GLn and m data lines DL1 to DLm that are arranged to cross each other to define a pixel area. (2), a data driver 4 for supplying an analog video signal to the data lines DL1 to DLm, a gate driver 6 for supplying scan pulses to the gate lines GL1 to GLn, The image data RGB inputted from the outside is arranged and supplied to the data driver 4, the data control signal DCS is generated to control the data driver 4, and the gate control signal GCS is generated. The timing controller 8 which controls the driver 6 is provided.

The liquid crystal display 2 includes a transistor array substrate and a color filter array substrate bonded to each other, a spacer for maintaining a constant cell gap between the two array substrates, and a liquid crystal space provided by the spacer. With filled liquid crystal.

The liquid crystal display 2 includes a TFT formed in a pixel region where the n gate lines GL1 through GLn and the m data lines DL1 through DLm cross each other, and pixel electrodes connected to the TFT. The TFT supplies a data signal from the data lines DL1 to DLm to the pixel electrode in response to a scan pulse from the gate lines GL1 to GLn. The pixel electrode forms a liquid crystal capacitor Clc facing the common electrode with a liquid crystal interposed therebetween, and overlaps the previous gate lines GL1 to GLn to form a storage capacitor Cst. The liquid crystal capacitor Clc and the storage capacitor Cst maintain a data signal applied to the pixel electrode until a next data signal is applied.

The timing controller 8 arranges the source data RGB input from the outside to be suitable for driving the liquid crystal display 2 and supplies the source data RGB to the data driver 4. In addition, the timing controller 8 uses the main clock DCLK, the data enable signal DE, and the horizontal and vertical synchronization signals Hsync and Vsync, which are input from the outside, to the data control signal DCS and the gate control signal. (GCS) is generated to control the driving timing of each of the data driver 4 and the gate driver 6.

The gate driver 6 sequentially generates a scan pulse, that is, a gate high pulse, in response to a gate start pulse GSP and a gate shift clock GSC of the gate control signal GCS from the timing controller 8. It contains a shift register. The gate driver 6 sequentially supplies a gate high pulse to the gate lines GL1 to GLn of the liquid crystal display 2 to turn on the plurality of TFTs connected to the gate lines GL1 to GLn. do.

The data driver 4 converts the data signal Data arranged from the timing controller 8 into an analog image signal according to the data control signal DCS supplied from the timing controller 8, and converts the data signal into an analog image signal. In synchronism, an analog image signal corresponding to one horizontal line is supplied to the data lines DL1 through DLm every horizontal period in which scan pulses are supplied to the gate lines GL1 through GLn.

However, the conventional liquid crystal display and the driving method thereof driven as described above have the following problems.

In the conventional liquid crystal display, when the image is changed from the optimal resolution according to the size of the image display unit 2 to a resolution of another size, the image quality of the displayed image is deteriorated. That is, when the resolution of 1024x768, which is optimally used in the 17-inch image display unit, is changed to 800x600 resolution, the analog image signal is distorted and the image quality of the displayed image is degraded.

The present invention is to solve the above problems, by using the resolution information (Standard Pixel Per Inch) stored in the EDID (Extended Display Identification Data) provided in the drive device of the liquid crystal display, according to the user's convenience SUMMARY OF THE INVENTION An object of the present invention is to provide a driving apparatus and a driving method of a liquid crystal display device capable of adjusting an image display area while maintaining a resolution and maintaining image quality.

The driving device of the liquid crystal display according to the embodiment of the present invention for achieving the above object is to receive the resolution information by outputting the first selection signal in accordance with the resolution change signal input from the outside, the synchronization according to the resolution information A data control signal using a graphics card for outputting a signal, an extended display identification data (EDID) for providing resolution information to the graphics card according to the first selection signal, and a synchronization signal output from the graphics card; And a timing controller which generates a gate control signal and supplies the gate control signal to the data driver and the gate driver.

A method of driving a liquid crystal display according to an exemplary embodiment of the present invention for achieving the above object includes storing a plurality of resolution information, and selecting one of the plurality of resolution information according to a resolution change signal input from an external device. Generating and outputting a first selection signal; generating and outputting a synchronization signal using resolution information corresponding to the first selection signal; and using an synchronization signal generated according to the resolution information. And displaying the data.

Hereinafter, a driving apparatus and a driving method of a liquid crystal display according to an exemplary embodiment of the present invention having the above characteristics will be described in detail with reference to the accompanying drawings.

2 is a configuration diagram illustrating a driving device of a liquid crystal display according to a first embodiment of the present invention.

As shown in FIG. 2, the driving apparatus of the liquid crystal display according to the exemplary embodiment of the present invention includes n gate lines GL1 to GLn and m data lines (arranged in directions perpendicular to each other to define a pixel area). A liquid crystal display 110 having DL1 to DLm, a data driver 120 for supplying an image data signal to the data lines DL1 to DLm, and a scan pulse to the gate lines GL1 to GLn. A gate driver 130 for supplying a signal and outputting a first selection signal CS1 according to a resolution change signal CSet input from the outside, and receiving the resolution information SPPI to synchronize according to the resolution information SPPI. The graphics card 150 generating and outputting signals Hsync1, Vsync1, DE1, and DCLK1, and the EDID 160 providing resolution information SPPI to the graphics card 150 according to the first selection signal CS1. ) And inputted from the graphics card 150 The timing controller 140 generates the data control signal DCS and the gate control signal GCS by using the synchronization signals Hsync1, Vsync1, DE1, and DCLK1 to control the data driver 120 and the gate driver 130. ) Is configured.

The liquid crystal display 110 includes a thin film transistor TFT formed in each pixel area defined by the n gate lines GL1 through GLn and the m data lines DL1 through DLm, and the thin film transistor TFT. It is connected to the pixel electrode for driving a liquid crystal molecule. The thin film transistor TFT supplies a data signal from the data lines DL1 to DLm to the pixel electrode in response to a scan pulse from the gate lines GL1 to GLn. The pixel electrode faces the common electrode with a liquid crystal interposed therebetween to form a liquid crystal capacitor Clc, and overlaps the previous gate lines GL1 to GLn to form a storage capacitor Cst. The liquid crystal capacitor Clc and the storage capacitor Cst maintain a data signal applied to the pixel electrode until the next data signal is charged.

The graphic card 150 outputs a first selection signal CS1 to the EDID 160 according to a resolution change signal CSet input from the outside, and outputs the EDID 160 from the EDID 160 to the first selection signal CS1. It is provided with the resolution information (SPPI) according to. As a synchronization signal according to the received resolution information SPPI, a timing-modulated main clock DCLK1, a data enable signal DE1, and horizontal and vertical synchronization signals Hsync1 and Vsync1 are generated and output.

The timing controller 140 arranges the image data RGB supplied from the graphic card 150 to match the driving of the liquid crystal display 110 (MRGB) and supplies the image data RGB to the data driver 120. In addition, the data control signal DCS and the gate control signal GCS are generated using the synchronization signals DCLK1, DE1, Hsync1, and Vsync1 input from the graphics card 150 to generate the data driver 120 and the gate. The driving timing of each driver 130 is controlled.

The gate driver 130 sequentially generates scan pulses, that is, gate high pulses, in response to the gate start pulse GSP and the gate shift clock GSC of the gate control signal GCS from the timing controller 140. Contains shift registers. The thin film transistor TFT is turned on in response to the scan pulse.

The data driver 120 converts the image data MRGB arranged from the timing controller 140 into an image data signal, which is an analog signal, according to the data control signal DCS supplied from the timing controller 140. An image data signal for one horizontal line is supplied to the data lines DL1 to DLm every one horizontal period in which scan pulses are supplied to the lines GL1 to GLn. That is, the data driver 120 selects a gamma voltage having a predetermined level according to the gray level values of the aligned image data MRGB, and supplies the selected gamma voltage to the data lines DL1 to DLm.

FIG. 3 is a diagram illustrating in detail the graphic card and the EDID illustrated in FIG. 2.

As shown in FIG. 3, the graphics card 150 includes a determination unit 151 for outputting a first selection signal CS1 according to a resolution change signal CSet input from an external device, and the first selection signal ( Sync to supply the resolution information SPPI input according to CS1 to the image processor 153 and to generate and output the synchronization signals Hsync1, Vsync1, DE1, and DCLK1 having a timing corresponding to the resolution information SPPI. And a signal generating unit 152 and an image processing unit 153 for sorting and outputting the image data RGB according to the resolution information SPPI.

The EDID 160 includes a display information storage area 161 storing display information of a liquid crystal display and a lookup table area 162 storing the resolution information SPPI.

The determination unit 151 generates the first selection signal CS1 according to the resolution change signal CSet input from the outside and outputs the first selection signal CS1 to the EDID 160. The first selection signal CS1 is an address value of the lookup table area 162 included in the EDID 160.

The synchronization signal generator 152 supplies the resolution information SPPI input from the EDID 160 to the image processor 153 and has synchronization timing signals Hsync1 and Vsync1 having a timing according to the resolution information SPPI. , DE1, DCLK1) is generated and output.

The image processor 153 rearranges and outputs the image data RGB according to the resolution information SPPI input from the synchronization signal generator 152.

The display information storage area 161 of the EDID 160 stores a data format provided by the Video Eletronics Standards Association (VESA) and sets data values in the lookup table area 162.

The look-up table area 162 stores an area of resolution information SPPI, and typically, resolution information having sizes of 640 × 480, 800 × 600, 960 × 600, 1024 × 768, 1280 × 800, and 1400 × 1050. Including SPPI), arbitrarily designated resolution information SPPI may be stored according to a user's convenience.

4A through 4C are diagrams illustrating an image display area and a non-display area implemented in the liquid crystal display.

The image display area illustrated in FIG. 4A is a case where the resolution is changed smaller than the size of the liquid crystal display 110 and the image display area is set to be positioned at the center of the liquid crystal display 110. For example, the display device displays a resolution of 640 × 480 or 800 × 600 in a 17 inch (17 inch) liquid crystal display, and the image display area is set to be positioned at the center of the liquid crystal display.

4B illustrates a case in which the resolution is changed to a quarter size smaller than the size of the liquid crystal display 110, and the image display area is set to be biased at one lower end of the liquid crystal display 110. This is a case where the resolution is changed to 1/8 size smaller than the size of the liquid crystal display 110 and the image display area is set to be biased to the lower end of the other side of the liquid crystal display 110.

As shown in FIGS. 4A to 4C, the operation of adjusting the resolution of the image display area and setting the display position includes receiving the resolution information (SSPI) stored in the lookup table area 162 and thus receiving a synchronization signal ( By generating the Hsync1, Vsync1, DE1, DCLK1, and driving the liquid crystal display 110 using the synchronization signals (Hsync1, Vsync1, DE1, DCLK1). Here, the generation method of the synchronization signals Hsync1, Vsync1, DE1, and DCLK1 will be described in detail.

5 is a timing diagram for explaining a modulation method of a synchronization signal.

As shown in FIG. 5, the synchronization signals Hsync1, Vsync1, DE1, and DCLK1 may be generated by modulating the timing of the synchronization signals Hsync, Vsync, DE, and DCLK with respect to image data of a previous resolution. That is, the vertical portion of the image display area may be adjusted by adjusting the driving timing of the data enable signal DE and the vertical synchronization signal Vsync, and the data enable signal DE and the horizontal synchronization signal ( Hsync) can be adjusted to adjust the horizontal portion of the image display area.

Specifically, the Vfp (Vertical Front Porch) section shown in FIG. 5 shows timings between the end of the data enable signal DE and the start of the vertical synchronization signal Vsync. Indicates an interval. The vertical back porch (Vbp) section shows timings between the end of the vertical synchronization signal Vsync and the start of the data enable signal DE, and represents the section “B” of FIG. 4A.

A horizontal front porch (Hfp) section shown in FIG. 5 shows timings between a start portion of the data enable signal DE and an end portion of the horizontal sync signal Hsync, and represents a section “C” of FIG. 4A. . In addition, the horizontal back porch (Hbp) section indicates timing of a portion where the horizontal synchronization signal Hsync is not synchronized with the data enable signal DE, and represents the section “D” of FIG. 4A.

The Vsw (Vertical Sync Width) section shown in FIG. 5 is an area in which an image is displayed by synchronizing the data enable signal DE with the vertical sync signal Vsync. The section "A" and "B" shown in FIG. "Represents the interregion of a section. In addition, the horizontal sync width (Hsw) is an area in which an image is displayed by synchronizing the data enable signal DE with the horizontal sync signal Hsync. The interval between the "C" section and the "D" section shown in FIG. Represents an area.

That is, as a method of changing the driving timing of the synchronization signals Hsync, Vsync, DE, and DCLK with respect to the previous resolution according to the resolution information SPPI, more precisely, Vfp timing, Vbp timing, Hfp timing, and Hbp timing It modulates the Vsw timing and Hsw timing in which the image is displayed accordingly.

The driving method of the liquid crystal display according to the exemplary embodiment of the present invention configured as described above is as follows.

First, the resolution information SPPI is stored in the lookup table area 162 of the EDID 160. That is, the information about the image display area is stored in advance so that the user can display the image display area having a desired resolution at a desired position according to the resolution change signal CSet input from the outside. Thereafter, when the first selection signal CS1 corresponding to the resolution change signal CSet input from the outside, that is, the address value of the lookup table area 162 is transmitted to the EDID 160, the EDID 160 is transmitted. The resolution information SPPI stored in the lookup table area 162 is supplied to the synchronization signal generator 152 according to the first selection signal CS1.

The synchronization signal generator 152 supplies the received resolution information SPPI to the image processor 153 and simultaneously generates the synchronization signals Hsync1, Vsync1, DE1, and DCLK1 having a timing corresponding to the resolution information SPPI. It generates and transmits to the timing controller 140. Here, the synchronization signals Hsync1, Vsync1, DE1, and DCLK1 are signals in which the Vsw timing and the Hsw timing are modulated by adjusting the Vfp timing, the Vbp timing, the Hfp timing, and the Hbp timing as described above.

The image processor 153 arranges the image data RGB according to the resolution information SPPI and provides the image data RGB to the timing controller 140, and the timing controller 140 supplies an image supplied from the image processor 153. The data RGB is aligned to match the driving of the liquid crystal display 110 and supplied to the data driver 120. In addition, the data driver 120 and the gate driver 130 are driven by generating a data control signal DCS and a gate control signal GCS using the synchronization signals Hsync1, Vsync1, DE1, and DCLK1. By controlling the timing, an image is displayed on the liquid crystal display 110.

 Accordingly, the liquid crystal display according to the embodiment of the present invention stores and uses the resolution information SPPI in the EDID 160, thereby adjusting the image display area while changing the resolution according to the user's convenience, and improving the quality of the image. I can keep it.

FIG. 6 illustrates a driving device of the liquid crystal display according to the second embodiment of the present invention. As shown in FIG. 6, the driving device of the liquid crystal display according to the second embodiment of the present invention includes image data RGB. ) And outputs the second selection signal CS2 according to the resolution change signal CSet input from the graphics card 250 for generating and outputting the synchronization signals Hsync, Vsync, DE, and DCLK. A timing controller 240 receiving information SPPI and modulating and outputting the synchronization signals Hsync, Vsync, DE, and DCLK according to the resolution information, and the timing controller according to the second selection signal CS2. And an EDID 260 that provides resolution information SPPI to 240.

The graphic card 250 includes an image data supply unit 251 for supplying image data RGB, and synchronization signals Hsync and Vsync for controlling driving timings of the data driver 120 and the gate driver 130, respectively. And a synchronization signal generation unit 252 for generating DE, DCLK).

The timing controller 240 includes a determination unit 241 for outputting a second selection signal CS2 according to a resolution change signal CSet input from the outside, and the synchronization signal generation unit 252 according to the resolution information SPPI. A synchronization signal converting unit 242 for modulating and outputting the synchronization signals Hsync, Vsync, DE, and DCLK inputted from the signal; and an image processing unit for rearranging and outputting image data RGB according to the resolution information SPPI 243 and a control signal generator 244 for generating and outputting each control signal DCS and GCS according to the modulated synchronization signals Hsync1, Vsync1, DE1, and DCLK1 received from the synchronization signal converter 242. ) Is configured to include.

The EDID 260 includes a display information storage area 261 storing display information of the liquid crystal display and a lookup table area 262 storing the resolution information SPPI.

The determination unit 241 included in the timing controller 240 outputs the second selection signal CS2 to the EDID 260 according to a resolution change signal CSet input from the outside. The second selection signal CS2 is an address value of the lookup table area 262 provided in the EDID 260.

The sync signal converter 242 supplies the resolution information SPPI input from the EDID 260 to the image processor 243 and sync signals Hsync and Vsync input from the sync signal generator 252. , DE, and DCLK) are modulated and transmitted to the control signal generator 244.

The image processor 243 realigns the image data RGB according to the resolution information SPPI input from the synchronization signal converter 242 and supplies the image data RGB to the data driver 120.

The display information storage area 261 stores a data format provided by the Video Eletronics Standards Association (VESA) and sets data values in the lookup table area 262.

The look-up table area 262 stores the resolution information SPPI, and the synchronization signal generation unit receives the resolution information SPPI according to the second selection signal CS2 input from the determination unit 241. To 252.

A driving method of the liquid crystal display device including the timing controller 240 and the EDID 260 having the above configuration is as follows.

First, the resolution information SPPI is stored in the EDID 260. That is, the resolution information SPPI of the image display area is stored in advance so that the image displayed according to the resolution change signal CSet input from the outside can be displayed at a desired position. Thereafter, when the second selection signal CS2 according to the resolution change signal CSet input from the outside is transmitted to the EDID 260, the resolution information stored in the lookup table area 262 of the EDID 260 SPPI is supplied to the synchronization signal converter 242 according to the second selection signal CS2.

The sync signal converter 242 supplies the received resolution information SPPI to the image processor 243 and at the same time the sync signal Hsync transmitted from the sync signal generator 252 according to the resolution information SPPI. , Vsync, DE, and DCLK are modulated and transmitted to the control signal generator 244. Here, the modulation method of the synchronization signal (Hsync, Vsync, DE, DCLK), as shown in Figure 6, by adjusting the Vfp timing, Vbp timing, Hfp timing, and Hbp timing modulated Vsw timing and Hsw timing will be.

The image processor 243 arranges the image data RGB to be suitable for driving the liquid crystal display 110 according to the resolution information SPPI and supplies the same to the data driver 120. In addition, the control signal generator 244 uses the modulated sync signals Hsync1, Vsync1, DE1, and DCLK1 transmitted from the sync signal generator 252 to control the data control signal DCS and the gate control signal ( By generating a GCS to control driving timing of each of the data driver 120 and the gate driver 130, an image is displayed on the liquid crystal display 110.

The timing controller 240 shown in FIG. 6 has resolution information from the determination unit 241 and the EDID 260 which outputs the second selection signal CS2 according to a resolution change signal CSet input from the outside. The sync signal converter 242 is provided to receive the SPPI and output modulated sync signals Hsync1, Vsync1, DE1, and DCLK1. Therefore, even in a product in which the graphic card 250 is not built-in in a driving device of a liquid crystal display device such as a notebook computer, the displayed image can be displayed at a desired position at a desired resolution regardless of the function of the graphic card 250. Can be.

The present invention described above is not limited to the above-described embodiment and the accompanying drawings, it is conventional in the art that various substitutions, modifications and changes are possible without departing from the technical spirit of the present invention. It will be evident to those who have knowledge of.

As described above, the driving apparatus and the driving method of the liquid crystal display according to the present invention have the following effects.

The present invention stores and uses the resolution information (Standard Pixel Per Inch) in the EDID (Extended Display Identification Data) provided in the driving device of the liquid crystal display device, thereby adjusting the image display area while changing the resolution according to the user's convenience, The quality of the image can be maintained.

Claims (18)

A graphics card configured to output a first selection signal according to a resolution change signal input from an external device, receive resolution information, and generate and output a synchronization signal according to the resolution information; Extended Display Identification Data (EDID) for providing resolution information to the graphics card according to the first selection signal; And, And a timing controller for generating a data control signal and a gate control signal using the synchronization signal output from the graphic card and supplying the data control signal and the gate control signal to the data driver and the gate driver. The method of claim 1, The graphic card may include a determination unit for outputting a first selection signal according to a resolution change signal input from an external device; A synchronization signal generator for generating and outputting a synchronization signal according to the resolution information supplied from the EDID; And, And an image processor for sorting and outputting image data according to the resolution information. The method of claim 2, And the synchronizing signal generating unit supplies the resolution information inputted from the EDID to the image processing unit and simultaneously generates and outputs a synchronizing signal according to the resolution information. The method of claim 3, wherein And a synchronization signal generated according to the resolution information is a signal generated by converting a timing of a data enable signal, a horizontal synchronization signal, and a vertical synchronization signal. The method of claim 1, And the EDID includes a display information storage area storing display information of a product and a look-up table area storing the resolution information. The method of claim 5, And a first selection signal output from the determination unit is an address value of a lookup table area included in the EDID. A graphics card for generating and outputting image data and a synchronization signal; A timing controller configured to output a second selection signal according to a resolution change signal input from the outside to receive resolution information, and to modulate and output the input synchronization signal accordingly; And an EDID for providing resolution information to the timing controller according to the second selection signal. The method of claim 7, wherein The timing controller may include a determination unit configured to output a second selection signal according to a resolution change signal input from an external device; A synchronization signal converter for modulating and outputting an input synchronization signal according to the resolution information; An image processor for sorting and outputting image data according to the resolution information; And, And a control signal generator for generating and outputting a control signal according to the modulated synchronization signal. The method of claim 8, And the synchronizing signal converter supplies the resolution information input from the EDID to the image processing unit and modulates and outputs the synchronizing signal input according to the resolution information. The method of claim 7, wherein And the EDID includes a display information storage area storing display information of a product and a look-up table area storing the resolution information. The method of claim 10, And wherein the second selection signal is an address value of a look-up table area provided in the EDID. The method of claim 10, And wherein the modulated synchronous signal is a signal whose timing of a data enable signal, a horizontal synchronous signal, and a vertical synchronous signal is modulated. Storing a plurality of resolution information; Generating and outputting a first selection signal for selecting one of the plurality of resolution information according to a resolution change signal input from an external device; Generating and outputting a synchronization signal using resolution information corresponding to the first selection signal; And, And displaying the image data using the synchronization signal generated according to the resolution information. The method of claim 13, And the first selection signal is an address value of a location where one of the plurality of resolution information is stored. The method of claim 13, And a synchronization signal generated according to the resolution information is a signal obtained by modulating a timing of a data enable signal, a horizontal synchronization signal, and a vertical synchronization signal. Storing a plurality of resolution information; Generating and outputting a second selection signal for selecting one of the plurality of resolution information according to a resolution change signal input from an external device; Modulating and outputting an input synchronization signal using resolution information corresponding to the second selection signal; And, And displaying the image data by using the modulated synchronization signal. The method of claim 16, And the second selection signal is an address value of a location where one of the plurality of resolution information is stored. The method of claim 16, And wherein the modulated synchronous signal is a signal in which the timing of a data enable signal, a horizontal synchronous signal, and a vertical synchronous signal is modulated.

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