KR20070108560A - Memory cell data reading circuit, memory circuit, and memory cell data reading method - Google Patents

Abstract

A memory cell data reading circuit comprising a judgment circuit (3) that reads a plurality of data from multiplexed memory cells (5) the data inverting directions of which are univocal, and that, if different data are existent in the read data, judges the data, which has not been inverted in accordance with the data inverting direction, as legal data stored in the memory cells (5); and an output part (4) that outputs, as data stored in the memory cells, the data that is judged as the legal data by the judgment circuit (3).

Description

Data reading circuit of memory cell, memory circuit, data reading method of memory cell {MEMORY CELL DATA READING CIRCUIT, MEMORY CIRCUIT, AND MEMORY CELL DATA READING METHOD}

The present invention relates to a data readout circuit of a memory cell, a memory circuit, and a data readout method of a memory cell for performing error correction for soft errors in the memory cell.

In recent memory devices, process miniaturization, an increase in capacity, and a decrease in voltage are in progress. With this flow, the soft error rate tends to increase, which is a problem. Here, the soft error is an error generated by the influence of the environment, such as neutron beams, unlike a hard error that cannot be used due to a physical failure or the like.

In the conventional memory device, countermeasures such as error detection by redundancy or parity check, or error correction by a majority vote determination circuit or an ECC circuit have been taken against this soft error.

Moreover, patent document 1 shown below is known as a prior art which concerns on this invention, for example. The semiconductor memory to which this error correction function is added corrects an error of a memory cell by using a memory cell array unit having three or more odd memory cells and a majority decision circuit for each memory cell array unit.

Patent Document 1: Japanese Patent Application Laid-Open No. 6-52697

However, error detection alone cannot correct the error. In addition, in order to perform error correction, a complicated circuit for error correction is required. For example, the semiconductor memory to which the error correction function of Patent Document 1 is added requires a memory cell array section having three or more odd memory cells and a majority decision circuit for each memory cell array section.

SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and an object of the present invention is to provide a data reading circuit of a memory cell, a memory circuit, and a data reading method of a memory cell capable of correcting an error of the memory cell without using a complicated circuit. do.

MEANS TO SOLVE THE PROBLEM In order to solve the above-mentioned subject, this invention is a data reading circuit of the memory cell which reads the data of a memory cell, Comprising: A plurality of data is read from the multiplexed memory cell in which the data reversal direction of a memory cell is uniform, When there is other data, a judgment circuit for judging data when not inverted in accordance with the data reversal direction as legitimate data stored in the memory cell, and data judged as legitimate data by the judging circuit are stored in the memory cell. It includes an output unit that outputs data.

Further, in the data readout circuit of the memory cell according to the present invention, if the data read out from the multiplexed memory cell are all the same, data of any one of the multiplexed memory cells is stored in the memory cell. It is characterized by judging as legitimate data.

Further, in the data read circuit of the memory cell according to the present invention, the decision circuit is an OR circuit.

In addition, the present invention is a memory circuit having a multiplexed memory cell in which the data inversion direction of the memory cell is uniform, and reads a plurality of data from the multiplexed memory cell, and when there is other data among the read data, the data And a determination circuit for judging data when not inverted in accordance with the inversion direction as legitimate data stored in the memory cell, and an output unit for outputting data judged as legitimate data by the judging circuit as memory data of the memory cell.

Further, in the memory circuit according to the present invention, when the data read from the multiplexed memory cells are all the same, the judgment circuit judges any one of the multiplexed memory cells as valid data stored in the memory cell. It is characterized by.

Further, in the memory circuit according to the present invention, a multiplicity setting unit for selectively setting the multiplicity of the multiplexed memory cells, wherein the determination circuit includes all the memory cells selectively multiplexed by the multiplicity setting unit The determination is made by reading data from the data.

In the memory circuit according to the present invention, the determination circuit is an OR circuit.

In addition, the present invention provides a data read method of a memory cell for reading data of a memory cell, wherein a plurality of data is read from a multiplexed memory cell in which the data reversal direction of the memory cell is uniform, and there is other data among the read data. The judgment step of judging data in the case of not inverting according to the data inversion direction as legitimate data stored in a memory cell, and an output for outputting data judged as legitimate data by the judging circuit as memory data of the memory cell. To execute the steps.

Further, in the data reading method of the memory cell according to the present invention, if the data read from the multiplexed memory cell are all the same, data of any one of the multiplexed memory cells is stored in the memory cell. It is characterized by judging as legitimate data.

1 is a block diagram showing an example of a configuration of an embodiment of the present invention.

2 is a flowchart showing an example of a data reading operation in the embodiment of the present invention.

3 is a block diagram showing another example of the configuration of the embodiment of the present invention;

EMBODIMENT OF THE INVENTION Hereinafter, embodiment of this invention is described, referring drawings.

The memory cell represents the value of data by the amount of charge. In the present embodiment, the value of data in a state of high charge is set to "1" and the value of data in a state of low charge is set to "0" in the memory cell. The present invention is applied to a memory in which data reversal direction due to soft error of a memory cell is determined, such as DRAM (Dynamic Random Access Memory) or Flash RAM (Random Access Memory). In such a memory, a soft error in which data is inverted from a state of high charge to a state of charge occurs due to the movement of charges in a memory cell under the influence of neutron beams. That is, the inversion direction of the soft error in this embodiment is a direction from "1" to "0".

First, the structure of embodiment of this invention is demonstrated.

1 is a block diagram illustrating an example of a configuration of an embodiment of the present invention. This embodiment includes an input unit 1, a memory cell group 2, a determination circuit 3, and an output unit 4. The memory cell group 2 is a multiplex of two adjacent memory cells 5. The determination circuit 3 is provided with the memory cell group 2.

Next, operation | movement of embodiment of this invention is demonstrated.

First, the operation of data recording in the embodiment of the present invention will be described. The data input unit 1 transfers data to the indicated memory cell group 2 in accordance with an instruction of data writing from the outside. Data input to the memory cell group 2 is written like all the memory cells 5.

Next, the operation of reading data in the embodiment of the present invention will be described. 2 is a flowchart showing an example of the operation of reading data in the embodiment of the present invention. First, the determination circuit 3 reads data from all the memory cells 5 in the corresponding memory cell group 2 (S11). Next, the judgment circuit 3 judges whether or not the data from all the memory cells 5 are the same (S12). If the data is the same (S12, Y), the determination circuit 3 determines that there is no soft error, and determines the same data read from the memory cell group 2 as legitimate data (S13), and the process proceeds to process S15. On the other hand, when the data is different (S12, N), the determination circuit 3 determines that there is a soft error, corrects the error (S14), and proceeds to process S15. Here, the error correction is to determine the data in the case of not inverting in accordance with the inversion direction due to the soft error as legitimate data. Since the inversion direction in this embodiment is a direction from "1" to "0", it is judged that "0" is the result of inversion by a soft error among other data in the memory cell group 2, "1" is determined as legitimate data that does not invert. Such a determination circuit 3 can be realized by using an OR circuit, and can be realized on a very small circuit scale.

Next, the output part 4 outputs the legitimate data determined by the determination circuit 3 to the outside (S15), and complete | finishes this flow.

In the present embodiment, the multiplicity of the memory cells 5 in the memory cell group 2 is set to 2, but if there is room in the unused areas of the memory cells, the multiplicity is increased to allow more adjacent memories. The cell may be a memory cell group. According to this increase in the degree of multiplicity, the memory cells 5 of the memory cell group 2 become all errors, thereby reducing the cases in which the error cannot be corrected and improving the reliability.

In addition, depending on the number of unused areas of the memory cell and the required reliability, the multiplicity may be set by an instruction from the outside. 3 is a block diagram showing another example of the configuration of the embodiment of the present invention. In FIG. 3, the same code | symbol as FIG. 1 shows the same or same thing as the object shown in FIG. 1, and abbreviate | omits description here. Compared to FIG. 1, FIG. 3 includes an input unit 11 instead of the input unit 1, a determination circuit 13 instead of the determination circuit 3, and an output unit 14 instead of the output unit 4. And a multiplicity setting unit 16. The multiplicity setting section 16 sets a memory cell group multiplexed with any number of memory cells 5 according to an instruction from the outside. In data writing, the input unit 11 writes data in the memory cell group set by the multiplicity setting unit 16. At the time of data reading, the decision circuit 13 reads data from the memory cell group set by the multiplicity setting section 16 and performs the above-described data reading operation to determine valid data. The output unit 14 outputs valid data determined by the determination circuit 13 to the outside.

In addition, the determination step corresponds to the processes S11, S12, S13, and S14 in the embodiment. In addition, an output step corresponds to the process S15 in embodiment.

As described above, according to the present invention, error correction can be performed only by two or more memory cells and a very simple decision unit. As in the related art, error correction by majority vote requiring three or more memory cells and a majority decision determination unit or The circuit scale can be significantly reduced compared to error correction by ECC which requires a complicated calculation circuit.

Claims (9)

A data reading circuit of a memory cell for reading data of a memory cell, When a plurality of pieces of data are read from a multiplexed memory cell in which the data inversion direction of the memory cell is uniform, and if there is other data among the read data, data stored in the memory cell when not inverted in accordance with the data inversion direction is stored. A judgment circuit judging as legitimate data, And an output unit for outputting data judged as legitimate data by the determination circuit as storage data of the memory cell. The data determining apparatus of claim 1, wherein the determination circuit judges any one of the multiplexed memory cells as valid data stored in the memory cell when the data read out from the multiplexed memory cells are the same. Data readout circuit of the memory cell. 2. The data read circuit of claim 1, wherein the decision circuit is an OR circuit. A memory circuit having multiplexed memory cells in which the data reversal direction of the memory cells is uniform, A judging circuit that reads a plurality of data from the multiplexed memory cells, and judges the data in the case of not inverting in accordance with the data reversal direction as legitimate data stored in the memory cell when there is other data among the read data; , And an output unit for outputting data judged as valid data by the determination circuit as storage data of a memory cell. The data determining apparatus according to claim 4, wherein the determination circuit judges any one of the multiplexed memory cells as valid data stored in the memory cell when the data read out from the multiplexed memory cells are the same. Memory circuit. The apparatus of claim 4, further comprising a multiplicity setting unit for selectively setting a multiplicity of the multiplexed memory cells. And the judgment circuit reads out data from all memory cells selectively multiplexed by the multiplicity setting section and performs the judgment. 5. The memory circuit according to claim 4, wherein said determination circuit is an OR circuit. A data reading circuit of a memory cell for reading data of a memory cell, When a plurality of pieces of data are read from a multiplexed memory cell in which the data inversion direction of the memory cell is uniform, and if there is other data among the read data, data stored in the memory cell when not inverted in accordance with the data inversion direction is stored. A judgment step of judging as legitimate data, And an output step of outputting, as the stored data of the memory cell, data determined as legitimate data by the judgment circuit. 10. The method as claimed in claim 8, wherein the determining step judges that any one of the multiplexed memory cells is valid data stored in the memory cell when the data read from the multiplexed memory cells are the same. Method of reading data from a memory cell.

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