KR20070105139A - Method of manufacturing a nand type flash memory device - Google Patents

Method of manufacturing a nand type flash memory device Download PDF

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KR20070105139A
KR20070105139A KR1020060037222A KR20060037222A KR20070105139A KR 20070105139 A KR20070105139 A KR 20070105139A KR 1020060037222 A KR1020060037222 A KR 1020060037222A KR 20060037222 A KR20060037222 A KR 20060037222A KR 20070105139 A KR20070105139 A KR 20070105139A
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film
forming
memory device
flash memory
manufacturing
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KR1020060037222A
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Korean (ko)
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KR100833430B1 (en
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김남경
김세준
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주식회사 하이닉스반도체
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Priority to KR1020060037222A priority Critical patent/KR100833430B1/en
Priority to US11/618,702 priority patent/US7410881B2/en
Priority to TW096100035A priority patent/TWI341011B/en
Priority to CN2007100844503A priority patent/CN101030559B/en
Publication of KR20070105139A publication Critical patent/KR20070105139A/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76897—Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
    • H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
    • H01L21/28506—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
    • H01L21/28512—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic System
    • H01L21/28525—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic System the conductive layers comprising semiconducting material
    • H01L21/28531—Making of side-wall contacts

Abstract

A method for fabricating a NAND-type flash memory device is provided to reduce resistance of a drain contact plug and contact resistance by filling a conductive layer in a drain contact and etching a predetermined depth of the conductive layer and by sequentially forming a silicide layer and a metal layer in the etched region to form a drain contact plug. A plurality of gates are formed on a semiconductor substrate(100) and a junction region is formed on the semiconductor substrate between the gates. After a first interlayer dielectric(116) is formed on the resultant structure, a predetermined region of the first interlayer dielectric is etched to form a contact hole exposing the junction region. After a conductive layer(118) is formed in the contact hole, a predetermined depth of the conductive layer is etched. The conductive layer can be made of polysilicon, and the predetermined depth can be 500-5000 angstroms. A silicide layer(120) and a first metal layer(122) are sequentially formed in the etched region to form a contact plug. The silicide layer can be made of one of Ti, Co, Pt, Ir or Ru. After a second interlayer dielectric(124) is formed on the resultant structure, a predetermined region of the second interlayer dielectric is etched to expose the contact plug. A barrier metal layer(126) and a second metal layer(128) are sequentially formed on the resultant structure.

Description

ＮＡＮＤ형 플래쉬 메모리 소자의 제조 방법{Method of manufacturing a NAND type flash memory device}Method of manufacturing a NAND type flash memory device

도 1a 내지 도 1d는 본 발명의 일 실시 예에 따른 NAND형 플래쉬 메모리 소자의 제조 방법을 설명하기 위해 순서적으로 도시한 선택 트랜지스터 영역의 단면도.1A to 1D are cross-sectional views of select transistor regions sequentially shown for explaining a method of manufacturing a NAND type flash memory device according to an embodiment of the present invention.

<도면의 주요 부분에 대한 부호의 설명><Explanation of symbols for main parts of the drawings>

100 : 반도체 기판 102 : 터널 산화막100 semiconductor substrate 102 tunnel oxide film

104 : 제 1 폴리실리콘막 106 : 유전체막104: first polysilicon film 106: dielectric film

108 : 제 2 폴리실리콘막 110 : 텅스텐실리사이드막108: second polysilicon film 110: tungsten silicide film

112 : 하드마스크막 114 : 접합부112: hard mask film 114: junction

116 : 제 1 층간절연막 118 : 도전막116: first interlayer insulating film 118: conductive film

120 : 실리사이드막 122 : 제 1 금속막120: silicide film 122: first metal film

124 : 제 2 층간절연막 126 : 베리어 메탈막124: second interlayer insulating film 126: barrier metal film

128 : 제 2 금속막128: second metal film

본 발명은 NAND형 플래쉬 메모리 소자의 제조 방법에 관한 것으로, 특히 드레인 콘택에 도전막을 매립한 후, 상기 도전막을 소정깊이 식각한 다음, 식각된 영역에 실리사이드막과 금속막을 순차적으로 형성하여 드레인 콘택플러그를 형성함으로써, 드레인 콘택 플러그의 저항 및 접촉 저항을 감소시킬 수 있는 NAND형 플래쉬 메모리 소자의 제조 방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a NAND type flash memory device. In particular, after a conductive film is embedded in a drain contact, the conductive film is etched to a predetermined depth, and then a silicide film and a metal film are sequentially formed in the etched region to drain drain plug The present invention relates to a method for manufacturing a NAND type flash memory device capable of reducing the resistance and contact resistance of a drain contact plug.

종래의 NAND형 플래쉬 메모리 소자의 제조 방법을 간략히 설명한 후, 종래기술의 문제점을 도출한다.After briefly explaining a conventional method of manufacturing a NAND type flash memory device, problems of the prior art are derived.

셀 영역의 반도체 기판 상부에 터널 산화막, 제 1 폴리실리콘막, 유전체막, 제 2 폴리실리콘막, 텅스텐실리사이드막 및 하드마스크막이 적층되어 플로팅 게이트와 콘트롤 게이트가 적층된 게이트 전극이 형성됨과 동시에 선택 트랜지스터 영역에도 이와 동일한 적층 구조의 게이트 전극이 형성된다. 그리고, 이온 주입 공정을 실시하여 소오스 또는 드레인으로 작용하는 접합부를 형성한다.A tunnel oxide film, a first polysilicon film, a dielectric film, a second polysilicon film, a tungsten silicide film, and a hard mask film are stacked on the semiconductor substrate in the cell region to form a gate electrode in which a floating gate and a control gate are stacked. The gate electrode of the same laminated structure is also formed in the region. An ion implantation step is then performed to form a junction that acts as a source or a drain.

전체구조상부에 SAC 질화막을 형성한 후 게이트 라인 사이를 절연시키고 상부 배선과의 절연을 위한 제 1 층간절연막을 형성한 다음, 화학적 기계적 연마(CMP) 공정을 실시한다. 그리고, 셀프 얼라인 콘택 식각 공정으로 제 1 층간절연막 및 SAC 질화막의 소정 영역을 식각하여 접합부를 노출시키는 콘택을 형성한다. 그리고, 콘택이 매립되도록 폴리실리콘 도전막을 형성하여 콘택 플러그를 형성한다.After the SAC nitride film is formed on the entire structure, the gate line is insulated and the first interlayer insulating film is formed to insulate the upper wiring, and then a chemical mechanical polishing (CMP) process is performed. Then, a predetermined region of the first interlayer insulating layer and the SAC nitride layer is etched by a self-aligned contact etching process to form a contact that exposes the junction. Then, a polysilicon conductive film is formed to fill the contact to form a contact plug.

콘택 플러그를 포함한 전체구조상부에 제 2 층간절연막을 형성한 후, 제 2 층간절연막의 소정영역을 식각하여 상기 콘택 플러그를 노출시킨 다음, 금속막을 형성한다.After forming the second interlayer insulating film on the entire structure including the contact plug, the predetermined area of the second interlayer insulating film is etched to expose the contact plug, and then a metal film is formed.

그런데, 전술한 바와 같은 종래 NAND형 플래쉬 메모리 소자의 제조 방법으로 콘택플러그를 형성하면, 콘택 내부의 폴리실리콘 도전막이 길게 형성되어 콘택플러그 자체가 높은 저항값을 갖는다. 또한, 콘택플러그가 형성되는 공정 중에 콘택홀 내부에 보잉(Bowing) 현상 및 심(Seam)이 발생되는 문제점이 있으며, 후속 화학적 기계적 연마공정(CMP)에 의해 상기 심이 과대해져 도전막 증착시 불소(F)의 어택(Attack)이 발생되는 문제점이 있다.However, when the contact plug is formed by the conventional method of manufacturing the NAND type flash memory device as described above, the polysilicon conductive film inside the contact is formed long, so that the contact plug itself has a high resistance value. In addition, there is a problem in that a bowing phenomenon and a seam are generated in the contact hole during the process of forming the contact plug, and the seam becomes excessive by a subsequent chemical mechanical polishing process (CMP), which causes fluorine (e.g. There is a problem that an attack of F) occurs.

본 발명의 목적은 드레인 콘택에 도전막을 매립한 후, 상기 도전막을 소정깊이 식각한 다음, 식각된 영역에 실리사이드막과 금속막을 순차적으로 형성하여 드레인 콘택플러그를 형성함으로써, 드레인 콘택플러그의 저항 및 접촉 저항을 감소시킬 수 있는 NAND형 플래쉬 메모리 소자의 제조 방법을 제공함에 있다.An object of the present invention is to embed a conductive film in a drain contact, and then etch the conductive film to a predetermined depth, and then form a drain contact plug by sequentially forming a silicide film and a metal film in the etched region, thereby forming resistance and contact of the drain contact plug. Disclosed is a method of manufacturing a NAND type flash memory device capable of reducing resistance.

본 발명의 일 실시 예에 따른 NAND형 플래쉬 메모리 소자의 제조 방법은 반도체 기판 상부에 복수개의 게이트를 형성하고 상기 게이트 사이의 상기 반도체 기판상에 접합 영역을 형성하는 단계; 전체구조상부에 제 1 층간절연막을 형성한 후, 상기 제 1 층간절연막의 소정영역을 식각하여 상기 접합 영역을 노출시키는 콘택홀을 형성하는 단계; 상기 콘택홀에 도전막을 형성한 후, 상기 도전막을 소정깊이 식각하는 단계; 상기 식각된 영역에 실리사이드막 및 제 1 금속막을 순차적으로 형성하여 콘택 플러그를 형성하는 단계; 전체구조상부에 제 2 층간절연막을 형성한 후, 상기 제 2 층간절연막의 소정 영역을 식각하여 상기 콘택 플러그를 노출시키는 단계; 전체구조상부에 베리어 메탈막 및 제 2 금속층을 순차적으로 형성하는 단계를 포함한다.A method of manufacturing a NAND type flash memory device according to an embodiment of the present invention includes forming a plurality of gates on a semiconductor substrate and forming a junction region on the semiconductor substrate between the gates; Forming a contact hole exposing the junction region by etching a predetermined region of the first interlayer dielectric layer after forming a first interlayer dielectric layer on the entire structure; Forming a conductive film in the contact hole and then etching the conductive film to a predetermined depth; Forming a contact plug by sequentially forming a silicide layer and a first metal layer in the etched region; Forming a second interlayer insulating film on the entire structure, and then etching a predetermined region of the second interlayer insulating film to expose the contact plug; Sequentially forming a barrier metal film and a second metal layer on the entire structure.

상기 도전막은 폴리실리콘으로 형성한다. 상기 소정깊이는 500 내지 5000 Å 이다. 상기 실리사이드막은 Ti, Co, Pt, Ir, Ru 중 어느 하나의 금속으로 형성한다. 상기 실리사이드막은 10 내지 1000 Å 의 두께로 형성하되, 상기 제 1 층간절연막의 높이 보다 높지 않도록 형성한다.The conductive film is formed of polysilicon. The predetermined depth is 500 to 5000 mm 3. The silicide film is formed of any one metal of Ti, Co, Pt, Ir, and Ru. The silicide film is formed to a thickness of 10 to 1000 Å, but not higher than the height of the first interlayer insulating film.

상기 실리사이드막을 형성한 후, RTP 방식 또는 공정로(Furnace) 방식으로 400 내지 1500 ℃ 의 온도하에서 어닐 공정을 실시하는 단계를 더 포함한다.After the silicide film is formed, the method may further include performing an annealing process at a temperature of 400 to 1500 ° C. in an RTP method or a Furnace method.

상기 제 1 금속막은 TiN, TaN 또는 WN 등 전도성 질화막으로 형성한다. 상기 실리사이드막 및 제 1 금속막은 화학적 기상증착법(Chemical Vapor Deposition : CVD) 또는 원자층 증착법(Atomic Layer Deposition : ALD)으로 형성한다. 상기 베리어 메탈막은 Ti 또는 TiN 으로 형성한다.The first metal film is formed of a conductive nitride film such as TiN, TaN, or WN. The silicide layer and the first metal layer are formed by Chemical Vapor Deposition (CVD) or Atomic Layer Deposition (ALD). The barrier metal film is formed of Ti or TiN.

이하, 첨부된 도면을 참조하여 본 발명의 실시 예를 상세히 설명하기로 한다.Hereinafter, with reference to the accompanying drawings will be described an embodiment of the present invention;

도 1a 내지 도 1d는 본 발명의 일 실시 예에 따른 NAND형 플래쉬 메모리 소자의 제조 방법을 설명하기 위해 순서적으로 도시한 선택 트랜지스터 영역의 단면도 이다.1A to 1D are cross-sectional views of selection transistor regions sequentially shown to explain a method of manufacturing a NAND type flash memory device according to an embodiment of the present invention.

도 1a를 참조하면, 반도체 기판(100) 상부에 터널 산화막(102), 제 1 폴리실 리콘막(104), 유전체막(106), 제 2 폴리실리콘막(108), 텅스텐실리사이드막(110) 및 하드마스크막(112)이 적층되어 셀 영역에는 플로팅 게이트와 콘트롤 게이트가 적층된 게이트 전극이 형성된다. 이와 동시에 선택 트랜지스터에도 동일 구조의 게이트 전극이 형성된다.Referring to FIG. 1A, a tunnel oxide film 102, a first polysilicon film 104, a dielectric film 106, a second polysilicon film 108, and a tungsten silicide film 110 are disposed on a semiconductor substrate 100. The hard mask layer 112 is stacked to form a gate electrode in which a floating gate and a control gate are stacked in the cell region. At the same time, the gate electrode having the same structure is formed in the selection transistor.

게이트 식각시 발생되는 마이크로 트렌치 및 플라즈마 데미지를 제거하기 위해 산화 공정을 실시하여 게이트 측벽, 바람직하게는 제 1 및 제 2 폴리실리콘막(204 및 208)의 측벽에 산화막(미도시)을 형성한다. 그리고, 이온 주입 공정을 실시하여 소오스 및 드레인으로 작용하는 접합부(114)를 형성한다.An oxidation process is performed to remove micro trenches and plasma damage generated during gate etching, thereby forming an oxide film (not shown) on the sidewalls of the gate sidewalls, preferably the first and second polysilicon layers 204 and 208. Then, an ion implantation process is performed to form a junction 114 serving as a source and a drain.

도면에는 미도시 되었으나, 선택 트랜지스터 영역의 게이트 측벽에 스페이서를 형성한 후, 전체구조상부에 제 1 버퍼 산화막 및 SAC 질화막을 형성할 수도 있다. 전체구조상부에 게이트 라인 사이를 절연시키고 상부 배선과의 절연을 위한 제 1 층간절연막(116)을 형성한 후, 화학적 기계적 연마(CMP) 공정을 실시하여 평탄화 한다. Although not shown in the drawing, after forming a spacer on the gate sidewall of the selection transistor region, a first buffer oxide film and an SAC nitride film may be formed over the entire structure. After insulating the gate lines on the entire structure and forming the first interlayer insulating film 116 for insulating the upper wiring, a chemical mechanical polishing (CMP) process is performed to planarize.

도 1b를 참조하면, 셀프 얼라인 콘택 식각 공정으로 제 1 층간절연막(116)의 소정영역을 식각하여 드레인 또는 소오스 영역을 노출시키는 콘택을 형성한다. 콘택이 매립되도록 일례로 폴리실리콘을 사용하여 도전막(118)을 형성한다.Referring to FIG. 1B, a predetermined region of the first interlayer insulating layer 116 is etched by a self-aligned contact etching process to form a contact that exposes a drain or source region. For example, the conductive film 118 is formed using polysilicon so that the contact is filled.

식각공정을 실시하여 상기 도전막(118)을 500 내지 5000 Å 의 깊이로 식각한다.An etching process is performed to etch the conductive film 118 to a depth of 500 to 5000 mm 3.

도 1c를 참조하면, 도 1b의 공정에 의해 식각된 콘택 영역에 10 내지 1000 Å 의 두께로 실리사이드막(120)을 형성하되, 제 1 층간절연막(116)의 높이 보다 높지 않도록 형성한 후, 어닐(Aneal) 공정을 실시하여 실리사이드막(120)을 결정화 시킨다.Referring to FIG. 1C, a silicide film 120 is formed in a contact region etched by the process of FIG. 1B to a thickness of 10 to 1000 Å, but not higher than the height of the first interlayer insulating film 116, followed by annealing. An annealing process is performed to crystallize the silicide layer 120.

보다 상세하게, 실리사이드막(120)으로는 Ti, Co, Pt, Ir, Ru 중 어느 하나의 금속을 사용하며, RTP 방식 또는 공정로(Furnace) 방식으로 400 내지 1500 ℃ 의 온도하에서 어닐 공정을 실시한다. In more detail, the silicide layer 120 uses any one of Ti, Co, Pt, Ir, and Ru, and performs an annealing process at a temperature of 400 to 1500 ° C. in an RTP method or a Furnace method. do.

다음, 콘택홀이 완전히 매립되도록 제 1 금속막(122)을 형성한다. 제 1 금속막(122)으로는 TiN, TaN 또는 WN 등 전도성 질화막을 사용한다.Next, the first metal film 122 is formed to completely fill the contact hole. As the first metal film 122, a conductive nitride film such as TiN, TaN, or WN is used.

실리사이드막(120) 및 제 1 금속막(122)의 증착방식은 화학적 기상증착법(Chemical Vapor Deposition : CVD) 또는 원자층 증착법(Atomic Layer Deposition : ALD)을 사용한다.As the deposition method of the silicide layer 120 and the first metal layer 122, chemical vapor deposition (CVD) or atomic layer deposition (ALD) is used.

전술한 바와 같이, 본 발명은 도전막(118) 상부에 바로 제 1 금속막(122)을 형성하면 콘택 플러그의 저항이 높아지기 때문에, 도전막(118)과 제 1 금속막(122) 사이에 실리사이드막(120)을 형성하여 콘택 플러그를 형성함으로써, 콘택 플러그 자체의 저항을 현저하게 낮출 수 있다.As described above, in the present invention, if the first metal film 122 is directly formed on the conductive film 118, the resistance of the contact plug increases, so that the silicide is formed between the conductive film 118 and the first metal film 122. By forming the film 120 to form the contact plug, the resistance of the contact plug itself can be significantly lowered.

도 1d를 참조하면, 전체구조상부에 제 2 층간절연막(124)을 형성한 후, 제 2 층간절연막(124)의 소정영역을 식각하여 콘택플러그를 노출시키는 콘택홀을 형성한다. 전체구조상부에 Ti 또는 TiN 을 사용하여 베리어 메탈막(126)을 형성한 다음, 제 2 금속막(128)을 형성한다.Referring to FIG. 1D, after forming the second interlayer insulating layer 124 on the entire structure, a predetermined hole of the second interlayer insulating layer 124 is etched to form a contact hole exposing a contact plug. The barrier metal film 126 is formed on the entire structure by using Ti or TiN, and then the second metal film 128 is formed.

본 발명은 도면에 도시된 실시 예를 참고로 설명되었으나, 이는 예시적인 것에 불과하며, 본 기술분야의 통상의 지식을 가진 자라면 이로부터 다양한 변형 및 균등한 타 실시 예가 가능하다는 점을 이해할 것이다.Although the present invention has been described with reference to the embodiments illustrated in the drawings, this is merely exemplary, and it will be understood by those skilled in the art that various modifications and equivalent other embodiments are possible.

따라서, 본 발명의 진정한 기술적 보호 범위는 첨부된 특허청구범위의 기술적 사상에 의해 정해져야 할 것이다.Therefore, the true technical protection scope of the present invention will be defined by the technical spirit of the appended claims.

본 발명은 드레인 콘택에 도전막을 매립한 후, 상기 도전막을 소정깊이 식각한 다음, 식각된 영역에 실리사이드막과 금속막을 순차적으로 형성하여 드레인 콘택플러그를 형성함으로써, 드레인 콘택플러그의 저항 및 접촉 저항을 감소시킬 수 있다.According to an embodiment of the present invention, after filling a conductive film in a drain contact, the conductive film is etched to a predetermined depth, and then a silicide film and a metal film are sequentially formed in the etched region to form a drain contact plug, thereby improving resistance and contact resistance of the drain contact plug. Can be reduced.

Claims (9)

반도체 기판 상부에 복수개의 게이트를 형성하고 상기 게이트 사이의 상기 반도체 기판상에 접합 영역을 형성하는 단계;Forming a plurality of gates over the semiconductor substrate and forming a junction region on the semiconductor substrate between the gates; 전체구조상부에 제 1 층간절연막을 형성한 후, 상기 제 1 층간절연막의 소정영역을 식각하여 상기 접합 영역을 노출시키는 콘택홀을 형성하는 단계;Forming a contact hole exposing the junction region by etching a predetermined region of the first interlayer dielectric layer after forming a first interlayer dielectric layer on the entire structure; 상기 콘택홀에 도전막을 형성한 후, 상기 도전막을 소정깊이 식각하는 단계;Forming a conductive film in the contact hole and then etching the conductive film to a predetermined depth; 상기 식각된 영역에 실리사이드막 및 제 1 금속막을 순차적으로 형성하여 콘택 플러그를 형성하는 단계;Forming a contact plug by sequentially forming a silicide layer and a first metal layer in the etched region; 전체구조상부에 제 2 층간절연막을 형성한 후, 상기 제 2 층간절연막의 소정 영역을 식각하여 상기 콘택 플러그를 노출시키는 단계;Forming a second interlayer insulating film on the entire structure, and then etching a predetermined region of the second interlayer insulating film to expose the contact plug; 전체구조상부에 베리어 메탈막 및 제 2 금속층을 순차적으로 형성하는 단계;Sequentially forming a barrier metal film and a second metal layer on the entire structure; 를 포함하는 NAND형 플래쉬 메모리 소자의 제조 방법.Method of manufacturing a NAND type flash memory device comprising a. 제 1 항에 있어서,The method of claim 1, 상기 도전막은 폴리실리콘으로 형성하는 NAND형 플래쉬 메모리 소자의 제조 방법.The conductive film is a method of manufacturing a NAND flash memory device formed of polysilicon. 제 1 항에 있어서,The method of claim 1, 상기 소정깊이는 500 내지 5000 Å 인 NAND형 플래쉬 메모리 소자의 제조 방 법.The predetermined depth is 500 to 5000 Å method of manufacturing a NAND flash memory device. 제 1 항에 있어서,The method of claim 1, 상기 실리사이드막은 Ti, Co, Pt, Ir, Ru 중 어느 하나의 금속으로 형성하는 NAND형 플래쉬 메모리 소자의 제조 방법.The silicide layer is formed of a metal of any one of Ti, Co, Pt, Ir, and Ru. 제 1 항에 있어서,The method of claim 1, 상기 실리사이드막은 10 내지 1000 Å 의 두께로 형성하되, 상기 제 1 층간절연막의 높이 보다 높지 않도록 형성하는 NAND형 플래쉬 메모리 소자의 제조 방법.The silicide layer is formed to a thickness of 10 to 1000 Å, but not to be higher than the height of the first interlayer insulating film manufacturing method of the NAND type flash memory device. 제 1 항에 있어서,The method of claim 1, 상기 실리사이드막을 형성한 후, RTP 방식 또는 공정로(Furnace) 방식으로 400 내지 1500 ℃ 의 온도하에서 어닐 공정을 실시하는 단계를 더 포함하는 NAND형 플래쉬 메모리 소자의 제조 방법.After the silicide film is formed, the method of manufacturing a NAND flash memory device further comprising the step of performing an annealing process at a temperature of 400 to 1500 ℃ by RTP method or Furnace method. 제 1 항에 있어서,The method of claim 1, 상기 제 1 금속막은 TiN, TaN 또는 WN 등 전도성 질화막으로 형성하는 NAND형 플래쉬 메모리 소자의 제조 방법.The first metal film is formed of a conductive nitride film such as TiN, TaN or WN method of manufacturing a NAND flash memory device. 제 1 항에 있어서,The method of claim 1, 상기 실리사이드막 및 제 1 금속막은 화학적 기상증착법(Chemical Vapor Deposition : CVD) 또는 원자층 증착법(Atomic Layer Deposition : ALD)으로 형성하는 NAND형 플래쉬 메모리 소자의 제조 방법.The silicide layer and the first metal layer may be formed by chemical vapor deposition (CVD) or atomic layer deposition (ALD). 제 1 항에 있어서,The method of claim 1, 상기 베리어 메탈막은 Ti 또는 TiN 으로 형성하는 NAND형 플래쉬 메모리 소자의 제조 방법.The barrier metal film is formed of Ti or TiN method of manufacturing a flash memory device.
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