KR20070099907A - Delay locked loop apparatus - Google Patents

Abstract

A delay locked loop is provided to improve operation reliability of a semiconductor device by synchronizing an output of a semiconductor memory device with an external clock. A delay locked loop includes first and second course delay units, a decoder, and a fine delay unit. The fine delay unit includes first and second delay controllers(210,220), a path select signal generator(300), and an output unit(230). The first delay controller includes plural series-coupled delay units and delays a first input signal by a time, which is determined according to a phase difference between first and second input signals. The second delay controller includes plural series-coupled delay units and delays the second input signal by a time, which is determined according to the phase difference between the first and second input signals. A path select signal generator receives the first and second input signals and outputs a path select signal according to the phases of the first and second input signals, when the DLL(Delay Locked Loop) is locked. The output unit outputs one of the output signals from the first and second delay controllers in response to the path select signal.

Description

DEL device {Delay Locked Loop Apparatus}

1 is a configuration diagram of a general DLL device;

FIG. 2 is a configuration diagram of the fine delay unit shown in FIG. 1;

3 is a detailed circuit diagram of the delay means shown in FIG. 2;

4 is a block diagram of a fine delay unit according to the present invention;

5 is a detailed circuit diagram of the fine delay unit shown in FIG. 4;

FIG. 6 is a detailed circuit diagram of the delay means shown in FIG.

<Description of the symbols for the main parts of the drawings>

200: fine delay unit 210: first delay control unit

212-1 to 212-m: delay means 220: second delay control unit

222-1 to 222-m: delay unit 230: output unit

232: first comparison means 234: second comparison means

240: inversion circuit 250, 260: variable delay circuit

300: path selection signal generation unit

The present invention relates to a DLL device, and more particularly, to a DLL device for generating an accurate internal clock signal in a semiconductor memory device using high frequency and low voltage.

In general, a semiconductor memory device operating in synchronization with an external clock signal employs a clock buffer that receives a clock signal from an external source and converts it into a clock required within the semiconductor memory device in order to perform a high speed operation. As a result, the time until the data is output from the memory device is changed by the influence of the process or the like, resulting in a phase difference between the output signal of the semiconductor memory device and the external clock signal.

When the phases of the external clock signal and the memory device output signal do not coincide, the high frequency characteristics of the semiconductor memory device are deteriorated. For this purpose, a delay locked loop for generally matching the phase of the external clock signal and the memory device output signal is performed; DLL) device.

1 is a block diagram of a general DLL device.

As shown in the drawing, the DLL device receives an output signal of the clock buffer 110 and the clock buffer 110 that receives the external clock signal CLK, converts it to an internal level, and outputs the output signal from the first decoder 190. Clocks delayed from a plurality of coarse delay units 120 and 122 and a plurality of coarse delay units 120 and 122 for outputting clock signals X1 and X2 delayed by a predetermined time by the control signal. A fine delay unit 130 for receiving the signals X1 and X2 and finely adjusting and outputting the phases of the clock signals X1 and X2 delayed by the control signal output from the second decoder 192, Receives the phase-adjusted signal Y from the fine delay unit 130 and temporarily stores the output buffer 140 for outputting the DLL clock signal DLL_CLK and the output signal Y of the fine delay unit 130. Time difference between the externally supplied clock signal and the internal clock signal. Delay amount according to the comparison signal output from the phase detector 160 and the phase detector 160, which receives the replica 150, the external clock signal and the output signal of the replica 150 and compares each other and outputs a comparison signal. A phase control unit 170 for outputting a phase control signal for adjusting a signal, a counter 180 for generating a coefficient value according to the phase control signal output from the phase control unit 170, and receiving and decoding a coefficient value from the counter 180 After receiving and decoding the coefficient values from the first decoder 190 and the counter 180 which provide the control signals generated according to the first and second coarse delay units 120 and 122, the fine delay unit 130 is then decoded. It includes a second decoder 192 to provide a).

In such a DLL device, a large delay difference between the external clock and the internal clock is corrected by the first and second coarse delay units 120 and 122, and the fine delay of the correction result of the first and second coarse delay units 120 and 122 is fine. Mixing and fine adjustment in the unit 130 allows the semiconductor memory device to be output in synchronization with an external clock.

The output signal of the fine delay unit 130 is again modeled by the replica 150, so that the clock signal is continuously corrected by the phase control signal generated according to the modeling result.

FIG. 2 is a configuration diagram of the fine delay unit illustrated in FIG. 1.

As shown in the drawing, the fine delay unit 130 receives the output signal X1 of the first coarse delay unit 120 and delays a predetermined time to output the first coarse delay unit 132 and the second coarse delay unit 122. And a second delay control unit 134 for receiving the output signal X2 of the control unit and delaying the output signal X2 for a predetermined time, and outputting the respective output terminals of the first and second delay control units 132 and 134 to the output node Z. Connected. The signal applied to the output node Z is inverted by the inverter 136 and outputted Y.

In addition, the first and second delay controllers 132 and 134 have the same number of delay means 132-0 to 132-n and 134-0 to 134-n, respectively, and the fine delay unit 130 is internally provided. When operating for fine adjustment of the clock signal, the number of enabled control signals of the first delay controller 132 is controlled to be equal to the number of disabled control signals of the second delay controller 134. That is, the control signals S1_0 to S1_n of the first delay control unit 132 and the control signals S2_0 to S2_n of the second delay control unit 134 are controlled to have opposite phases.

Each of the delay means 132-0 to 132-n and 134-0 to 134-n can be configured as a three-phase CMOS inverter as shown in FIG.

FIG. 3 is a detailed circuit diagram of the delay means shown in FIG.

As shown, the delay means is driven by a signal applied to the input terminal IN to which the output signals X1 and X2 of the first or second coarse delay units 120 and 122 are input, and the power source terminal and the first terminal. First MOS transistor P1 connected between node K1, second MOS transistor P2 connected between first node K1 and output terminal OUT and driven by control signal bar Sb, output It is connected between the terminal OUT and the second node K2 and connected between the third MOS transistor N1 and the second node K2 and the ground terminal driven by the control signal S and applied to the input terminal IN. And a fourth MOS transistor N2 which is driven by the signal to be made.

The first and second delay control units 132 and 134 are configured to control the enabled control signals among the control signals inputted to the plurality of delay means 132-0 to 132-n and 134-0 to 134-n. The output delay time of the input signal can be controlled according to the number. For example, if nx delay means of the first delay control unit 132 are activated (x is a natural number less than n), the second delay control unit 134 By activating x + 1 delay means, the delay time between the first and second input signals X1 and X2 can be corrected.

That is, the control signals S1_0 to S1_n and S2_0 to S2_n are selectively enabled with respect to the first and second delay control units 132 and 134 each having n + 1 delay means. The signal is outputted by the low resistance by the delay means and by the high resistance by the delay means in which the control signal is disabled, and the resultant output signal Y of the fine delay unit 130 is the first input signal. The delay is output within the time difference between X1 and the second input signal X2.

However, in the case of using such a fine delay unit, since a plurality of delay means are connected to the output node Z, a heavy load is applied, and accordingly, the rising time of the signal Y generated at the output node Z is increased. There is a problem that a margin for overfalling time cannot be guaranteed.

In particular, in a semiconductor memory device using a high frequency and a low voltage, the rising and falling times of the output node Z take more than half a period of the clock signal, so that the output signal does not rise to a desired level, and thus an incorrect clock signal. Is output and the memory device malfunctions.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-described problem, and has a technical problem to provide a DLL device for synchronizing an output signal to an external clock in a semiconductor memory device using high frequency and low voltage.

According to an aspect of the present invention, a DLL device includes: first and second coarse delay units for delaying and outputting an external clock signal for a given time, and a decoder for outputting a plurality of control signals; And a fine delay unit for finely delaying first and second input signals input from the first and coarse delay units in response to at least one of the control signals output from the decoder. The delay unit includes a plurality of delay means connected in series to delay the first input signal provided from the first coarse delay unit by a time determined by the phase difference between the first input signal and the second input signal. A first delay control unit; A second delay for delaying a second input signal provided from a second coarse delay section by a time determined by a phase difference between the first input signal and the second input signal, having a plurality of delay means connected in series; Control unit; A phase of the first and second input signals when the first input signal is input from the first coarse delay unit and the second input signal is input from the second coarse delay unit, and the delay locked loop is locked. A path selection signal generator for outputting a path selection signal according to the present invention; And an output unit outputting any one of output signals of the first and second delay control units in response to the path selection signal.

In addition, the DLL device according to another embodiment of the present invention includes a first and second coarse delay unit for delaying and outputting an external clock signal for a given time, respectively; A decoding unit for outputting a plurality of control signals; And receiving first and second input signals from the first and second coarse delay units, respectively, and in response to at least one of the control signals output from the decoding unit and the locking state signal. Outputs the first input signal as an output signal when the phase of the second input signal is ahead of the phase of the second input signal, and outputs the first input signal when the phase of the second input signal is earlier than the phase of the first input signal. And a fine delay unit for outputting a signal as an output signal.

Hereinafter, with reference to the accompanying drawings will be described in detail a preferred embodiment of the present invention.

4 is a block diagram of a fine delay unit according to the present invention.

The fine delay unit 200 according to the present invention receives the first input signal X1 from the first coarse delay unit, and responds to the first decoded first control signal S1 and the first input signal X1 and the first input signal X1. The first delay controller 210 delays the first input signal X1 by a time determined by the phase difference between the two input signals X2, and receives the second input signal X2 from the second coarse delay unit. In order to delay the second input signal X2 by a time determined by a phase difference between the first input signal X1 and the second input signal X2 in response to the previously decoded second control signal S2. The second delay control unit 220 receives the first input signal X1 from the first coarse delay unit, the second input signal X2 from the second coarse delay unit, and is enabled when a fine delay operation occurs. In response to the locking state signal LOCK_STATE, the phases of the first input signal X1 and the second input signal X2 Accordingly, the path selection signal generator 300 outputting the path selection signal SEL and the output signals X1_D and X2_D of the first and second delay controllers 210 are received and output from the path selection signal generator 300. And an output unit 230 for outputting the corrected clock signal Y in response to the path selection signal SEL.

Here, each of the first and second delay control units 210 and 220 includes a plurality of delay means connected in series, and the delay means constituting the first and second delay control units 210 and 220 have the same number (eg, For example, m) and the number of control signals enabled according to the delay time difference, that is, the phase difference, of the first and second input signals X1 and X2 are controlled.

For example, when the phase of the first input signal X1 is earlier than the second input signal X2, the output unit 230 may control the first delay controller 210 under the control of the path selection signal SEL. Output signal X1_D to the output terminal Y, and when the phase of the first input signal X1 and the second input signal X2 are the same, the level of the path selection signal SEL is shifted. Subsequently, when the phase of the second input signal X2 is ahead of the first input signal X1, the output signal X2_D of the second delay controller 220 is controlled by the level shifted path selection signal SEL. Output to the output terminal (Y).

On the other hand, the path selection signal generator 300 when the first input signal X1 is ahead of the second input signal X2 in response to the locking state signal LOCK_STATE enabled when the fine delay operation occurs. The path selection signal SEL is output, and when the second input signal X2 is out of phase with the first input signal X1, the inverted signal SELZ of the path selection signal is output.

FIG. 5 is a detailed circuit diagram of the fine delay unit shown in FIG. 4.

Hereinafter, the delay means outputs the input signal with a short time delay when the control signal is enabled, and outputs the input signal by delaying the input signal when the control signal is disabled.

As shown, the first delay control unit 210 is composed of a plurality of delay means (212-1 ~ 212-m), the first input signal (in) to the input terminal IN of the first delay means (212-1) ( X1) is supplied. The first to sixth terminals S1, S2, S3, S1z, S2z, and S3z of the delay means 212-1 to 212-m may include the first control signals S1_0 to S1_n and the inverted signals S1z_0. The pairs of ˜S1z_n are sequentially input, and the output terminal Y of the previous delay means is connected to the input terminal IN of the next delay means. In addition, the second delay control unit 220 is composed of a plurality of delay means (222-1 ~ 222-m), the second input signal (X2) as the input terminal (IN) of the first delay means (222-1) Supplied. In addition, as the first to sixth terminals S1, S2, S3, S1z, S2z, and S3z of the delay means 222-1 to 222-m, the second control signals S2_0 to S2_n and the inverted signal S2z_0 are used. The pairs of ˜S2z_n are sequentially input, and the output terminal Y of the previous delay means is connected to the input terminal IN of the next delay means.

The first and second control signals S1_0 to S1_n and S2_0 to S2_n are determined whether or not to be enabled according to the phase difference between the first and second input signals X1 and X2. Delay the control signal of the delay control unit sequentially according to the number of loops to increase the delay time, and enable the control signal of the delay control unit to which the slow phase signal is input sequentially according to the looping time to reduce the delay time. .

That is, the phase of the first input signal X1 is earlier than the phase of the second input signal X2, the first control signals S1_0 to S1_n are all enabled, and the second control signal S2_0 to It is assumed that the first and second delay controllers 210 and 220 operate with S2_n all disabled. In this case, the output unit 230 selects the output signal X1_D of the first delay control unit 210 and outputs the corrected clock signal Y. When the output signal Y is fed back to the input signal of the delay locked loop circuit and compared with an external clock, if it is determined that more delay is required, the control signal S1_0 is disabled while the control signal S2_0 is Enable to increase the delay time for the first input signal (X1), and reduce the delay time for the second input signal (X2). In addition, when the control signal S1_0 is disabled, the control signal S2_0 is enabled, the output signal Y is fed back to the input of the delay locked loop circuit, and compared with an external clock. In this case, the control signal S1_1 is disabled and the control signal S2_1 is enabled to further increase the delay with respect to the first input signal X1 and further reduce the delay with respect to the second input signal X2.

When this process is repeated, the phases of the first and second input signals X1 and X2 coincide with each other so that the delay value adjusted by the fine delay unit 200 is equal to the delay value of the coarse delay unit. The corrected clock signal Y existing between the phases of the first and second input signals X1 and X2 is generated.

FIG. 6 is a detailed circuit diagram of the delay means shown in FIG.

As shown, each delay means constituting the delay control means 210, 220 to be applied to the present invention may be configured as a CMOS inverting circuit whose delay value is changed by a plurality of control signals.

More specifically, the delay means of the present invention is connected between the inverting circuit 240 connected between the power supply terminal VDD and the ground terminal VSS, and between the power supply terminal VDD and the first node K11 of the inverting circuit 240. And the first delay circuit 250 and the second node K12 of the inverting circuit 240 and the ground terminal VSS driven by the control signals S1z, S2z, and S3z are connected to the control signals S1, S2, A second delay circuit 260 driven by S3).

Here, the inversion circuit 240 is connected between the power supply terminal VDD and the first node K11 and driven by the ground potential VSS, the first MOS transistor P11, the first node K11, and the output terminal. Second MOS transistor P12 connected between (Y) and driven by input signal IN, third MOS connected between output terminal Y and second node K12 and driven by input signal IN And a fourth MOS transistor N12 connected between the transistor N11 and the second node K12 and the ground terminal VSS and driven by a power supply voltage signal.

The first delay circuit 250 includes a plurality of MOS transistors connected in parallel between the power supply terminal VDD and the first node K11 and driven by the control signals S1z, S2z, and S3z, respectively. The delay circuit 260 is composed of a plurality of MOS transistors connected in parallel between the second node K12 and the ground terminal VSS and driven by the control signals S1, S2, and S3, respectively. Here, the MOS transistors constituting the first and second MOS transistors P11 and P12 and the first delay circuit 250 are PMOS transistors, and the third and fourth MOS transistors N11 and N12 and the second delay circuit. The MOS transistor constituting 260 may be an NMOS transistor, and the control signals S1z, S2z, and S3z for driving the first delay circuit 250 are controlled for driving the second delay circuit 260. It becomes an inverted signal of the signals S1, S2, S3.

In such a delay circuit, the input signal IN changes in a delay value depending on whether the MOS transistors constituting the first and second delay circuits 250 and 260 are turned on or off, for example, the control signal S1. When S2 and S3 are enabled at a high level, the resistance by the MOS transistor decreases to shorten the delay time, whereas when the control signals S1, S2 and S3 are disabled to the low level, the resistance increases to delay. It will take longer.

In this way, the delay time of the input signal can be varied according to whether the control signal applied to the delay means is enabled, so that the phase difference between the signals output from the coarse delay unit can be corrected.

Referring to FIG. 5 again, the output unit 230 may include a first delay signal X1_D, which is an output signal of the first delay controller 210, and a second delay signal X2_D, which is an output signal of the second delay controller 220. Is received and outputs any one of the first and second delay signals X1_D and X2_D under the control of the path selection signal SEL.

To this end, the output unit 230 includes a first comparing means 232 and a second comparing means 234, the first and second comparing means 232, respectively, the first delay signal (X1_D) and the path selection First comparison circuits 2232 and 2342 for comparing the bar signal SELb and outputting the first comparison signal, and comparing the second delay signal X2_D and the path selection signal SEL to output the second comparison signal. Third comparison circuits 2326 and 2346 for outputting the third comparison signal Y by comparing the output signals of the second comparison circuits 2324 and 2344 and the first and second comparison circuits 2232/2324 and 2342/2344. ).

Here, when the phase of the first input signal (X1) is ahead of the phase of the second input signal (X2), the path selection signal (SEL) is, for example, low level to the first through the output terminal (Y) The first delayed signal X1_D delaying the input signal X1 is outputted, and when the phases of the two input signals X1 and X2 become the same, the level of the path selection signal SEL transitions to a high level. After that, when the phase of the second input signal X2 is earlier than the phase of the first input signal X1, the second delay signal X2_D, which delays the second input signal X2 through the output terminal Y, is output. Be sure to

On the other hand, it is preferable that the first to third comparison means (2322, 2324, 2326, 2342, 2344, 2346) are each formed of a NAND gate.

That is, the present invention finely adjusts the delay amount of the clock signal output from the coarse delay unit by the delay control unit that can vary the delay amount, corrects the delay amount of the signal whose phase is earlier in accordance with the slower phase signal, and outputs it. By reducing the load on the output node, the semiconductor memory device can operate on a signal exactly synchronized to an external clock.

As such, those skilled in the art will appreciate that the present invention can be implemented in other specific forms without changing the technical spirit or essential features thereof. Therefore, the above-described embodiments are to be understood as illustrative in all respects and not as restrictive. The scope of the present invention is shown by the following claims rather than the detailed description, and all changes or modifications derived from the meaning and scope of the claims and their equivalents should be construed as being included in the scope of the present invention. do.

According to the present invention described above, the output in the semiconductor memory device can be synchronized to the external clock, thereby improving the operation reliability of the semiconductor device. In addition, even when the semiconductor memory device operates at high frequency and low power, the internal clock signal may be accurately generated even if the operating voltage decreases by reducing the rising time and the falling time of the internal clock signal.

Claims (18)

First and second coarse delay units for delaying and outputting an external clock signal for a given time, a decoder for outputting a plurality of control signals, and at least one control signal output from the decoder; A DLL device comprising a fine delay unit for finely delaying first and second input signals input from a second coarse delay unit, The fine delay unit, A first delay control unit having a plurality of delay means connected in series, for delaying the first input signal provided from the first coarse delay unit by a time determined by a phase difference between the first input signal and the second input signal. ; A second delay for delaying a second input signal provided from a second coarse delay section by a time determined by a phase difference between the first input signal and the second input signal, having a plurality of delay means connected in series; Control unit; A phase of the first and second input signals when the first input signal is input from the first coarse delay unit and the second input signal is input from the second coarse delay unit, and the delay locked loop is locked. A path selection signal generator for outputting a path selection signal according to the present invention; And An output unit outputting any one of output signals of the first and second delay control units in response to the path selection signal; DLL device comprising a. The method of claim 1, DLL devices, characterized in that the same number of delay means constituting the first and second delay control unit. The method of claim 1, The first delay control unit variably delays the first input signal by at least one of a plurality of control signals output from the decoder, And the second delay controller is configured to variably delay the second input signal by at least one of a plurality of control signals output from the decoder. The method of claim 3, wherein With respect to the first and second input signals, the signals output by activating all of the control signals of the delay control section into which the signals having a slow phase are input and the output signals of the delay control section into which the signals having the preceding phase are input have the same phase. And determining the number of enable signals of the control signal inputted to the delay control unit to which the signal having the preceding phase is input. The method of claim 1, The delay means includes an inverting circuit connected between a power supply terminal and a ground terminal; A first delay circuit connected between the power supply terminal and the first node of the inversion circuit and driven by a control signal; And A second delay circuit connected between the second node of the inverting circuit and the ground terminal and driven by the control signal; DLL device comprising a. The method of claim 5, The inversion circuit includes a first MOS transistor connected between the power supply terminal and the first node and driven by a ground potential; A second MOS transistor connected between the first node and an output terminal and driven by an input signal; A third MOS transistor connected between the output terminal and the second node and driven by an input signal; And A fourth MOS transistor connected between the second node and the ground terminal and driven by a power supply voltage signal; DLL device comprising a. The method of claim 6, And the first and second MOS transistors are PMOS transistors. The method of claim 6, And the third and fourth MOS transistors are NMOS transistors. The method of claim 5, And the first delay circuit comprises a plurality of MOS transistors connected in parallel between the power supply terminal and the first node and driven by a control signal, respectively. The method of claim 9, And the plurality of MOS transistors are PMOS transistors. The method of claim 6, And the second delay circuit includes a plurality of MOS transistors connected in parallel between the second node and the ground terminal and driven by a control signal, respectively. The method of claim 11, And the plurality of MOS transistors are NMOS transistors. The method of claim 5, And the control signal for driving the first delay circuit is an inverted signal of the control signal for driving the second delay circuit. The method of claim 1, The output unit selectively outputs an output signal of the first delay control unit or the second delay control unit, wherein the first delay control unit or the second delay control unit receives a signal having a phase out of the first or second input signals. DLL device, characterized in that for outputting the output signal. The method of claim 1, The output unit receives a first delay signal output from the first delay controller, a second delay signal output from the second delay controller, and a path selection signal, respectively, and controls the first delay signal by controlling the path selection signal. First comparing means for outputting; And Receiving a first delay signal output from the first delay controller, a second delay signal output from the second delay controller, and a path selection signal, respectively, and outputting the second delay signal by controlling the path selection signal; Second comparing means; DLL device comprising a. The method of claim 15, The first and second comparison means may include a first comparison circuit configured to output a first comparison signal by comparing a first delayed signal and an inverted signal of the path selection signal, respectively; A second comparison circuit comparing the second delay signal with the path selection signal and outputting a second comparison signal; And A third comparison circuit comparing the output signals of the first and second comparison circuits and outputting a third comparison signal; DLL device comprising a. The method of claim 16, The path selection signal is a DLL device, characterized in that applied to the high or low level in accordance with the phase of the first input signal and the second input signal. The method of claim 16, And the first to third comparison circuits are NAND gates.

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