KR101136981B1 - Phase controller and delay locked loop including same - Google Patents

Abstract

The present invention relates to a phase adjuster, and compares the phases of the internal clock CLK_IN and the two clocks X1 and X2 to weight one of the two clocks X1 and X2 to adjust the rising time and the polling time, respectively, and then the phase is adjusted. Any one of the two clocks is selected to output the output clock CLK_OUT having a phase between the two clocks X1 and X2.

Description

PHASE CONTROLLER AND DELAY LOCKED LOOP INCLUDING SAME}

1 is a circuit diagram showing an example of a phase adjuster according to the prior art.

2 is a circuit diagram illustrating an example of the inverter block 11 of FIG. 1.

3 is a waveform diagram illustrating phases of input clocks X1 and X2 and output clock CLK_OUT according to the operation of FIG. 1;

4 is a block diagram illustrating a delay locked loop according to an embodiment of the present invention.

FIG. 5 is a block diagram illustrating an operation of the course delay unit 410 of FIG. 4.

6 is a diagram illustrating an example of the phase adjuster 420 of FIG. 4.

FIG. 7 is a circuit diagram illustrating an example of the fine delay block FD1 of FIG. 6.

The present invention relates to a phase adjuster, and more particularly, to a phase adjuster used in a delay locked loop of a semiconductor memory device.

In general, a delay locked loop is a circuit for delaying an internal clock such that an internal clock of a synchronous memory using a clock in a semiconductor memory device matches an external clock without error. That is, when an external clock is used internally, skew occurs between the external clock and the internal clock or the external clock and data, and a delay locked loop is used to reduce such skew.

Recently, research has been conducted toward minimizing jitter by reducing the minimum variable delay time in such a delay locked loop. As a part of this, a coarse delay line and a fine delay unit ( A delay locked loop with a hierarchical delay line structure with fine delay unit is proposed.

FIG. 1 illustrates an example of a phase adjuster used as a conventional fine delay unit. A clock CLK_OUT having a phase between two input clocks X1 and X2 is generated by mixing two input clocks X1 and X2 according to weights.

Specifically, the phase adjuster of FIG. 1 mixes two input clocks X1 and X2 according to each of the weight signals S1_0 to S1_n (where n is a natural number of 1 or more) and S2_0 to S2_n, and delivers them to the common output node ND_C. 10 and an output unit 20 for inverting the signal transmitted through the common output node ND_C and outputting a clock CLK_OUT having a phase between two input clocks X1 and X2.

Here, the two input clocks X1 and X2 are signals provided from a dual coarse delay line (not shown) and have a difference as much as a unit delay cell from each other. Each weight signal S2_0 to S2_n is a signal whose phase is opposite to that of each weight signal S1_0 to S1_n.

The mixing unit 10 receives the input clock X1 in common and transfers the inverter blocks 11 connected in parallel to the common output node ND_C and the input clock X2 in common and transfers them to the common output node ND_C. Inverter blocks 12 are connected in parallel to each other, and each of the inverter blocks 11 and 12 transmits a power supply voltage or a ground voltage to the common output node ND_C according to each of the weight signals S1_0 to S1_n and S2_0 to S2_n. An impedance (Hi-Z) state is obtained.

Here, each of the inverter blocks 11 and 12 of the mixing unit 10 may be configured as a three-phase inverter (tri-state inverter), specifically, as shown in Figure 2, the power supply voltage (VDD) node Two PMOS transistors P1 and P2 connected in series between the common output node ND_C and two NMOS transistors N1 and N2 connected in series between the common output node ND_C and the ground voltage VSS node. Can be. At this time, the PMOS transistor P1 and the NMOS transistor N2 are controlled by the input clock X1, the PMOS transistor P2 is controlled by the weight signal, for example, S1_0, and the NMOS transistor N1 is in phase with the weight signal S1_0. This is controlled by the opposite signal S1B_0.

That is, when the weight signal S1_0 is enabled, the inverter block 11 of FIG. 2 raises the common output node ND_C to the power supply voltage VDD level or lowers the ground voltage VSS level according to the input clock X1. When the weight signal S1_0 is disabled, a high impedance state is obtained.

The output unit 20 may be configured as an inverter IV outputting a clock CLK_OUT having the same phase as an external clock by inverting the signal transmitted through the common output node ND_C.

In the conventional phase adjuster having such a configuration, the phases of the two input clocks X1 and X2 and the output clock CLK_OUT may appear as shown in FIG. 3 according to the states of the respective weighted signals S1_0 to S1_n, which will be described in detail below.

For example, assuming that there are five inverter blocks 11 receiving input clock X1 and five inverter blocks 12 receiving input clock X2, three weight signals S1_0 to S1_2 are enabled and 2 When the two weight signals S1_3 and S1_4 are disabled, the output clock CLK_OUT out of phase toward the input clock X1 is output between the two input clocks X1 and X2. In this case, it is assumed that the PMOS transistors and the NMOS transistors constituting the inverter blocks 11 and 12 are the same size.

In the same situation as above, when two weight signals S1_0 and S1_1 are enabled and three weight signals S1_2 to S1_4 are disabled, the output clock CLK_OUT out of phase toward the input clock X2 is output between the two input clocks X1 and X2. do. In addition, when all five weight signals S0 to S4 are enabled, the output clock CLK_OUT has the same phase as the input clock X1.

As such, the conventional phase adjuster generates output clocks CLK_OUT having a phase between two input clocks X1 and X2 according to the state of each weight signal S1_0 to S1_n using a plurality of inverter blocks 11 and 12 connected in parallel. .

However, when the operating frequency increases and the operating voltage decreases, the rising time and the polling time of the signal transmitted to the common output node ND_C may not be sufficient to drive the inverter IV of the output unit 20. .

That is, the conventional phase adjuster is composed of inverter blocks 11 and 12 configured as shown in FIG. 2, so that the rising time and the rising time of the signal output from each inverter block 11 and 12 even if the operating frequency increases and the operating voltage decreases The polling time is fixed.

Since the signals output from the inverter blocks 11 and 12 are mixed through the common output node ND_C, the rising time and the polling time of the common output node ND_C may cause the inverter IV of the output unit 20 to operate. There is a problem that the output clock CLK_OUT may not occur normally because it is not enough to drive.

Accordingly, it is an object of the present invention to adjust a phase without mixing two input clocks, so that a predetermined clock can be adjusted to a desired phase without error even when the operating frequency increases and the operating voltage decreases.

In addition, an object of the present invention is to adjust the rising time and the falling time of the clock in each inverter according to the situation, to adjust the predetermined clock to the desired phase in a high speed and low voltage operating environment.

A phase adjuster according to an embodiment of the present invention for achieving the above object, 'K' (K is smaller than 1 to the first input clock by comparing the phase of the reference clock and the first and second input clock) A control unit for outputting a first weighted signal having a weight of 1), a second weighted signal having a weight of '1-K' to the second input clock, and a selection signal; A delay unit configured to adjust the rising time and the falling time of the first and second input clocks as the first and second weighted signals, respectively, and output the first and second delayed clocks; And a selector which selects one of the first and second delay clocks as the selection signal and outputs the output clock having the same phase as the reference clock.

In the above configuration, the controller compares the phases of the reference clock and the first and second input clocks to give the first input clock a weight of 'K' (K is a prime number less than 1); And outputting a second weighted signal giving a weight of 'K-1' to a second input clock, and selecting the first delay clock when the phase of the first input clock is ahead of the phase of the reference clock. Preferably, the select signal is disabled and the select signal is selected to select the second delay clock when the phase of the second input clock is earlier than the phase of the reference clock.

The delay unit may include: a first delay line including a plurality of first fine delay blocks connected in series to adjust a rising time and a falling time of the first input clock using the first weight signal; And a second delay line including a plurality of second fine delay blocks connected in series to adjust the rising time and the polling time of the second input clock as the second weighted signal.

In the delay unit, each of the first fine delay blocks includes a first pull-up means and a first pull-down means, and resistances of the first pull-up means and the first pull-down means by the first weight signal. It is preferable to adjust the rising time and the falling time of the first input clock by adjusting.

In each of the first fine delay blocks, the first pull-up means includes: a first PMOS transistor having a gate connected to a ground voltage node and a source connected to a power supply voltage node; A plurality of second PMOS transistors having a gate for receiving a signal opposite in phase to the first weight signal, a source connected to the power supply voltage node, and a drain connected to a drain of the first PMOS transistor; And a third PMOS transistor having a gate configured to receive the first input clock, a source connected to a drain of the first PMOS transistor, and a drain connected to a node outputting the first delay clock. .

In each of the first fine delay blocks, the first pull-down means includes: a first NMOS transistor having a gate connected to the first input clock and a drain connected to a node outputting the first delay clock; A second NMOS transistor having a gate connected to a power supply voltage node, a drain connected to a source of the first NMOS transistor, and a source connected to a ground voltage node; And a plurality of third NMOS transistors having a gate receiving the first weight signal, a drain connected to a source of the first NMOS transistor, and a source connected to the ground voltage node.

In the delay unit, each of the second fine delay blocks includes a second pull-up means and a second pull-down means, and resistances of the second pull-up means and the second pull-down means by the second weight signal. It is preferable to adjust the rising time and the falling time of the second input clock by adjusting.

In each of the second fine delay blocks, the second pull-up means comprises: a fourth PMOS transistor having a gate connected to a ground voltage node and a source connected to a power supply voltage node; A plurality of fifth PMOS transistors having a gate for receiving a signal opposite in phase to the second weight signal, a source connected to the power supply voltage node, and a drain connected to a drain of the fourth PMOS transistor; And a sixth PMOS transistor having a gate receiving the second input clock, a source connected to a drain of the fourth PMOS transistor, and a drain connected to a node outputting the second delay clock. .

In each of the second fine delay blocks, the second pull-down means includes: a fourth NMOS transistor having a gate connected to the second input clock and a drain connected to a node outputting the second delay clock; A fifth NMOS transistor having a gate connected to a power supply voltage node, a drain connected to a source of the fourth NMOS transistor, and a source connected to a ground voltage node; And a plurality of sixth NMOS transistors having a gate configured to receive the second weight signal, a drain connected to a source of the fourth NMOS transistor, and a source connected to the ground voltage node.

On the other hand, the selection unit, a third inverter for inverting the selection signal; First and second NAND gates for NAND combining the first delay clock and a signal output from the third inverter; Third and fourth NAND gates for NAND combining the selection signal and the second delay clock; A fifth NAND gate NAND combining the signal output from the first NAND gate and the signal output from the third NAND gate; And a sixth NAND gate NAND combining the signal output from the second NAND gate and the signal output from the fourth NAND gate, wherein the output clock is provided through a common output node of the fifth and sixth NAND gates. It is preferable to output.

According to an aspect of the present invention, there is provided a delay locked loop including: a first controller configured to compare a phase of a reference clock and a feedback clock to output a control signal; A coarse delay unit configured to delay the reference clock as a unit delay cell unit as the control signal and output the first and second coarse delay clocks having a unit delay cell difference; Comparing the phases of the reference clock with the first and second coarse delay clocks to weight the first coarse delay clock, a second weighted signal to weight the second coarse delay clock, and selecting A second control unit which outputs a signal; A fine delay unit configured to output the first and second fine delay clocks by adjusting the rising time and the falling time of the first and second coarse delay clocks as the first and second weighted signals, respectively; And a selector which selects one of the first and second fine delay clocks as the selection signal and outputs the output clock having the same phase as the reference clock.

In the above configuration, the coarse delay unit may include: a first coarse delay line configured to delay the reference clock in unit delay cell units as the control signal and output the coarse delay clock as the first coarse delay clock; And a second coarse delay line having a difference between the first coarse delay line and one unit delay cell and outputting the second coarse delay clock to the second coarse delay clock by delaying the reference clock by a unit delay cell as the control signal. This is preferred.

The second controller compares phases of the reference clock and the first and second coarse delay clocks to give a weight of 'K' (K is a prime number less than 1) to the first coarse delay clock. Outputs a signal and a second weighted signal giving a weight of '1-K' to the second coarse delay clock, and wherein the first fine delay is performed when the phase of the first coarse delay clock precedes the second coarse delay clock. Enabling the selection signal to select a clock and disabling the selection signal to select the second fine delay clock when the phase of the second coarse delay clock is ahead of the phase of the first coarse delay clock. Do.

The fine delay unit may include: a first fine delay line including a plurality of first fine delay blocks connected in series to adjust a rising time and a falling time of the first coarse delay clock as the first weighted signal; And a second fine delay line composed of a plurality of second fine delay blocks connected in series to adjust the rising time and the polling time of the second coarse delay clock as the second weighted signal.

In the fine delay unit, each of the first fine delay blocks includes a first pull-up means and a first pull-down means, wherein the first pull-up means and the first pull-down means It is preferable to adjust the resistance to adjust the rising time and the falling time of the first coarse delay clock.

In each of the first fine delay blocks, the first pull-up means includes: a first PMOS transistor having a gate connected to a ground voltage node and a source connected to a power supply voltage node; A plurality of second PMOS transistors having a gate for receiving a signal opposite in phase to the first weight signal, a source connected to the power supply voltage node, and a drain connected to a drain of the first PMOS transistor; And a third PMOS transistor having a gate configured to receive the first coarse delay clock, a source connected to a drain of the first PMOS transistor, and a drain connected to a node outputting the first fine delay clock. desirable.

In each of the first fine delay blocks, the first pull-down means includes: a first NMOS transistor having a gate connected to the first coarse delay clock and a drain connected to a node outputting the first fine delay clock; A second NMOS transistor having a gate connected to a power supply voltage node, a drain connected to a source of the first NMOS transistor, and a source connected to a ground voltage node; And a plurality of third NMOS transistors having a gate receiving the first weight signal, a drain connected to a source of the first NMOS transistor, and a source connected to the ground voltage node.

In the fine delay unit, each second fine delay block includes a second pull-up means and a second pull-down means, wherein the second pull-up means and the second pull-down means It is preferable to adjust the resistance to adjust the rising time and the falling time of the second coarse delay clock.

In each of the second fine delay blocks, the second pull-up means comprises: a fourth PMOS transistor having a gate connected to a ground voltage node and a source connected to a power supply voltage node; A plurality of fifth PMOS transistors having a gate for receiving a signal opposite in phase to the second weight signal, a source connected to the power supply voltage node, and a drain connected to a drain of the fourth PMOS transistor; And a sixth PMOS transistor having a gate configured to receive the second coarse delay clock, a source connected to a drain of the fourth PMOS transistor, and a drain connected to a node outputting the second fine delay clock. desirable.

In each of the second fine delay blocks, the second pull down means may include: a fourth NMOS transistor having a gate connected to the second coarse delay clock and a drain connected to a node outputting the second fine delay clock; A fifth NMOS transistor having a gate connected to a power supply voltage node, a drain connected to a source of the fourth NMOS transistor, and a source connected to a ground voltage node; And a plurality of sixth NMOS transistors having a gate configured to receive the second weight signal, a drain connected to a source of the fourth NMOS transistor, and a source connected to the ground voltage node.

On the other hand, the selection unit, a third inverter for inverting the selection signal; First and second NAND gates for NAND combining the first fine delay clock and a signal output from the third inverter; Third and fourth NAND gates for NAND combining the selection signal and the second fine delay clock; A fifth NAND gate NAND combining the signal output from the first NAND gate and the signal output from the third NAND gate; And a sixth NAND gate NAND combining the signal output from the second NAND gate and the signal output from the fourth NAND gate, wherein the output is performed through a common output node of the fifth and sixth NAND gates. It is preferable to output the clock.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

As an embodiment of the present invention, the structure of FIG. 4 is disclosed. The embodiment of the present invention compares the phase of the internal clock CLK_IN with the phases of the two clocks X1 and X2 to give a weight to any one of the two clocks X1 and X2 to poll the rising time and polling. After adjusting the time, one of two clocks whose phase is adjusted is selected to output an output clock CLK_OUT having a phase between two clocks X1 and X2.

In detail, the embodiment of FIG. 4 includes an input buffer unit 100, a replica delay unit 200, a control unit 300, and a variable delay unit 400.

The input buffer unit 100 generates an internal clock CLK_IN of a full swing by buffering the external clock EXT_CLK of a small swing.

The replica delay unit 200 replicates the signal output from the initial variable delay unit 400 and outputs the delayed signal to the feedback clock FB_CLK. In this case, all the paths through which the output of the delay locked loop is transmitted to the external DQ pin are modeled in the replica delay unit 200.

The control unit 300 compares the phases of the internal clock CLK_IN and the feedback clock FB_CLK, outputs the control signal CTRL for controlling the coarse delay unit 410 of the variable delay unit 400, and outputs the coarse delay unit 410. The phase delays of the coarse delay clocks X1 and X2 and the internal clock CLK_IN are compared and output as a plurality of weight signals S3_0 to S3_n, S4_0 to S4_n and the selection signal SEL for controlling the phase adjuster 420 of the variable delay unit 400. Here, each of the weight signals S4_0 to S4_n is a signal whose phase is opposite to that of each of the weight signals S3_0 to S3_n. Since the phase comparator 300 can be easily implemented by those skilled in the art by using a flip-flop or the like, a detailed description of the configuration will be omitted.

The variable delay unit 400 delays the internal clock CLK_IN according to the control signal CTRL and outputs the coarse delay unit 410 for outputting the two coarse delay clocks X1 and X2, and the two coarse delays according to the weight signals S3_0 to S3_n and S4_0 to S4_n. After adjusting the phases of the clocks X1 and X2, the phase adjusting unit 420 selects one of two clocks whose phases are adjusted according to the selection signal SEL and outputs the output clock CLK_OUT.

Here, the course delay unit 410 may be configured as, for example, dual course delay lines 411 and 412 as shown in FIG. 5, and each of the course delay lines 411 and 412 is one unit delay cell (UDC). It works with a difference of).

That is, the number of unit delay cells (UDCs) of the higher course delay line 411 may be configured to be one less or one more than the number of unit delay cells (UDCs) of the lower course delay lines 412.

The coarse delay unit 410 having such a configuration may determine the number of unit delay cells (UDCs) used for delay in the upper coarse delay line 411 according to the control signal CTRL provided from the controller 300. The number of unit delay cells (UDCs) used for delay in the lower coarse delay line 412 is changed to two, four, six, and the like.

Accordingly, the internal clock CLK_IN is delayed through the upper coarse delay line 411 and the lower coarse delay line 412 and output as two coarse delay clocks X1 and X2 having one unit delay cell (UDC) difference.

For example, the phase controller 420 adjusts the rising time and the falling time of the coarse delay clock X1 according to each weight signal S3_0 to S3_n as shown in FIG. 6 and outputs the falling time as the fine delay clock X1_D. The upper fine delay line 421 to adjust the rising time and the polling time of the coarse delay clock X2 according to each weight signal S4_0 to S4_n, and output the fine fine delay line 422 to the fine delay clock X2_D, and the selection signal SEL. Accordingly, the selector 423 may select one of two fine delay clocks X1_D and X2_D to output the output clock CLK_OUT.

Here, the upper fine delay line 421 is configured to determine the rising time and the polling time of the coarse delay clock X1 according to i (where i is a natural number larger than 1 and smaller than n) weighted signals, for example, the weighted signals S3_0 to S3_2. It consists of a series of fine delayed blocks FD1 connected in series to adjust and invert the adjusted clock, and the lower fine delay line 422 is the rising of the coarse delay clock X2 according to i weighted signals, e.g., S4_0 to S4_2. It can consist of multiple serially connected fine delay blocks FD2 that adjust the time and polling time and invert the adjusted clock.

Each fine delay block FD1 includes a plurality of PMOS transistors P3 to P6 and nodes ND1 connected in parallel between the power supply voltage VDD node and the node ND1 as shown in FIG. 7. PMOS transistor P7 connected between output node Y, NMOS transistor N3 connected between output node Y and node ND2, and parallel between node ND2 and ground voltage VSS line The NMOS transistors N4 to N7 may be connected to each other.

At this time, the PMOS transistor P3 is always turned on by the ground voltage VSS, and each of the PMOS transistors P4 to P6 is controlled by signals S3B_0 to S3B_2 that are in phase with each of the weight signals S3_0 to S3_2. do. The PMOS transistor P7 and the NMOS transistor N3 are controlled by the coarse delay clock X1, and the NMOS transistor N4 is always turned on by the power supply voltage VDD. N7) is controlled by each weight signal S3_0-S3_2.

The fine delay block FD1 having the configuration shown in FIG. 7 raises the output node Y to the power supply voltage level when the coarse delay clock X1 is at a low level, and turns the output node Y when the coarse delay clock X1 is at a high level. Lower to ground voltage level.

When the weight signals S3B_0 to S3B_2 are all enabled, since the PMOS transistors P4 to P6 and the NMOS transistors N5 to N7 are both turned on to decrease the resistance, the clock output to the output node Y is reduced. Rising time or polling time is reduced. That is, the rising time or polling time of the clock output to the output node Y is adjusted according to the weight signals S3B_0 to S3B_2.

Meanwhile, the selector 423 includes an inverter IV2 for inverting the selection signal SEL, two NAND gates NA1 and NA3 for NAND combining a fine delay clock X1_D and a signal output from the inverter IV2, and a selection signal SEL and fine. NAND gate (NA5) which NAND combines the two NAND gates (NA2, NA4) and NAND gate (NA1) and the NAND gate (NA2) output NAND combination of delay clock X2_D to the output node , NAND gate NA6 may be configured by NAND combining the signal output from the NAND gate NA3 and the signal output from the NAND gate NA4 to the output node, and the same phase as the internal clock CLK_IN through the output node. Outputs an output clock CLK_OUT with

Hereinafter, the operation of an embodiment of the present invention will be described in detail with reference to FIGS. 4 to 7.

First, when the external clock EXT_CLK of the small swing is input, the external clock EXT_CLK is buffered through the input buffer unit 100 and output to the internal clock CLK_IN of the full swing.

After the internal clock CLK_IN passes through the variable delay unit 400, the internal clock CLK_IN is replicaly delayed through the replica delay unit 200 and output to the feedback clock FB_CLK. At this time, when the internal clock CLK_IN is initially input to the variable delay unit 400, the internal clock CLK_IN is delayed according to the delay value initially set in the variable delay unit 400 and transmitted to the replica delay unit 200.

The controller 300 generates a control signal CTRL for controlling the coarse delay unit 410 of the variable delay unit 400 by comparing the phases of the internal clock CLK_IN and the feedback clock FB_CLK. At this time, if the phase of the feedback clock FB_CLK is ahead of the phase of the internal clock CLK_IN, the controller 300 outputs a control signal CTRL for increasing the delay amount of the coarse delay unit 410, and the phase of the internal clock CLK_IN is the feedback clock. If it is ahead of the phase of FB_CLK, the control signal CTRL for reducing the delay amount of the coarse delay unit 410 is output.

In response to the control signal CTRL, the coarse delay unit 410 delays the internal clock CLK_IN in unit delay cell units and outputs the coarse delay clocks X1 and X2, and the controller 300 outputs the coarse delay clocks X1 and X2 and the internal clock CLK_IN. The plurality of weight signals S3_0 to S3_n and S4_0 to S4_n and the selection signal SEL for controlling the phase adjuster 420 are generated by comparing the phases of the plurality of phases.

At this time, the control unit 300 compares the phases of the coarse delay clocks X1 and X2 with the internal clock CLK_IN to give the coarse delay clock X1 a weight of 'K' (where K is a prime number less than 1). S3_n and a plurality of weight signals S4_0 to S4_n that give a weight of '1-K' to the course delay clock X2 are generated.

When the phase of the coarse delay clock X1 is ahead of the coarse delay clock X2, the controller 300 enables the selection signal SEL to select the fine delay clock X1_D, and the phase of the coarse delay clock X2 is the coarse delay clock X1. Prior to the phase of, disables the selection signal SEL to select fine delay clock X2_D.

The phase adjuster 420 generates the fine delay clocks X1_D and X2_D by adjusting the rising time and the falling time of the coarse delay clocks X1 and X2 according to the plurality of weight signals S3_0 to S3_n and S4_0 to S4_n, respectively, and then selecting signal SEL. Select one of the fine delay clocks X1_D and X2_D to output to the output clock CLK_OUT.

In this case, when the plurality of weight signals S3_0 to S3_n are all enabled, the rising and polling times of the fine delay clock X1_D become minimum, and when the plurality of weight signals S3_0 to S3_n are all disabled, the rising of the fine delay clock X1_D And the polling time is maximum.

When the phase of the coarse delay clock X1 is earlier than the phase of the coarse delay clock X2, the upper fine delay line 421 is selected by the selection signal SEL to shift the phase of the coarse delay clock X1 according to the plurality of weight signals S3_0 to S3_n. Adjusted. At this time, if the phase of the fine delay clock X1_D whose phase is adjusted is the same as the phase of the fine delay clock X2_D, the coarse delay unit 410 is adjusted so that the phase of the coarse delay clock X2 is earlier than the phase of the coarse delay clock X1, and the selection signal SEL The lower fine delay line 422 is selected to adjust the phase of the coarse delay clock X2 according to the plurality of weight signals S4_0 to S4_n.

For example, the feedback clock FB_CLK passing through the upper coarse delay line 411 according to the control signal CTRL provided from the controller 300 passes through the three unit delay cells UDC and passes the lower coarse delay line 412. When the feedback clock FB_CLK passes through the four unit delay cells UDC, if the weight of the weight signals S3_0 to S3_n is determined to be 0 by the controller 300, the course delay passing through the upper course delay line 411 is performed. The clock X1 outputs as the fine delay clock X1_D as it is.

However, when the controller 300 determines that the phase of the feedback clock FB_CLK is ahead of the phase of the internal clock CLK_IN, the weight of the weight signals S3_0 to S3_n gradually increases, and as the weight of the weight signals S3_0 to S3_n approaches 1, Among the two coarse delay clocks X1 and X2, a fine delay clock X1_D close to the phase of the coarse delay clock X2 is output. Then, when the weights of the weight signals S3_0 to S3_n become 1, the fine delay clock X1_D having the same phase as the coarse delay clock X2 is output.

At this time, if the control unit 300 determines that the phase of the feedback clock FB_CLK is ahead of the phase of the internal clock CLK_IN, shift left occurs in the upper coarse delay line 411. That is, the upper coarse delay line 411 outputs a coarse delay clock X1 through three unit delay cells UDC and outputs a coarse delay clock X1 through five unit delay cells UDC.

In addition, if it is necessary to increase the delay in the feedback clock FB_CLK even after the shift left occurs in the upper course delay line 411, the weight of the weight signals S3_0 to S3_n may be reduced. Decreasing the weight of the weight signals S3_0 to S3_n is equivalent to increasing the weight of the weight signals S4_0 to S4_n, and means that the fine delay clock X2_D approaches the phase of the coarse delay clock X1.

In the case where the delay is to be reduced, it will be apparent to those skilled in the art that the above-described method can be achieved by applying the reverse method, and thus the detailed description will be omitted.

As described above, the embodiment of the present invention compares the phases of the internal clock CLK_IN and the two coarse delay clocks X1 and X2 to weight one of the two coarse delay clocks X1 and X2 to adjust the rising time and the polling time, respectively. After that, one of the two phase-controlled clocks X1_D and X2_D may be selected to generate an output clock CLK_OUT having the same phase as the internal clock CLK_IN.

That is, the embodiment of the present invention delays the two coarse delay clocks X1 and X2 according to the weight signals S3_0 to S3_n and S4_0 to S4_n, respectively, and then selects one of the delayed clocks X1_D and X2_D, and thus the phase of the predetermined clock. By adjusting, it is possible not to have a great influence on adjusting a predetermined clock to a desired phase even if the operating frequency increases and the operating voltage decreases.

In addition, the embodiment of the present invention can finely adjust the rising time and the polling time of the clock in each fine delay block FD1 according to the situation, so that even if the operating frequency increases and the operating voltage decreases, the predetermined clock is not affected. The effect can be adjusted to the desired phase.

As described above, the present invention adjusts the phase of a predetermined clock using a method of selecting one of delayed clocks after delaying each of two input clocks according to weights, so that the operating frequency increases and the operating voltage decreases without error. There is an effect that the predetermined clock can be adjusted to the desired phase.

In addition, when the phase of the predetermined clock is adjusted, the rising time and the falling time of the clock can be finely adjusted according to a situation, and thus, the predetermined clock can be adjusted to a desired phase even in a high speed and low voltage operating environment.

While the invention has been shown and described with reference to specific embodiments, the invention is not limited thereto, and the invention is not limited to the scope of the invention as defined by the following claims. Those skilled in the art will readily appreciate that modifications and variations can be made.

Claims (23)

A control unit for comparing a phase of a reference clock with a phase of the first and second input clocks to output a first weighted signal that weights the first input clock, a second weighted signal that weights the second input clock, and a selection signal ; A delay unit configured to adjust the rising time and the falling time of the first and second input clocks as the first and second weighted signals, respectively, and output the first and second delayed clocks; And And a selector which selects one of the first and second delay clocks as the selection signal and outputs the output clock having the same phase as the reference clock. Claim 2 has been abandoned due to the setting registration fee. The method of claim 1, The controller compares phases of the reference clock and the first and second input clocks to give the first input clock a weight of 'K' (K is a prime number less than 1), and the second input clock. And outputting a second weighted signal having a weight of 'K-1'. Claim 3 was abandoned when the setup registration fee was paid. The method of claim 1, The controller enables the selection signal to select the first delay clock when the phase of the first input clock is ahead of the phase of the reference clock, and the phase of the second input clock is greater than the phase of the reference clock. Disabling said select signal to select said second delay clock when preceding. Claim 4 was abandoned when the registration fee was paid. The method of claim 1, The delay unit, A first delay line including a plurality of first fine delay blocks connected in series for adjusting a rising time and a polling time of the first input clock as the first weighted signal; And And a second delay line consisting of a plurality of second fine delay blocks connected in series to adjust the rising time and the falling time of the second input clock as the second weighted signal. Claim 5 was abandoned upon payment of a set-up fee. The method of claim 4, wherein Each of the first fine delay blocks includes a first pull-up means and a first pull-down means, and adjusts the resistances of the first pull-up means and the first pull-down means by the first weight signal. A phase adjuster that adjusts the rising and falling times of the input clock. Claim 6 was abandoned when the registration fee was paid. The first pull-up means, A first PMOS transistor having a gate connected with the ground voltage node and a source connected with the power supply voltage node; A plurality of second PMOS transistors having a gate for receiving a signal opposite in phase to the first weight signal, a source connected to the power supply voltage node, and a drain connected to a drain of the first PMOS transistor; And And a third PMOS transistor having a gate receiving the first input clock, a source connected to a drain of the first PMOS transistor, and a drain connected to a node outputting the first delay clock. Phase adjuster. Claim 7 was abandoned upon payment of a set-up fee. The method of claim 5, The first pull down means, A first NMOS transistor having a gate connected to the first input clock and a drain connected to a node outputting the first delay clock; A second NMOS transistor having a gate connected to a power supply voltage node, a drain connected to a source of the first NMOS transistor, and a source connected to a ground voltage node; And And a plurality of third NMOS transistors having a gate receiving the first weighted signal, a drain connected to a source of the first NMOS transistor, and a source connected to the ground voltage node. Claim 8 was abandoned when the registration fee was paid. The method of claim 4, wherein Each of the second fine delay blocks includes a second pull-up means and a second pull-down means, and adjusts the resistance of the second pull-up means and the second pull-down means by the second weight signal. 2 Phase adjuster, which adjusts the rising and falling times of the input clock. Claim 9 was abandoned upon payment of a set-up fee. The method of claim 8, The second pull-up means, A fourth PMOS transistor having a gate connected to the ground voltage node and a source connected to the power supply voltage node; A plurality of fifth PMOS transistors having a gate for receiving a signal opposite in phase to the second weight signal, a source connected to the power supply voltage node, and a drain connected to a drain of the fourth PMOS transistor; And And a sixth PMOS transistor having a gate for receiving the second input clock, a source connected to the drain of the fourth PMOS transistor, and a drain connected to a node for outputting the second delay clock. Phase adjuster. Claim 10 has been abandoned due to the setting registration fee. The method of claim 9, A fourth NMOS transistor having a gate connected to the second input clock and a drain connected to a node outputting the second delay clock; A fifth NMOS transistor having a gate connected to a power supply voltage node, a drain connected to a source of the fourth NMOS transistor, and a source connected to a ground voltage node; And And a plurality of sixth NMOS transistors having a gate receiving the second weighted signal, a drain connected to a source of the fourth NMOS transistor, and a source connected to the ground voltage node. Claim 11 was abandoned upon payment of a setup registration fee. The method of claim 1, The selection unit, A third inverter for inverting the selection signal; First and second NAND gates for NAND combining the first delay clock and a signal output from the third inverter; Third and fourth NAND gates for NAND combining the selection signal and the second delay clock; A fifth NAND gate NAND combining the signal output from the first NAND gate and the signal output from the third NAND gate; And And a sixth NAND gate NAND combining the signal output from the second NAND gate and the signal output from the fourth NAND gate. And output the output clock through the common output node of the fifth and sixth NAND gates. A delay locked loop for performing a delay and a fixed operation as a reference clock and a feedback clock having a replica delayed from the reference clock, A first controller which compares a phase of the reference clock and the feedback clock and outputs a control signal; A coarse delay unit configured to delay the reference clock as a unit delay cell unit as the control signal and output the first and second coarse delay clocks having a unit delay cell difference; Comparing the phases of the reference clock with the first and second coarse delay clocks to weight the first coarse delay clock, a second weighted signal to weight the second coarse delay clock, and selecting A second control unit which outputs a signal; A fine delay unit configured to output the first and second fine delay clocks by adjusting the rising time and the falling time of the first and second coarse delay clocks as the first and second weighted signals, respectively; And And a selector configured to select one of the first and second fine delay clocks as the selection signal and output the output clock having the same phase as the reference clock. Claim 13 was abandoned upon payment of a registration fee. 13. The method of claim 12, The course delay unit, A first coarse delay line configured to delay the reference clock in unit delay cell units as the control signal and output the first coarse delay clock as the first coarse delay clock; And And a second coarse delay line having a difference between the first coarse delay line and one unit delay cell and outputting the second coarse delay clock to the second coarse delay clock by delaying the reference clock by a unit delay cell as the control signal. Characterized by a delay lock loop. Claim 14 has been abandoned due to the setting registration fee. 13. The method of claim 12, The second controller compares the phases of the reference clock and the first and second coarse delay clocks to give a weight of 'K' (K is a prime number less than 1) to the first coarse delay clock. And outputting a second weighted signal giving a weight of '1-K' to the second coarse delay clock. Claim 15 was abandoned upon payment of a registration fee. 13. The method of claim 12, The second control unit enables the selection signal to select the first fine delay clock when the phase of the first coarse delay clock is earlier than the second coarse delay clock, and the phase of the second coarse delay clock is changed. And deactivating the selection signal to select the second fine delay clock when ahead of phase of the first coarse delay clock. Claim 16 has been abandoned due to the setting registration fee. 13. The method of claim 12, The fine delay unit, A first fine delay line composed of a plurality of first fine delay blocks connected in series for adjusting a rising time and a polling time of the first coarse delay clock as the first weighted signal; And And a second fine delay line composed of a plurality of second fine delay blocks connected in series to adjust the rising time and the polling time of the second coarse delay clock as the second weighted signal. . Claim 17 has been abandoned due to the setting registration fee. The method of claim 16, Each of the first fine delay blocks includes a first pull-up means and a first pull-down means, and adjusts the resistances of the first pull-up means and the first pull-down means by the first weight signal. A delay-locked loop that adjusts the rising and polling times of the 1-course delay clock. Claim 18 was abandoned upon payment of a set-up fee. The method of claim 17, A first PMOS transistor having a gate connected with the ground voltage node and a source connected with the power supply voltage node; A plurality of second PMOS transistors having a gate for receiving a signal opposite in phase to the first weight signal, a source connected to the power supply voltage node, and a drain connected to a drain of the first PMOS transistor; And And a third PMOS transistor having a gate receiving the first coarse delay clock, a source connected to a drain of the first PMOS transistor, and a drain connected to a node outputting the first fine delay clock. Delay-locked loop. Claim 19 was abandoned upon payment of a registration fee. The method of claim 17, The first pull down means, A first NMOS transistor having a gate that receives the first coarse delay clock and a drain that is connected to a node that outputs the first fine delay clock; A second NMOS transistor having a gate connected to a power supply voltage node, a drain connected to a source of the first NMOS transistor, and a source connected to a ground voltage node; And A plurality of third NMOS transistors having a gate receiving the first weighted signal, a drain connected to a source of the first NMOS transistor, and a source connected to the ground voltage node; . Claim 20 was abandoned upon payment of a registration fee. The method of claim 16, Each of the second fine delay blocks includes a second pull-up means and a second pull-down means, and adjusts the resistance of the second pull-up means and the second pull-down means by the second weight signal. A delay-locked loop that adjusts the rising and falling times of the two-course delay clock. Claim 21 has been abandoned due to the setting registration fee. 21. The method of claim 20, The second pull-up means, A fourth PMOS transistor having a gate connected to the ground voltage node and a source connected to the power supply voltage node; A plurality of fifth PMOS transistors having a gate for receiving a signal opposite in phase to the second weight signal, a source connected to the power supply voltage node, and a drain connected to a drain of the fourth PMOS transistor; And And a sixth PMOS transistor having a gate configured to receive the second coarse delay clock, a source connected to the drain of the fourth PMOS transistor, and a drain connected to a node outputting the second fine delay clock. Delay-locked loop. Claim 22 is abandoned in setting registration fee. The second pull down means, A fourth NMOS transistor having a gate connected to the second coarse delay clock and a drain connected to a node outputting the second fine delay clock; A fifth NMOS transistor having a gate connected to a power supply voltage node, a drain connected to a source of the fourth NMOS transistor, and a source connected to a ground voltage node; And And a plurality of sixth NMOS transistors having a gate receiving the second weighted signal, a drain connected to a source of the fourth NMOS transistor, and a source connected to the ground voltage node. . Claim 23 was abandoned upon payment of a set-up fee. 13. The method of claim 12, The selection unit, A third inverter for inverting the selection signal; First and second NAND gates for NAND combining the first fine delay clock and a signal output from the third inverter; Third and fourth NAND gates for NAND combining the selection signal and the second fine delay clock; A fifth NAND gate NAND combining the signal output from the first NAND gate and the signal output from the third NAND gate; And And outputting the output clock through the common output node of the fifth and sixth NAND gates.

Images