KR20070097664A - Liquid crystal display and method for driving the same - Google Patents

Abstract

An LCD(Liquid Crystal Display) device and a driving method thereof are provided to drive effectively a screen and control the direction of a scan process by implementing an optimal configuration without using a frame memory. A liquid crystal panel(110) includes pixels defined by gate and data lines, and disposes thin film transistors. A gate driver(120) sequentially supplies a scan pulse in a scan processing direction to the gate lines of the liquid crystal panel. A data driver(120), which is formed at an end portion of the scan processing direction, supplies a data voltage to the data lines. A timing controller(141) adjacent to the data driver controls operation timing of the gate and data drivers by outputting gate and data control signals. First signal line groups(150) with a line on glass type transmit the gate control signal from the data driver to a start stage of the scan processing direction. Second signal line groups(123), which are formed on the data driver, connect the first signal line groups to each other.

Description

Liquid crystal display and method for driving the same {Liquid crystal display and method for driving the same}

1 is a configuration diagram of a liquid crystal display according to the prior art.

2 is a block diagram of a liquid crystal display according to an exemplary embodiment of the present invention.

3 is a waveform diagram illustrating a process of generating a scan pulse in the gate driver of FIG. 1.

4 is a waveform diagram illustrating a gate start pulse generated during one frame period.

5 is a flowchart illustrating a method of driving a liquid crystal display according to an exemplary embodiment of the present invention.

(Explanation of symbols for the main parts of the drawing)

110: liquid crystal panel 120: gate driver

130: data driver 140: printed circuit board

141: timing controller 142: gamma voltage generator

143: power supply unit 150: first signal line group

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a liquid crystal display device and a driving method thereof, and more particularly, to a liquid crystal display device and a driving method thereof for efficiently controlling a scanning progress direction on a liquid crystal panel.

The liquid crystal display device forms a liquid crystal layer having anisotropic dielectric constant between the color filter substrate, which is the upper and lower transparent insulating substrates, and the array substrate, and then adjusts the intensity of the electric field formed in the liquid crystal layer to change the molecular arrangement of the liquid crystal material. The display device expresses a desired image by adjusting the amount of light transmitted through the color filter substrate. As the liquid crystal display, a thin film transistor liquid crystal display (TFT LCD) using a thin film transistor (TFT) as a switching element is mainly used.

1 is a configuration diagram of a liquid crystal display according to the prior art.

As shown in FIG. 1, a conventional liquid crystal display device includes a liquid crystal panel 10 configured to display an image including a plurality of pixels in which regions are defined by gate lines GL1 to GLm and data lines DL1 to DLn. A driving circuit part for driving a liquid crystal panel is provided.

The driving circuit unit includes a gate driver 20 and a data driver 30 for driving the gate lines GL1 to GLm and the data lines DL1 to DLn of the liquid crystal panel 10, and a timing controller for controlling driving timings thereof. The unit 41, the liquid crystal panel 10, a gamma voltage generation unit 42 for generating gamma voltages (reference voltages), a power supply unit 43 for supplying driving voltages for driving the driving circuit unit, and the like.

The gate driver 20 and the data driver 30 are separated into a plurality of integrated circuits (ICs) and manufactured as a chip-shaped gate driver 21 and a source driver 31, each of which is a tape carrier package. They are mounted on (TCP; Tape carrier packages) 22 and 32 to drive the gate lines GL1 to GLm and the data lines DL1 to DLn of the liquid crystal panel 10.

Circuits such as the timing controller 41, the gamma voltage generator 42, the power supply 43, and the like are connected to a printed circuit board (PCB) 40 connected to the data driver 30, or the like. It is usually mounted on a main printed circuit board.

1 illustrates a configuration of a basic liquid crystal display device for normally displaying a screen, in which a printed circuit board 40 and a data driver 30 are positioned above the liquid crystal panel 10.

In this case, the scan pulse generated from the gate driver 20 is sequentially applied from the first gate line GL1 to the last gate line GLm under the control of the timing controller 41, and is supplied in response to the scan pulse. As the data lines DL1 to DLn are driven by the voltage, the normal screen may be driven from the upper side to the lower side of the liquid crystal panel 10.

By the way, in a liquid crystal display device having a specific purpose such as a model using a light emitting diode (LED) backlight unit, the printed circuit board 40 including the data driver 30 is disposed on the lower side of the liquid crystal panel 10 as necessary. In this case, since the scan progress direction in which the scan pulses are sequentially applied using the frame memory or the like must be adjusted again from the upper side to the lower side, the required parts and the cost are unnecessarily increased.

Therefore, the technical problem to be achieved by the present invention is that when the data driver is located on the lower side of the liquid crystal panel, the liquid crystal display which can efficiently drive the normal screen from the upper side to the lower side of the liquid crystal panel by optimizing the configuration without using the frame memory To provide a device.

Another object of the present invention is to provide a method of driving such a liquid crystal display.

Technical problems to be achieved by the present invention are not limited to the above-mentioned technical problems, and other technical problems not mentioned above will be clearly understood by those skilled in the art from the following description. Could be.

According to an aspect of the present invention, a liquid crystal display device includes a liquid crystal panel including pixels divided into gate lines and data lines that cross each other, and a thin film transistor is arranged in units of pixels; A gate driver sequentially supplying scan pulses to the gate lines of the liquid crystal panel in a scan progress direction, a data driver positioned at an end of the scan progress direction and supplying a data voltage to the data lines of the liquid crystal panel; A timing controller configured to be adjacent to the data driver and output a gate control signal and a data control signal to control driving timing of the gate driver and the data driver; and from the data driver to a start end of the scan progress direction To directly transmit the gate control signal. And a second signal line group formed on the data driver so as to be connected to the first signal line group and connecting the first signal line group to each other. do.

Preferably, the gate driver includes a plurality of gate drivers, and the first and second signal line groups are configured to receive the gate control signal and to transmit the gate control signal to a top gate driver positioned at a start end of the scan direction. .

The gate control signal includes a gate start pulse (GSP), a gate shift clock (GSC), a gate output enable (GOE), and the like.

In addition, the driving method of the liquid crystal display according to an exemplary embodiment of the present invention includes the steps of outputting a gate control signal and a data control signal to control a driving timing of a timing controller located at an end of a scan progress direction, and the gate control signal; Transmitting from the data driver connected to the timing controller to the start end of the scan direction through a first signal line group of a line on glass type and a second signal line group formed on the data driver; A driver sequentially supplying scan pulses to gate lines of a liquid crystal panel in a scan progress direction according to the gate control signal, and the data driver positioned adjacent to the timing controller part according to the data control signal Supplying data voltage to the data lines of the liquid crystal panel And displaying, by the liquid crystal panel, an image according to a scan pulse supplied through the gate lines and a data voltage supplied to the data lines in response to the scan pulse.

The gate control signal includes a gate start pulse (GSP), a gate shift clock (GSC), a gate output enable (GOE), and the like.

The supplying of the scan pulse may include supplying a gate start pulse and a gate shift clock, shifting the gate start pulse according to the gate shift clock to generate a shift pulse every one horizontal period, and outputting a gate output signal. Enabling the scan pulse to generate the scan pulse so as to correspond to the shift pulse in a high period or a low period of the gate output enable, and the scan pulse is sequentially applied to the gate lines according to the scan progress direction It is preferred to include the step of being fed.

Specific details of other embodiments are included in the detailed description and the drawings. Advantages and features of the present invention and methods for achieving them will be apparent with reference to the embodiments described below in detail with the accompanying drawings. Like reference numerals refer to like elements throughout.

Hereinafter, a liquid crystal display and a driving method thereof according to an exemplary embodiment of the present invention will be described in detail with reference to the accompanying drawings.

2 is a block diagram of a liquid crystal display according to an exemplary embodiment of the present invention.

Referring to FIG. 2, the liquid crystal display according to the exemplary embodiment may be largely divided into a liquid crystal panel 110 and a driving circuit unit for driving the liquid crystal panel 110.

The liquid crystal panel 110 is composed of a plurality of pixels arranged in a matrix type, and a plurality of gate lines GL1 to GLm and data lines DL1 to DLn separating the pixels are arranged to cross the gate line. Images are displayed on each of the pixels according to scan pulses sequentially applied through the fields GL1 to GLm and data voltages applied through the data lines DL1 to DLn.

In this case, each pixel is a thin film transistor TFT, a liquid crystal capacitor Clc, and a storage arranged in units of pixels at intersections of the gate lines GL1 to GLm and the data lines DL1 to DLn, as shown in FIG. 2. It may be represented by an equivalent circuit including a capacitor Cst.

The driving circuit unit includes a timing controller unit 141, a gate driver unit 120, a data driver unit 130, a first signal line group 150 of a line on glass (LOG) type, a power supply unit 143, and gamma. And a voltage generator 142.

The timing controller 141 controls the gate driver 120 using the pixel data R, G, and B inputted from the system SYS, the vertical and horizontal synchronization signals Hsync, Vsync, and the clock CLK. Each control timing is generated by generating a gate control signal and a data control signal for controlling the data driver 130.

The gate control signal includes a gate start pulse (GSP), a gate shift clock (GSC), a gate output enable (GOE), and the data control signal as a source start. A source start pulse (SSP), a source shift clock (SSC), a source output enable (SOC), a polarity signal (POL), and the like are included.

The gate driver 120 and the data driver 130 are separated into a plurality of integrated circuits (ICs) and manufactured as the gate driver 121 and the source driver 131 in a chip form.

Each driver 121 and 131 is connected to the liquid crystal panel 110 in a structure that is mounted in an integrated circuit region opened on a tape carrier package (TCP) 122 and 132. In addition, a chip on film (COF) structure which is mounted on the base film of the tape carrier package and electrically connected to the liquid crystal panel by a tape automated bonding (TAB) method, and a chip mounted directly on the liquid crystal panel A chip on glass (COG) structure may be used.

The gate driver 120 generates scan pulses that sequentially drive the gate lines GL1 to GLm of the liquid crystal panel 100 in response to the gate control signal transmitted from the timing controller 141.

The data driver 130 supplies data voltages of one line for each horizontal period to the data lines DL1 to DLn of the liquid crystal panel 110 in response to the data control signal. At this time, the data driver 130 receives the pixel data R, G, and B from the timing controller 141, selects a gamma voltage corresponding thereto, and uses the selected gamma voltage to select the pixel data R, G, and B. Is converted into a data voltage and supplied to the data lines DL1 through DLn.

In more detail, the data driver 130 shifts the source start pulse SSP according to the source shift clock SSC to generate a sampling signal. Subsequently, the data driver 130 sequentially inputs and latches the pixel data R, G, and B in predetermined units in response to the sampling signal. The latched pixel data R, G, and B for one line are converted into a data voltage, which is an analog signal, and supplied to the data lines DL1 through DLn in an enable period of the source output signal SOE. In this case, the data driver 130 converts the data voltage into a positive polarity or a negative polarity in response to the polarity signal POL.

The gate driver 120 generates a scan pulse consisting of the gate low voltage VGH and the gate high voltage VGL in response to the gate control signal GCS from the timing controller 141, and scan scan direction D1. Accordingly, scan pulses are sequentially supplied to the gate lines GL1 to GLm. As the scan pulse is supplied, the thin film transistors TFT connected to the gate lines GL1 to GLm are sequentially driven.

The power supply unit 143 receives power from an external system SYS to generate various levels of driving voltages such as a gate high voltage VGH, a gate low voltage VGL, a common voltage Vcom, and a constant voltage VDD. Apply the required voltage to each part.

The gamma voltage generator 142 receives a voltage branched from the power supply unit 143, generates gamma voltages (reference voltages) necessary for digital / analog conversion of the data driver 130, and supplies them to the data driver 130.

The timing controller 141, the power supply 143, the gamma voltage generator 142, and the like are mounted on the printed circuit board 140 connected to the data driver 130, or connected to the main printed circuit board. It is configured on the phase.

Here, as shown in FIG. 2, when the data driver 130 and the printed circuit board 140 are positioned below the liquid crystal panel 110, that is, at the end of the desired scan direction D1, scan progresses as in the prior art. The first signal line group 150 of the line-on-glass type and the second signal line group 123 on the tape carrier package 122 in the data driver 120 are disposed for the purpose of directing the direction D1 from the upper side to the lower side. It is arranged separately to set the output of the gate control signal from the gate line GL1 at the top of the screen.

The first signal line group 150 and the second signal line group 123 connected to the first signal line group 150 have an upper side of the liquid crystal panel 110, that is, a start end of the scan advance direction D1. Since the gate control signal is directly transmitted to the uppermost gate driver 121, the same scan progress direction D1 is set as in the prior art without adding a frame memory, thereby realizing a normal screen.

FIG. 3 is a waveform diagram illustrating a process of generating a scan pulse in the gate driver of FIG. 1, and FIG. 4 is a waveform diagram illustrating a gate start pulse generated during one frame period. The operation of the gate driver 120 is described in more detail. It is shown.

As shown in FIG. 4, one gate start pulse GSP is supplied to one frame (screen), and scan pulses are sequentially supplied to the gate lines GL1 to GLm by the supplied gate start pulse GSP.

More specifically, a gate start pulse GSP and a gate shift clock GSC having a period of one horizontal period 1H are supplied from the timing controller unit 141.

The gate shift clock GSC moves the gate start pulse GSP from the embedded first shift resist to the i th shift resist every one period. Here, whenever a gate start pulse GSP is moved to an adjacent shift register, that is, every one horizontal period 1H, a shift pulse is generated from the shift register.

When the gate output enable GOE is supplied from the timing controller 141, the gate output enable GOE is supplied every 1 horizontal period 1H in the high section of the gate output enable GOE (a low section in the case of the inverter). A scan pulse corresponding to the shift pulse is generated, and a scan pulse is supplied according to the scan progress direction D1 to be sequentially driven from the first gate line GL1.

As such, when scan pulses are sequentially supplied to the gate lines GL1 to GLm and data voltages are supplied to the data lines DL1 to DLn, a constant image corresponding to the data voltages is displayed on the liquid crystal panel 110. .

5 is a flowchart illustrating a method of driving a liquid crystal display according to an exemplary embodiment of the present invention.

First, in step S100, the timing controller 141 located at the end of the scan progress direction D1 outputs a gate control signal and a data control signal to control the driving timing.

Next, in step S110, the second signal line group 123 formed on the data driver 120 to connect the first signal line group 150 of the line on glass type and the first signal line group 150 to each other. The gate control signal is directly transmitted from the data driver 130 connected to the timing controller unit 141 to the start end of the scan progress direction D1 via the control unit.

Next, in step S120, the gate driver 120 sequentially supplies scan pulses to the gate lines GL1 to GLm of the liquid crystal panel 110 in the scan progress direction D1 according to the gate control signal.

Here, the gate control signal includes a gate start pulse (GSP), a gate shift clock (GSC), a gate output enable (GOE), and the like. Can be broken down.

First, the timing controller 141 supplies the gate start pulse GSP and the gate shift clock GSC to the gate driver 120, and the gate driver 120 supplies the gate start pulse G according to the gate shift clock GSC. GSP) is shifted to generate shift pulses every one horizontal period (1H).

The gate output enable GOE is supplied to the gate driver 120, and the gate driver 120 generates a scan pulse so as to correspond to the shift pulse in the high section or the low section of the gate output enable GOE.

Thereafter, the scan driver is sequentially supplied to the gate lines GL1 to GLm in the scan driving direction D1.

The timing controller 141 is positioned below the liquid crystal panel 110 adjacent to the data driver 130, that is, at the end of the scan advancing direction D1, but the first signal line group 150 and the second signal. The scan pulse is applied by the line group 123 from the upper side of the liquid crystal panel 110 which is the start end of the scan progress direction D1.

As described above, since the normal screen is driven from the first gate line GL1 to the last gate line GLm along the scan progress direction D1, the data driver 130 is positioned at the end of the scan progress direction D1. Even in this case, the scan progress direction D1 can be appropriately set without applying a separate frame memory.

Next, in step S130, the data driver 130 positioned adjacent to the timing controller 141 supplies the data voltages to the data lines DL1 to DLn of the liquid crystal panel 110 according to the data control signal.

Next, in step S140, the liquid crystal panel 110 performs an image according to scan pulses supplied through the gate lines GL1 to GLm and data voltages supplied to the data lines DL1 to DLn in response to the scan pulses. Will be displayed.

Although embodiments of the present invention have been described above with reference to the accompanying drawings, those skilled in the art to which the present invention pertains may implement the present invention in other specific forms without changing the technical spirit or essential features thereof. I can understand that.

Therefore, since the embodiments described above are provided to completely inform the scope of the invention to those skilled in the art, it should be understood that they are exemplary in all respects and not limited. The invention is only defined by the scope of the claims.

According to the liquid crystal display device and the driving method thereof according to the preferred embodiment of the present invention made as described above, when the data driver is located on the lower side of the liquid crystal panel, the configuration is optimized on the upper side of the liquid crystal panel without using a frame memory. The normal screen can be driven efficiently to the lower side.

Claims (6)

A liquid crystal panel composed of pixels divided into gate lines and data lines crossing each other, and having a thin film transistor disposed on a pixel basis; A gate driver sequentially supplying scan pulses to the gate lines of the liquid crystal panel in a scan progress direction; A data driver positioned at an end of the scan progress direction and supplying a data voltage to the data lines of the liquid crystal panel; A timing controller unit positioned adjacent to the data driver and outputting a gate control signal and a data control signal to control driving timing of the gate driver and the data driver; A first signal line group of a line on glass type configured to directly transmit the gate control signal from the data driver to a start end of the scan progress direction; And And a second signal line group formed on the data driver to be connected to the first signal line group and connecting the first signal line group to each other. The method of claim 1, The gate driver includes a plurality of gate drivers, And the first and second signal line groups are configured to receive the gate control signal and transmit the gate control signal to a top gate driver positioned at a start end of the scan direction. The method of claim 1, The gate control signal, And a gate start pulse (GSP), a gate shift clock (GSC), and a gate output enable (GOE). Outputting a gate control signal and a data control signal to control a driving timing by a timing controller located at an end in a scan progress direction; The gate control signal is transmitted from the data driver connected to the timing controller to the start end of the scan direction through a first signal line group of a line on glass type and a second signal line group formed on the data driver. step; A gate driver sequentially supplying scan pulses to gate lines of a liquid crystal panel in a scan progress direction according to the gate control signal; Supplying a data voltage to data lines of the liquid crystal panel according to the data control signal, wherein the data driver is disposed adjacent to the timing controller; And And displaying an image according to the scan pulse supplied through the gate lines and the data voltage supplied to the data lines in response to the scan pulse. . The method of claim 4, wherein The gate control signal, And a gate start clock (GSP), a gate shift clock (GSC), and a gate output enable (GOE). The method of claim 5, Supplying the scan pulse, Supplying a gate start pulse and a gate shift clock; Shifting the gate start pulse according to the gate shift clock to generate a shift pulse every one horizontal period; Supplying a gate output enable and generating the scan pulse to correspond to the shift pulse in a high or low period of the gate output enable; And And sequentially supplying the scan pulses to the gate lines according to the scan progress direction.

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