KR20070095563A - Semiconductor memory device - Google Patents

Abstract

A semiconductor memory device is provided to perform an access operation normally with a redundancy cell instead of a damaged cell when a last column address as to a specific word line is detected in a no wrap mode, when the cell corresponding to the last column address as to the specific word line or a partial column address around the specific word line is damaged and is replaced with the redundancy cell. A first counter(100) generates an internal column address by inputting and counting an external column address. A detection part(200) receives the internal column address, and outputs a word line reset signal to change a first word line into a second word line by detecting whether the internal column address coincides with a specific column address. A second counter(300) receives the word line reset signal from the detection part, and generates a cell block address in response to the word line reset signal. A fuse box(400) receives the internal column address and a cell block address, and outputs a redundancy column address in order to correspond to the assembly of the internal column address and the cell block address.

Description

Semiconductor Memory Device

1 is a timing diagram for describing an operation of a conventional semiconductor memory device.

2 illustrates a configuration of a semiconductor memory device according to an embodiment of the present invention.

3 illustrates a configuration of a detector included in the semiconductor memory device according to the present embodiment.

4 is a block diagram of a signal generation unit included in a detection unit of a semiconductor memory device according to an exemplary embodiment.

5 shows a configuration of a signal generator for generating a control clock used in the signal generator.

6 illustrates a configuration of a pulse generator included in the detection unit of the semiconductor memory device according to the present embodiment.

7 illustrates a configuration of the shift register included in the detection unit of the semiconductor memory device according to the present embodiment.

8 is a timing diagram for describing an operation of the semiconductor memory device according to the present embodiment.

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device. More particularly, in a semiconductor memory device such as pseudo-sRAM, a cell corresponding to the last column address or a part of a column address near a specific word line is damaged. When replaced with a redundancy cell, the present invention relates to a semiconductor memory device capable of normally accessing a redundant cell instead of the damaged cell when the last column address for the specific word line is detected in a no wrap mode.

Among semiconductor memory devices, random access memory (RAM) is a memory capable of random access to a storage location and performing both writing and reading of information, and is widely used in storage devices of computers and peripheral terminals. Advantages include low cost, small size, low power consumption, high speed calling, and non-destructive decryption. The downside is that all stored data is erased when the power is turned off. Kinds of information are dynamic RAM which does not need to be refreshed at regular intervals while the power is connected, and static RAM which does not erase information when only power is connected.

While SRAM has the advantage of connecting to other integrated circuits, the same memory capacity as dynamic RAM requires three to four times more devices, which makes the circuit complex and expensive. Therefore, in recent years, researches on so-called pseudo SRAMs that implement an SRAM-like operation using a cell of a dynamic ram have been actively conducted. Pseudo SRAM has the advantage of enabling high integration such as 16Mbit, 32Mbit, 64Mbit while reducing the chip size (chip size) compared to the existing SRAM. However, since the cell has the same configuration as the cell of the dynamic ram, there is a burden to perform the refresh operation internally.

Pseudo SRAM has an operation mode called a no wrap mode, which is performed by internally increasing each word line one by one for each word line. That is, in pseudo-SRAM, when the last column address is detected for each word line in the normal mode, the word line is internally increased. Accordingly, the cell block address, which is the address of the cell block in each bank, also increases. However, in the conventional semiconductor memory device, when a cell corresponding to the last column address or a part of a column address of a specific word line is damaged and replaced with a redundancy cell, there is a problem in that the redundancy cell cannot be normally accessed in the normal mode. . This will be described in more detail with reference to FIG. 1.

 In Fig. 1, / adv is a signal that allows the controller to accept an external address and predetermined control signals to perform a read or write operation on a new word line, and / CS is a chip select signal. Yi (n) is a delay internal column address delayed by a predetermined interval internally, Yi255_det is a signal for detecting the last column address for the corresponding word line, and CAX <A> and CAX <B> are cell blocks in each bank. Is the cell block address that is the address of. WL (n) is a signal enabled when the nth word line is activated and WL (n + 1) is a signal enabled when the n + 1th word line is activated.

As shown in FIG. 1, when the last column address for each word line is detected in the wrap mode and the detection signal Yi255_det is enabled, the cell block addresses CAX <A> and CAX <B> are increased. At this time, the delay internal column addresses Yi 252 to Yi 255 are still in a state before being activated.

In this case, if the cell corresponding to the last column address Yi255 for the word line WL (n) is damaged and replaced with a redundancy cell, the fuse box is a cell block address CAX <A>, CAX in the semiconductor memory device. In response to <B>), a redundancy column address corresponding to the corresponding redundancy cell is output. However, in the conventional semiconductor memory device, the cell block addresses CAX <A> and CAX <B> are level-shifted in response to the enable of the detection signal Yi255_det as shown in FIG. The current word line WL (n) is active and the next word line WL (n + 1) is not yet active.

However, in the fuse box, when the cell block addresses CAX <A> and CAX <B> are leveled as described above, the word line increases from the word line WL (n) to the word line WL (n + 1). You will be mistaken for it. Accordingly, the fuse box does not normally output the redundancy column address for the redundancy cell replacing the damaged cell WL (n) × Yi255, and the wrong redundancy column address corresponding to the word line WL (n + 1). There was a problem outputting.

As a result, in the conventional semiconductor memory device, when the cell corresponding to the last column address Yi255 for the word line WL (n) is damaged and replaced with the redundancy cell, the last for the word line WL (n) in the overlapping mode. When a column address is detected, there is a problem in that a redundant cell that replaces the damaged cell cannot be normally accessed. This problem also occurred when the last column address (Yi255) as well as the adjacent column addresses Yi252 to Yi254 were damaged.

Accordingly, a technical problem to be solved by the present invention is that in a semiconductor memory device such as pseudo RAM (PSRAM), a cell corresponding to a last column address or a part of a column address near a specific word line is damaged and replaced with a redundancy cell. In this case, the present invention provides a semiconductor memory device capable of normally accessing the redundancy cell instead of the damaged cell when the last column address for the specific word line is detected in the normal mode.

In order to achieve the above technical problem, the present invention includes a first counter for receiving an external column address and counting it to generate an internal column address; A detector configured to receive the internal column address, detect whether the internal column address matches a specific column address, and output a word line reset signal for changing a current first word line into a second word line; A second counter receiving a word line reset signal from the detector and generating a cell block address in response to the word line reset signal; Provided is a semiconductor memory device including a fuse box for receiving the internal column address and the cell block address, and outputs a redundancy column address preset to correspond to the combination of the internal column address and the cell block address.

In the present invention, the specific column address is preferably the last column address of the first word line.

In the present invention, it is preferable that the detector outputs the word line reset signal after a predetermined period has elapsed corresponding to a preset clock latency value.

The detection unit may include: a first pulse generator configured to generate a first pulse signal having a predetermined enable period in response to a first control signal enabled for a predetermined period when a word line is changed; A pull-up unit configured to pull-up a first node in response to the first pulse signal; A detector for detecting whether the internal column address matches the specific column address and outputting a detection signal; A second pulse generator configured to generate a second pulse signal having a predetermined enable interval in response to the detection signal; A pull-down unit configured to pull down the first node in response to the second pulse signal; A first logic unit performing a logic operation on a signal buffering the first control signal and an output signal of the first node; And a signal generation unit configured to receive an output signal of the first logic unit and to be controlled by a plurality of latency signals according to the clock latency value to generate the word line reset signal.

The signal generator may include: a first delay unit configured to delay an output signal of the first logic unit by a first interval in response to the plurality of latency signals and output the delayed signal to a second node; A second delay unit which delays a signal of the second node by a second interval; A first transfer gate configured to transfer a signal of the second node to a third node in response to a first clock enabled during a read operation; A second transfer gate configured to transfer an output signal of the second delay unit to the third node in response to a second clock enabled during a write operation; It is preferably configured to include a third pulse generator for generating a third pulse signal having a predetermined enable interval in response to the signal of the third node.

In an embodiment, the first delay unit may include: a first shift register configured to receive an output signal of the first logic unit and move it by a predetermined clock period; A second shift register which receives an output signal of the first shift register and shifts the output signal by a predetermined clock period; A third transfer gate configured to transfer an output signal of the first sheath register to the second node in response to a first latency signal of the plurality of latency signals; And a fourth transfer gate configured to transfer an output signal of the second sheath register to the second node in response to a second latency signal among the plurality of latency signals.

In the present invention, the second delay unit preferably includes at least one shift register for receiving a signal of the second node and moving it by a predetermined clock period.

In the present invention, it is preferable that the detection unit performs an AND operation on each signal constituting the internal column address, and outputs the result as the detection signal.

In the present invention, each of the first pulse generator and the second pulse generator includes a delay unit for delaying the input signal by a predetermined interval; And a second logic unit configured to logically operate the input signal and the output signal of the delayer and output a result thereof.

In the present invention, the retarder is preferably an inverting retarder.

In the present invention, it is preferable that the second logic unit performs a negative AND operation.

In the present invention, it is preferable that the first logic unit performs a negative logic operation.

Hereinafter, the present invention will be described in more detail with reference to Examples. These examples are only for illustrating the present invention, and the scope of protection of the present invention is not limited by these examples.

2 illustrates a configuration of a semiconductor memory device according to an embodiment of the present invention. Referring to the configuration of the semiconductor memory device according to the present embodiment, the configuration is as follows.

As shown in FIG. 2, the semiconductor memory device according to the present embodiment receives an external column address Y_add <0: 7> and counts it to generate an internal column address CAY <0: 7>. 1 counter 100; The internal column address (CAY <0: 7>) is input to detect whether the internal column address (CAY <0: 7>) matches a specific column address, thereby wording the current word line (WL (n)). A detector 200 for outputting a word line reset signal reset_wl for changing to the line WL (n + 1); A second counter 300 that receives a word line reset signal reset_wl from the detector 200 and generates a cell block address CAX <A, B> in response to the word line reset signal reset_wl; The internal column address (CAY <0: 7>) and the cell block address (CAX <A, B>) are input, and the internal column address (CAY <0: 7>) and the cell block address (CAX <A, B>) are received. ) Is configured to include a fuse box 400 for outputting a redundancy column address red_Yi which is preset.

The operation of this embodiment configured as described above will be described in detail with reference to FIGS. 2 to 8.

First, as illustrated in FIG. 2, the first counter 100 receives an external column address Y_add <0: 7> and counts it, thereby counting the internal column address CAY <0: 7>. ) Here, the first counter 100 is the same as the address counter used in the conventional semiconductor memory device in the basic configuration.

Subsequently, the detection unit 200 receives an internal column address CAY <0: 7> and detects whether the internal column address CAY <0: 7> matches a specific column address, particularly the last column address. If the detection result coincides with the last column address, a word line reset signal reset_wl for outputting the current word line WL (n) to the word line WL (n + 1) is output. Will be described with reference to FIGS. 3 to 7.

3 illustrates a configuration of the detector 200 according to the present embodiment, and FIG. 4 illustrates a configuration of the signal generator 210 included in the detector 200. First, in the initial operation of the semiconductor memory device, the power-up signal pwrup becomes low level and its inversion signal pwrupb becomes high level, so that node A1 is initialized to high level and node A2 is initialized to low level. do. In addition, since the node C is also initialized to a low level in FIG. 4, the reset signal reset_wl is in a low level state.

Subsequently, as shown in FIG. 8, the control unit causes the control unit to perform an external address and predetermined control to perform a read or write operation on a control signal that is enabled for a predetermined period when the word line is changed, that is, a new word line WL (n). When the control signal / adv, which is a signal that allows the reception of the signals, is enabled at the low level, the inversion signal adv is enabled from the low level to the high level. Accordingly, the pulse generator 201 outputs a pulse signal that transitions to a low level for a predetermined period. That is, as shown in FIG. 6, the pulse generator 201 outputs a high level signal out when a low level signal in is first input. Subsequently, when the input signal in transitions to the high level, the delay unit 250 as the inversion delay means continuously outputs the high level signal, which is the previous level, during the predetermined delay period, so that the output signal out becomes the low level. . In addition, when the delay period elapses, the output of the delay unit 250 transitions to a low level, so the output signal out transitions back to a high level. As a result, the pulse generator 201 outputs a pulse signal that transitions to a low level for a predetermined period as the control signal adv transitions to a high level.

Next, the PMOS P11 pulls up the node A1 in response to the low level signal from the pulse generator 201. The transfer gate TG11 transfers a low level signal applied from the inverter IV19 to the node A2 in synchronization with the clocks clk and clkb, and the NOR gate NR12 is output from the inverter IV20. The low level signal is output in response to the high level signal. Therefore, a low level signal is input to the input terminal in of the signal generator 210.

Since the delay unit 220 receives the low level signal from the signal generator 210 of FIG. 4, the signal output from the shift registers 211 to 215 and the transfer gates TG31 to TG35 becomes low level and is a node. (B) is also at a low level. The pulse generator 219 receives a low level signal from the inverter IV38. Here, the pulse generator 219 is identical to the pulse generator 201 in its configuration and operation. Therefore, since the pulse generator 219 receives the low level signal and outputs the high level signal, the word line reset signal reset_wl is in the low level state. As a result, as shown in FIG. 8, when the control signal / adv transitions to a low level, the word line reset signal reset_wl is in a low level state.

Thereafter, the output signal of the sensing unit 202 becomes low level and the pulse generator 203 outputs a high level signal until the internal column address CAY <0: 7> is inputted from 0 to 254. N11 is still in the turned off state. Thus, node A1 continues to maintain the previous high level by the latch operation by inverter IV16 and inverter IV17.

However, when the last internal column address for the word line WL (n), that is, the internal column addresses CAY <0: 7> are all input at the high level, the NAND gates ND11 to 13 all receive the low level signal. The NOR gate NR11 receives three low level signals and outputs a high level signal. That is, the detector 202 detects the last internal column address for the word line WL (n) and outputs a high level detection signal. In response to the high level signal, the pulse generator 203 outputs a pulse signal having a low level for a predetermined period (hereinafter referred to as a "low level pulse signal"), and the inverter IV15 inverts it and outputs it. do. Accordingly, the NMOS N11 is turned on in response to the high level pulse signal output from the inverter IV15 to pull down the node A1. Here, the configuration and operation of the pulse generator 203 is the same as the pulse generator 201.

The transfer gate TG11 transfers to the node A2 a pulse signal (hereinafter referred to as a "high level pulse signal") that is a high level for a predetermined period applied from the inverter IV19 in synchronization with the clocks clk and clkb. The NOR gate NR12 performs a negative logic sum operation on the low-level pulse signal and the control signal adv_d output from the inverter IV20 and outputs the result. At this time, the control signal adv_d is a signal buffered by the inverter IV11 and the inverter IV12 and is in a low level state. Therefore, the NOR gate NR12 outputs a high level pulse signal by performing a negative logic sum operation on the low level pulse signal and the low level control signal adv_d. Therefore, a high level pulse signal is input to the input terminal in of the signal generator 210.

The signal generator 210 of FIG. 4 outputs a word line reset signal reset_wl by delaying or shifting the high-level pulse signal by a predetermined interval according to a preset clock latency value, which is specifically described with reference to FIG. 4. Explain. In this case, the clock latency refers to how many times the first read data comes out after the control signal / adv is enabled.

As shown in FIG. 4, the shift registers 211 to 215 included in the delay unit 220 are connected in series. The shift registers 211 to 215 are configured as shown in FIG. 7 and output the delayed or shifted input signal in by one clock cycle. That is, in FIG. 7, the transfer gate TG61 receives the input signal in synchronization with the rising edge of the clock clk, and the latch means composed of the inverter IV61 and the inverter IV62 inverts and outputs the same. Latch The NOR gate NR61 performs a negative logic sum operation on the signal from the inverter IV61 and the control signal adv_d, and outputs the result. The control signal adv_d is low level at this time, as described above, The output of the gate NR61 becomes equal to the phase of the node D1. Then, at the falling edge of the clock clk, the transfer gate TG62 transfers the output of the NOR gate NR61 to the node D2. As a result, the shift registers 211 to 215 move the input signal in by one clock cycle and output it as an output signal out.

Transfer gates TG31 to TG35 are connected to the output terminals of the shift registers 211 to 215 to transfer the output signals of the shift registers to the node B. The transfer gates TG31 to TG35 are controlled by the plurality of latency signals bcm_lc2 to lc6 according to clock latency values. Here, the latency signals bcm_lc2 to lc6 are enabled at a high level according to a clock latency value preset as a mode register set (MRS) value during initial operation of the system. The signal is transmitted to the node B through a transfer gate that is turned on in response to one latency signal.

For example, when the clock latency is 2, only the latency signal bcm_lc2 is enabled at a high level, and the remaining latency signals bcm_lc3 to lc6 are all disabled at a low level, so only the transfer gate TG31 is turned on and the remaining transfer gate TG32-35 are all turned off. Therefore, in this case, the high-level pulse signal input to the input terminal in of the signal generator 210 is delayed or shifted by one clock period by the shift register 211 and then transferred to the node B. In addition, for example, when the clock latency is 6, only the latency signal bcm_lc6 is enabled at a high level, and all the remaining latency signals bcm_lc2 to lc5 are disabled at a low level, so that only the transfer gate TG35 is turned on and the remaining transfer gate is turned on. (TG31 ~ 34) are all turned off. Therefore, in this case, the high level pulse signal inputted to the input terminal (in) of the signal generator 210 is delayed or shifted by 5 clock cycles by the shift register 211 to the shift register 215, and then the node ( Delivered to B).

Subsequently, the pulse signal transmitted to the node B is transmitted to the node C through another path depending on whether the current operation mode is read or write. That is, when the current operation mode is a read, the control signal web4 becomes high level and the control clock clk_r is enabled high level in FIG. 5, so that the pulse signal of the node B is transmitted through the transfer gate TG37. Is passed to node C. On the other hand, when the current operation mode is light, since the control signal web4 becomes low level and the control clock clk_w is enabled high level, the pulse signal of the node B is delayed by the shift registers 216 to 217. After delayed or shifted by the unit 230 by two clock cycles, the signal is transferred to the node C through the transfer gate TG36. The shift registers 216 to 217 constituting the delay unit 230 are as shown in FIG. 7, and the clock clk_ctr in FIG. 5 is a signal buffered by the clock clk.

Subsequently, since the pulse generator 219 generates a pulse signal that transitions to a low level in a predetermined section in response to a high level pulse signal, the word line reset signal reset_wl is input to the high level in a predetermined section as shown in FIG. 8. It becomes a pulse signal to be enabled.

As described above, when the operation of the detection unit 200 is summarized, the detection unit 200 receives the internal column address CAY <0: 7>, and the internal column address CAY <0: 7> has a specific column address, particularly, the last. Detects whether or not the column address is the same as the 255th column, and when the detection result coincides with the last column address, a word for changing the current word line WL (n) to the word line WL (n + 1). Output the line reset signal reset_wl. In particular, the detector 200 controls the delay element elements in the detector 200 in outputting the word line reset signal reset_wl, and the shift registers 211 to 217 included in the signal generator 210 and the transfer unit. By appropriately controlling the operations of the gates TG31 to TG35, the word line reset signal reset_wl is enabled after the operation on the word line WL (n) is completed as shown in FIG. Therefore, according to the present embodiment, even when the last column address for the corresponding word line is detected in the normal mode and the detection signal yi255_det is enabled in the detection unit 200 of FIG. 3, the word line reset signal reset_wl is derived therefrom. It is enabled after a predetermined interval has elapsed and an operation on the corresponding word line WL (n) is completed.

Next, in FIG. 2, the second counter 300 receives the word line reset signal reset_wl from the detector 200 and responds to the word line reset signal reset_wl in response to the cell block address CAX <A, B. Output>) That is, as shown in FIG. 8, the second counter 300 performs a counting operation in response to the word line reset signal reset_wl to output the cell block addresses CAX <A and B>. Accordingly, unlike the conventional case in which the cell block addresses CAX <A, B> are level shifted in response to the detection signal yi255_det, in the present embodiment, the cell block addresses CAX <A, B are shown in FIG. > Is level-shifted in response to the word line reset signal reset_wl.

Meanwhile, the second counter 300 also outputs the internal row address CAX <0:13> by counting the external row address X_add <0:13>. The second counter 300 may be configured using a general address counter used in a semiconductor memory device.

Finally, the fuse box 400 receives the internal column address CAY <0: 7> and the cell block address CAX <A, B>, and the internal column address CAY <0: 7> and the cell. The redundancy column address red_Yi preset to correspond to the combination of the block addresses CAX <A, B> is output. That is, in the present embodiment, as described above, the word line reset signal reset_wl is enabled after the operation on the corresponding word line WL (n) is completed, and the cell block addresses CAX <A, B> are The level is shifted in response to the word line reset signal reset_wl. In other words, since the cell block addresses CAX <A> and CAX <B> do not level-shift before the word line reset signal reset_wl is enabled, the fuse box replaces the current word line with the word line. There is no malfunction that is incorrectly recognized as word line WL (n + 1) instead of WL (n). Therefore, even when the cell corresponding to the last column address Yi255 for the word line WL (n) is damaged and replaced with a redundancy cell, in the present embodiment, the fuse box 400 replaces the damaged cell in a no-lap mode. The normal redundancy column address red_Yi may be output to be accessed by the redundancy cell preset to do so. The same may be applied to cases in which not only the last column address Yi255 but also the adjacent column addresses Yi252 to Yi254 are damaged.

As a result, according to the present embodiment, when the cell corresponding to the last column address for a specific word line or some column address in the vicinity thereof is damaged and replaced with a redundancy cell, the last column address for the specific word line is detected in the Norlap mode. Can be accessed normally by a redundancy cell instead of the damaged cell.

As described above, in the semiconductor memory device according to the present invention, when a cell corresponding to the last column address of a specific word line or some column address in the vicinity thereof is damaged and replaced with a redundancy cell, the semiconductor memory device according to the present invention may be used for the specific word line. When the last column address is detected, it allows normal access to the redundancy cell instead of the damaged cell.

Claims (14)

A first counter that receives an external column address and counts the external column address to generate an internal column address; A detector configured to receive the internal column address, detect whether the internal column address matches a specific column address, and output a word line reset signal for changing a current first word line into a second word line; A second counter receiving a word line reset signal from the detector and generating a cell block address in response to the word line reset signal; And a fuse box configured to receive the internal column address and the cell block address and output a redundancy column address preset to correspond to the combination of the internal column address and the cell block address. The method of claim 1, And the specific column address is a last column address of the first word line. The method of claim 1, And the detector outputs the word line reset signal after a predetermined period has elapsed in response to a preset clock latency value. The method of claim 3, wherein The detection unit A first pulse generator configured to generate a first pulse signal having a predetermined enable period in response to the first control signal enabled for the predetermined period when the word line is changed; A pull-up unit configured to pull-up a first node in response to the first pulse signal; A detector for detecting whether the internal column address matches the specific column address and outputting a detection signal; A second pulse generator configured to generate a second pulse signal having a predetermined enable interval in response to the detection signal; A pull-down unit configured to pull down the first node in response to the second pulse signal; A first logic unit performing a logic operation on a signal buffering the first control signal and an output signal of the first node; And a signal generator configured to receive an output signal of the first logic unit and to be controlled by a plurality of latency signals according to the clock latency value to generate the word line reset signal. The method of claim 4, wherein The signal generation unit A first delay unit delaying an output signal of the first logic unit by a first interval in response to the plurality of latency signals and outputting the delayed signal to a second node; A second delay unit which delays a signal of the second node by a second interval; A first transfer gate configured to transfer a signal of the second node to a third node in response to a first clock enabled during a read operation; A second transfer gate configured to transfer an output signal of the second delay unit to the third node in response to a second clock enabled during a write operation; And a third pulse generator configured to generate a third pulse signal having a predetermined enable interval in response to the signal of the third node. The method of claim 5, The first delay unit A first shift register which receives an output signal of the first logic unit and shifts the output signal by a predetermined clock period; A second shift register which receives an output signal of the first shift register and shifts the output signal by a predetermined clock period; A third transfer gate configured to transfer an output signal of the first sheath register to the second node in response to a first latency signal of the plurality of latency signals; And a fourth transfer gate configured to transfer an output signal of the second sheath register to the second node in response to a second latency signal of the plurality of latency signals. The method of claim 5, The second delay unit And at least one shift register configured to receive a signal of the second node and move the signal of the second node by a predetermined clock period. The method of claim 5, The third pulse generator is A delay unit for delaying the input signal by a predetermined interval; And a second logic unit configured to logically operate the input signal and the output signal of the delayer and output a result thereof. The method of claim 8, The delay unit is an inversion delay unit, and the second logic unit performs a negative AND operation. The method of claim 4, wherein And the sensing unit performs an AND operation on each signal constituting the internal column address, and outputs the result as the detection signal. The method of claim 4, wherein Each of the first pulse generator and the second pulse generator A delay unit for delaying the input signal by a predetermined interval; And a second logic unit configured to logically operate the input signal and the output signal of the delayer and output a result thereof. The method of claim 11, And the retarder is an inverted retarder. The method of claim 11, And the second logic unit performs a negative AND operation. The method of claim 4, wherein And the first logic unit performs a negative logic operation.

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