KR20070094766A - Adaptive digital voltage regulator - Google Patents

Abstract

A digitally-controlled, DC/DC converter includes at least one switched-mode power stage for the purpose of converting an input voltage (Vin) into an output voltage (Vout); the power stage including at least one controllable switching device, which is turned ON and OFF by a control device with temporal resolution t. The converter further includes a duty cycle control mechanism for controlling the duty cycle of the controllable switching device, the duty cycle control mechanism including a mechanism for estimating the output voltage error; a mechanism for estimating the target duty cycle; a duty cycle quantization mechanism for determining, for a target duty cycle estimate, a first set of quantized ON time/OFF time pairs suitable for controlling the switching device; and a selector mechanism for determining the turn ON and turn OFF times of said controllable switching device by choosing, cycle by cycle, an ON time/OFF time pair from a second set of quantized ON time/OFF time pairs, derived from said first set, choosing in such a manner that the amplitude of the output voltage error is continually minimized. To compensate for the load-dependent effects of parasitics the second set of quantized ON time/OFF time pairs is adjusted continuously, to insure optimum performance at all load levels.

Description

Adaptive Digital Voltage Regulators {ADAPTIVE DIGITAL VOLTAGE REGULATOR}

TECHNICAL FIELD The present invention relates to the field of power conversion, and more particularly, to a digitally controlled switch mode DC / DC converter.

There are various kinds of switch mode DC / DC power converters whose properties are determined by the average duty cycle of the controllable switching device in the converter's power conversion stage. Examples include buck, boost, inverting buck-boost, forward, and flyback converters operating in continuous conduction mode (CCM). to be. If the load of the power converter changes dynamically, or needs to track the change in load with a minimum output voltage error, the regulation of these converters continues to predict the output voltage error (the output voltage error is the desired output voltage). This is achieved by continuously adjusting the duty cycle of the switching device to compensate for the apparent load change in the output voltage error estimate. In this case, the operation of regulation consists in controlling the duty cycle of the switching device on a cycle-by-cycle basis in accordance with an output voltage error estimate, so that the amplitude of the output voltage error is continuously minimized.

The regulation mechanism for this purpose, known as a pulse width modulation (PWM) regulator, generally includes a pulse width control mechanism and a duty cycle control mechanism, where the former generates an ON pulse suitable for realizing the duty cycle generated by the latter. do. As such, the duty cycle control mechanism includes a mechanism for predicting a target duty cycle (essential for obtaining the desired output voltage). The target duty cycle prediction mechanism is a normal feedback mechanism driven by the output voltage error, but may be a feedforward mechanism driven by the input voltage or by some combination of the two.

The most commonly used pulse width control mechanism is basically analog; In other words, a continuously varying analog signal representing the desired duty cycle is received as an input, and an output pulse having a continuously varying width is output. As in the previous analog field, continuous advances in integrated circuit technology have facilitated the application of digital technology to the field of power conversion. As a result, digital PWM regulation mechanisms have been developed to replace analog PWM regulators, and commercialization is underway. The quantization of the generated pulse width—the result of the temporal decomposition of the digital regulation mechanism—is an attribute of such mechanisms. If the temporal resolution of the regulation mechanism is Δt, the pulse width is limited to an integer multiple of Δt. In addition, the switching cycle over successive ON and OFF pulses is also limited to an integer multiple of Δt.

Power converters One challenge for those who want to apply digital PWM regulation mechanisms to DC / DC converters, especially for battery-powered mobile applications, is to achieve application performance acceptable as digital regulation mechanisms. Quantization of the pulse width is transformed into quantized duty cycles, which inhibits the ability of any duty cycle control mechanism to limit the output voltage ripple to any application-indicated level. To understand the nature of this challenge, consider a DC / DC converter in a battery-powered mobile application. The switching frequency is typically set around 1 MHz to maximize the operating efficiency of the converter and minimize the size and cost of discrete elements. Thus, a digital PWM regulation mechanism operating at 16 MHz will produce pulse widths of 0, 1/16 ㎲, 2/16 ㎲, 3/16 ㎲ .... 16/16 ㎲. Assuming a fixed switching frequency, 17 instantaneous duty cycles (including 0 and 1) may be applied. One way to regulate the output voltage is to cross between two quantized duty cycles, one smaller than the target duty cycle and the other larger. In one embodiment of this concept (see US Pat. No. 6,677,733), the duty cycle control mechanism examines the current output voltage error estimate and, if positive, selects a smaller duty cycle for the next cycle of the switching device. Likewise, if the current output voltage error estimate is negative, then select a larger duty cycle for the next cycle of the switching device. In the best case, however, this duty cycle control mechanism may not be able to limit the output voltage ripple to an acceptable level, in which case the only obvious reliance for the manufacturer of the regulator is to improve the temporal resolution of the regulation mechanism. . That is, to increase the clock frequency.

Even if the ripple is acceptable in static line and load conditions, the difficulty in providing accurate output voltage feedback with increased ripple (although acceptable) poses a challenge to strict regulation under dynamic load conditions. to provide. In this case, the only obvious solution for regulator manufacturers to minimize ripple without affecting dynamic performance is to increase the clock frequency.

However, increasing the clock frequency to mitigate the effects of quantization on output voltage errors (static and dynamic) will compromise the cost and efficiency metrics. For example, the complexity and resulting cost of digital regulation mechanisms is likely to increase in addition to power consumption. In addition, the increased cost and power consumption will be even more doubled if the need to increase the clock frequency prevents the digital regulation mechanism and integration (at the board level) with other electronic devices.

Clearly, there is a need for digital control methods that alleviate the need for higher clock frequencies for the purpose of obtaining only acceptable (static and dynamic) output voltages in various types of DC / DC converters.

Summary of the Invention

It is a primary object of the present invention to provide a digital control method that alleviates the need for higher clock frequencies for the purpose of obtaining only acceptable (static and dynamic) output voltages in various types of DC / DC converters.

To this end, a mechanism for predicting output voltage error; A mechanism for predicting a target duty cycle, a new duty cycle quantization mechanism for determining a first set of one or more quantized ON time / OFF time pairs regulating the output voltage, and two or more quantized derived from the first set A digital duty cycle control mechanism is disclosed that includes a new output-voltage-error-drive selector mechanism that determines the ON time and OFF time of the switching device by selecting cycle-by-cycle from a second set of ON time / OFF time pairs.

The novelty of the duty cycle quantization mechanism is that the output voltage ripple generated by a series of quantized switching cycles (sum of continuous ON time and OFF time) increases the number of quantized switching cycles available to generate the series of cycles. Decrease with increasing; And the available number is derived from the insight that it can be extended by mitigating the (previous) assumption that the length of every switching cycle in cycles under nominal load conditions is fixed. If, for example, the switching cycles are allowed to shrink / extend by the temporal decomposition of the digital regulation mechanism, there is a possibility that the number of available switching cycles increases by three times, significantly reducing the output voltage ripple.

The novelty of the selector mechanism comes from the insight that in a temporally quantized switching environment, the feedback mechanism controlling the switch is basically limited in the amount of useful information that can be provided in each cycling of the switch. For example, a digital regulation mechanism that implements conventional fixed-frequency pulse width modulation provides about four bits per cycle. Under these circumstances, even in steady state, when it is impossible to construct a pulse with the width necessary to precisely drive the output voltage error to zero, when the sign of the error changes, as can be seen in the prior art cited above It is important to be able to select an appropriate quantized pulse to drive the error back to zero. In other words, instantaneous output voltage error feedback must be available to operate effectively in a temporally quantized environment, even if its reliability is limited to 1 bit.

This insight may result in a duty cycle quantization mechanism that determines a first set of one or more quantized ON time / OFF time pairs for regulating an output voltage from a predicted target duty cycle, and two or more derived from the first set. In a new output-voltage-error-drive selector mechanism that selects, on a cycle-by-cycle basis, from the second set of quantized ON time / OFF time pairs, the feedback path when combined In addition to the delay in, the ripple induced by quantization is reduced. To illustrate the latter, the selection of ON time / OFF time pairs instead of the ON time can be divided into two choices: the ON time and the OFF time, and the feedback measured during the ON time and OFF time is the output voltage. Means that it can be applied virtually instantaneously to regulate it.

According to the present invention there is provided a method of converting an input voltage to an output voltage by a switch mode DC / DC converter; The input voltage is converted to an output voltage by a power stage comprising at least one controllable switch that is turned on / off by the control device and the control device is controlled by the temporal resolution Δt of the control device. Both the ON time and the OFF time are characterized by being limited to an integer multiple of Δt. At the heart of this approach is a duty cycle control mechanism that controls the duty cycle of the controllable switching device. The duty cycle control mechanism may include a mechanism for predicting an output voltage error; A mechanism for predicting a target duty cycle; Duty cycle quantization mechanism that determines a first set of quantized ON time / OFF time pairs suitable for the controllable switching device for a target duty cycle, wherein the controllable switching device is configured for each pair of quantization (of the first set). The ON time / OFF time is independently determined from each other, that is, the sum of the ON time and the OFF time is not fixed; Varies only by pair-to-pair set of discrete values {Tswi} (i = 1,2, ... I, where Tswi is an integer multiple of Δt); And selecting the ON time / OFF time pair in cycle units from the second set of quantized ON time / OFF time pairs derived from the first set to determine the ON / OFF time of the controllable switching device and It includes an output-voltage-error-drive selector mechanism that selects the amplitude to continue to be minimized.

According to the present invention, a switch-mode DC / DC converter is provided,

One or more power stages that convert the input voltage Vin into an output voltage Vout and each include one or more controllable switching devices;

A control device for turning on / off the controllable switching device; And

A duty cycle control mechanism for controlling the duty cycle of the controllable switching device,

The control device is limited by the temporal resolution (Δt) of the control device so that the ON time and the OFF time of the controllable switching device are limited to an integer multiple of Δt,

The duty cycle control mechanism,

A mechanism for predicting output voltage error;

A mechanism for predicting a target duty cycle;

Determine a first set of one or more quantized ON time / OFF time pairs suitable for controlling the controllable switching device for a target duty cycle estimate, and for each pair of quantized ON time / OFF times (of the first set) The sum of is defined by a set of discrete values {Tswi} [(i = 1,2, ... I), where I is a positive integer and Tswi is an integer multiple of Δt; And

Determine the ON time and the OFF time of the controllable switching device by selecting the ON time / OFF time pair on a cycle basis from a second set of two or more quantized ON time / OFF time pairs derived from the first set and An output-voltage-error-driven selector mechanism that selects such that the amplitude of the output voltage error continues to be minimized.

In a preferred embodiment, the selector mechanism selects the ON time / OFF time pair on a cycle basis from a set of two quantized ON time / OFF time pairs extracted from a (set) table indexed by the predicted target duty cycle. Determine an ON / OFF operation time; Select an ON time / OFF time with a lower displayed duty cycle when the output voltage error estimate is positive (that is, when the output voltage is higher than the desired output voltage) and have a higher displayed duty cycle when the output voltage error estimate is negative. Select a pair.

In a second preferred embodiment, the selector mechanism comprises an ON time from a set of three quantized ON time / OFF time pairs generated by a selector mechanism from a quantized ON time / OFF time pair generated by the duty cycle quantization mechanism. Determining the ON / OFF operation time by selecting a / OFF time pair on a cycle basis; Select an ON / OFF time pair with the lowest duty cycle marked as the lowest output voltage error estimate, and select the pair with the duty cycle marked as the highest when the output voltage error estimate is lowest, and the highest and lowest If not, select the remaining pair.

In a third embodiment, the selector mechanism is the ON time / OFF time from a set of six quantized ON time / OFF time pairs generated by the selector mechanism from the quantized ON time / OFF time pair generated by the duty cycle quantization mechanism. Determine ON / OFF operation time by selecting a pair on a cycle basis; Selects an ON / OFF time pair with the lowest duty cycle indicated when the output voltage error estimate is the highest, selects the pair with the duty cycle highest indicated when the output voltage error estimate is the lowest, and the output voltage error is the corresponding intermediate value. Select one of the remaining intermediate pairs

Those skilled in the art will appreciate that the digital duty cycle control mechanism of the present invention may be implemented in mixed signal circuits including logic circuits and / or microprocessors with appropriate software or firmware. In addition, those skilled in the art will appreciate that the digital duty cycle control mechanism of the present invention may be applied to DC / DC converter technology including, but not limited to, buck, boost, inverting buck-boost, forward, and flyback converters. I will understand.

The following figures and descriptions disclose other aspects and advantages of the present invention.

Various forms and features of the invention will be understood by reference to the following figures.

1 illustrates a prior art digital duty cycle control mechanism,

2 shows a digital duty cycle control mechanism according to the invention,

3 illustrates one embodiment of a digital duty cycle control mechanism in accordance with the present invention;

4 shows a second embodiment of a digital duty cycle control mechanism according to the invention,

5 shows a third embodiment of a digital duty cycle control mechanism according to the invention,

6 is a table of variable-frequency duty cycle pairs indexed by predicted target duty cycles.

There are various kinds of switch mode DC / DC power converters whose properties are determined by the average duty cycle of the controllable switching device in the power conversion stage of the converter. Examples are buck, boost, inverting buck-boost, forward, and flyback converters operating in continuous conduction mode (CCM). . If the load of the power converter changes dynamically, or needs to track the change in load with a minimum output voltage error, the regulation of these converters continues to predict the output voltage error (the output voltage error is the desired output voltage). This is achieved by continuously adjusting the duty cycle of the switching device to compensate for the apparent load change in the output voltage error estimate. In this case, the operation of regulation consists in controlling the duty cycle of the switching device on a cycle-by-cycle basis in accordance with an output voltage error estimate, so that the amplitude of the output voltage error is continuously minimized.

The regulation mechanism for this purpose, known as pulse width modulation (PWM), generally includes a pulse width control mechanism and a duty cycle control mechanism, where the former generates an ON pulse suitable for the realization of the duty cycle generated by the latter. . As such, the duty cycle control mechanism includes a mechanism for predicting a target duty cycle (which is the duty cycle necessary to obtain the desired output voltage). The target duty cycle prediction mechanism is a normal feedback mechanism driven by the output voltage error, but may be a feedforward mechanism driven by the input voltage, or any combination of the two.

The most commonly used pulse width control mechanism is basically analog; That is, it accepts a continuously varying analog signal representing the desired duty cycle as an input and outputs an output pulse having a continuously varying width. As in the previous analog field, continuous advances in integrated circuit technology have facilitated the application of digital technology to the field of power conversion. As a result, digital PWM regulation mechanisms have been developed to replace analog PWM regulators, and commercialization is underway. The resulting pulse width is quantized—the result of the temporal decomposition of the digital regulation mechanism—is an attribute of such mechanisms. If the temporal decomposition of the regulation mechanism is Δt, the pulse width is limited to an integer multiple of Δt. In addition, the spanning cycle, spanning successive ON and OFF pulses are also limited to an integer multiple of Δt.

1 shows a conventional switch-mode DC / DC power converter (see US Pat. No. 6,677,733), which includes a power stage 100 that converts an input voltage Vin into an output voltage Vout; A fixed-frequency control device (150) included in the power stage (100) for turning on / off the controllable switching device (110); And a duty cycle control mechanism 200 that controls the duty cycle of the switching device 110.

Since the controller 150 is a fixed-frequency controller, the switching device 110 is turned on at a fixed interval Tsw. The controller 150 turns off the switching device 110 by converting the duty cycle input into the ON time in cycle units (if necessary).

The duty cycle control mechanism includes an output voltage error predictor 230, a mechanism for generating an undistorted output voltage error prediction from the output voltage error signal, and a switching device 110 in such a way that the amplitude of the output voltage error is continuously minimized. ) ON and

It consists of an output-voltage-error-drive duty cycle selector that determines the OFF time.

In a digital implementation, the output voltage error predictor often takes the form of a digital proportional-integral-differential (PID) filter that operates on the output voltage error signal. PID filters offer improved signal-to-noise ratios and the possibility of compromise of delay. If delay is to be minimized, then a bi-valued output voltage error prediction obtained through a binary comparator will be appropriate. This is a property of the output voltage error predictor 230. In the duty cycle control mechanism 200, the prediction of the output voltage error is sampled by the duty cycle selector 250 at the end of every switching cycle, the value applied to select the duty cycle of the next switching cycle, This determines the ON and OFF times of the switching device 110.

Thus, duty cycle selector 250 selects Dmin or Dmax on a cycle-by-cycle basis (Dmin and Dmax are defined to span a range of input voltages specific to the application); Select Dmin when the output voltage error prediction is positive (that is, when the undistorted output voltage is higher than the desired output voltage) and Dmax when the output voltage error prediction is negative.

While the simplicity of the duty cycle control mechanism described above is effective, the duty-cycle-quantization-induced output voltage ripple may become unacceptable if the range of the input voltage and the resulting spread of Dmin and Dmax is too wide. .

2 shows a switch-mode DC / DC power converter according to the present invention, comprising: a power stage 101 for converting an input voltage Vin into an output voltage Vout; A control device 151 for turning on / off the controllable switching device 112 included in the power stage 101; And a duty cycle control mechanism 201 that controls the duty cycle switching device 111.

An additional feature of the control device 151 is that both the ON / OFF time of the controllable switching device is limited to an integer multiple of Δt because of the temporal resolution Δt of the control device. Since the control device 151 is not a fixed-frequency control device, the ON time and the OFF time must be input to turn ON / OFF the switching device 111.

The duty cycle control mechanism is adapted to recover the target duty cycle DT and the undistorted output voltage error VE from a target duty cycle predictor / output voltage error predictor 231, an output voltage error signal or an input voltage signal, or a combination of the two. A mechanism for predicting, determining a first set of at least one quantized duty cycle DQ _j j = 1,2, ... J in the vicinity of the target duty cycle DT for target duty cycle prediction, or A variable-frequency duty cycle quantizer 221 suitable for controlling the switching device 111; And generating a second set of at least two quantized duty cycles (DQk k = 1,2 ... K, in order from lowest to highest) from the first set of duty cycle DQ _j and repeating the above on a cycle-by-cycle basis. The ON / OFF time of the switching device 111 is determined by selecting one duty cycle (and corresponding ON time / OFF time pair) from the second set of duty cycles DQk, and the amplitude of the output voltage error continues. And an output-voltage-error-drive duty cycle selector 211 that selects to be minimal.

In a digital implementation, the target duty cycle predictor 231 is in the form of a digital PID filter that operates on an output voltage error signal. According to the invention, the filter may operate on an input voltage signal instead of or in addition to the output voltage error signal. Similarly, output voltage error predictor 231 is often implemented as a PID filter. PID filters offer an improved trade-off between signal-to-noise ratio and delay. Where delays should be minimal, even at the cost of limited reliable output voltage error prediction, the two or three value output voltage error prediction generated by a binary or ternary comparator is simple and effective. This is a property of the output voltage error predictor 231. Further, in the duty cycle control mechanism 201, the output-voltage-error-drive duty cycle selector 211 performs the duty cycle based on a sample of the output voltage error estimates obtained during the ON time or the OFF time or both. Choose.

In the case where the duty cycle selector 211 selects a duty cycle based on a sample of the output voltage error estimate obtained during the ON time, the prediction of the output voltage error is performed after the switching cycle starts and before the selection of the duty cycle is determined. Sampled by the cycle selector 211 and applied in a timely manner to effect the OFF operation inherent in the selected duty cycle. For buck converters, the output voltage error predictions are symmetrical with respect to the average, so the output voltage error prediction may be derived directly by sampling a binary or ternary comparator. The ideal sampling time can be determined from the ON times of DQ1 and DQK; Specifically, the sampling time for the start of the switching cycle is 1/4 (ON1 + ONK) and (if necessary) is cut to the nearest multiple of Δt. The calculation of the sampling time should be done as often as the set DQ _j changes.

 For a boost converter, if the output voltage error progression is not symmetric about the mean, derivation of the output voltage error prediction is not direct. In this case, the two- or three-valued output voltage error prediction is very easily constructed from two binary samples of the defined error voltage in time separated but steady state, with one sample usually being positive and the other sample being negative. For example, the first sample can be taken after the OFF time (before the switching cycle begins) 1/4 (OFF1 + OFFK), and the second sample is after the subsequent ON time (which causes the beginning of the switching cycle) 1 / 4 (ON1 + ONK), allowing output voltage error prediction to be configured and allowing the duty cycle to timely select the duty cycle to effect the OFF inherent in the selected duty cycle. If these two samples are both positive, the error prediction is positive; If both samples are negative, the error prediction is negative. If one sample is positive and the other is negative, the error prediction is zero for three-valued prediction, or does not change from the previous value for two-valued prediction.

In the case where the duty cycle selector 211 selects the duty cycle based on samples of the output voltage error prediction obtained during the ON time and again during the OFF time, the prediction of the output voltage error occurs once the switching cycle is started and turned off. It is sampled by the duty cycle selector 211 before the time is determined, again after the OFF time and before the final determination of the duty cycle, and at its implicit ON time. The duty cycle selector 211 applies the first sample to limit the selection of the duty cycle, and so doing determines the OFF time; And finally apply a second sample to select the duty cycle, which determines the ON time and marks the end of the switching cycle. Both selections are performed immediately upon sampling and timely effect the ON and OFF inherent in the selected duty cycle. The ideal sampling time is determined from the on / off times of DQ1 and DQK. For the start of the switching cycle, the first sampling time is 1/4 (ON1 + ONK) and is cut off (if necessary) to the nearest multiple of Δ; The second sampling time for the OFF time is 1/4 (OFF1 + OFFK) and is cut off (if necessary) to the nearest multiple of Δ. The calculation of the sampling time should be done as often as the set DQj changes.

Thus, the duty cycle selector 211 selects the duty cycle from the set DQk (and its corresponding ON time / OFF time pair) on a cycle-by-cycle basis, selects DQ1 when the total output voltage prediction is the highest, and estimates the total output voltage. Select DQK when this is the lowest, and select one of the remaining intermediate duty cycles when the total output voltage error is one of the corresponding intermediate values.

Determination of the set DQj for a given DT value is accomplished by the variable-frequency duty cycle quantizer 221 via a two-step process, where the first step is an enumeration of the quantized duty cycles in the vicinity of the DT, and the second The step is the selection of DQj from the listed possibilities.

Determination of the second set duty cycle DQk from the first set DQj is made by the duty cycle selector 211 through a two step process, the first step being an extension of the set DQj and the second step being a set DQj From the expansion of DQk is the choice. Extension of the set DQj to XDQj (j = 1, 2,... JJ) provides a comprehensive set of quantized duty cycles in which an effective set of operations DQk can be selected. The extension can be accomplished in a variety of ways. A very simple extension can be done by setting XDQj = (m + (j-2)) / n, where DQ1 = m / n. In order to provide more precise resolution, XDQj can be set as follows.

XDQj = (m + (j-3) / 2) / n j is odd

And if XDQj = (m + (j-4) / 2) / (n-1) j is even,

Or XDQj = (m + (j-3) / 2) / n j is odd

And XDQj = (m + (j-2) / 2) / (n + 1) j is even.

The number JJ of the elements of the set XDQj must be large enough so that the maximum duty cycle in the set is large enough to compensate for parasitic effects at high loads. The calculation of XDQj should be done as often as the DQj changes.

The duty cycle operation set DQk can be determined statically or dynamically; That is, DQk may be a predetermined subset of XDQj, or may be dynamically "mapped" to a subset of generally contiguous XDQj determined by the load. The number of elements in this subset K is in any case determined by the logic of the duty cycle selector. When the duty cycle selector 211 selects the duty cycle based on a binary or ternary sample of the output voltage error prediction obtained during the ON time or the OFF time, the number of elements K is 2 or 3; When the duty cycle selector 211 selects a duty cycle based on binary or ternary samples of the output voltage error prediction obtained during the ON time and the OFF time, the number of elements K ranges from 4 to 9 Is in. If K = 2, a predetermined subset of XDQj, i.e., XDQ1 and XDQJJ, produces an unacceptable output voltage ripple. This may be a parasitic artifact, inevitably accompanied by significantly higher duty cycles at higher loads than at low loads. To compensate for this, a mechanism for dynamically determining DQk is useful.

A simple but effective mechanism for dynamically determining the operation set of duty cycles when K = 2 is to count the number of consecutive DQ1 or DQ2, and "slid" DQk within XDQj when the number exceeds a predetermined threshold. Or adjust DQ1 or DQ2 up and down by repositioning. Alternatively, the number of DQ1 for DQ2 or an excess of DQ2 for DQ1 may be used to adjust DQ1 and DQ2 in the window. All of these mechanisms can be adapted for other values of K.

Applying variable-frequency duty cycle quantization, equal-cycle output voltage feedback, and dynamic determination of the duty cycle's operating set to compensate for load-dependent parasitic effects significantly improves static and dynamic performance with minimal computational cost . Although the duty cycle control mechanism described above has inherent performance limitations that are similar in nature to conventional duty cycle control mechanisms, the effect of duty cycle quantization on performance is substantially reduced without introducing application dependence.

3 shows a switch-mode DC / DC power converter according to the present invention, comprising: a power stage 102 for converting an input voltage Vin to an output voltage Vout; A control device 152 for turning on / off the controllable switching device 112 included in the power stage 102; A duty cycle control mechanism 202 that controls the duty cycle of the switching device 112.

An additional feature of the control device 152 is that, due to the temporal resolution Δt of the control device, both the ON / OFF time of the controllable switching device is limited to an integer multiple of Δt. Since controller 152 is not a fixed-frequency controller, the ON time and the OFF time must be entered to turn ON / OFF the switching device 112.

The duty cycle control mechanism includes the target duty cycle predictor / output voltage error predictor 232 and the target duty cycle DT and the undistorted output voltage error VE from the output voltage error signal or the input voltage signal or a combination of both. And a quantized duty from a pair of quantized duty cycles (DQmin and DQmax, collectively referred to as DT) extracted from a table of duty cycle pairs 242 indexed by the predicted target duty cycle DT Determine the ON time / OFF time of the switching device 112 by selecting the cycle (and the corresponding quantized ON time / OFF time pair) on a cycle basis; An output-voltage-error-drive duty cycle selector 252 that selects such that the amplitude of the output voltage error continues to be minimum.

In a digital implementation, the target duty cycle predictor 232 often takes the form of a digital proportional-integral-differential (PID) filter and operates on an output voltage error signal. According to the invention, the filter operates in lieu of or in addition to the output voltage error signal. Similarly, the output voltage predictor 232 is often implemented as a PID filter. PID filters offer a trade-off between signal-to-noise ratio and delay. When delay is to be minimized, the bi-valued output voltage error prediction produced by the binary comparator is simple and effective. This is a property of the output voltage error predictor 232. In addition, in the duty cycle control mechanism 202, the output voltage error is sampled by the duty cycle selector 252 after the switching cycle begins and before the selection of the duty cycle, and applied in time (to the duty cycle selector 252). By) effectuates the OFF operation inherent in the selected duty cycle.

In a buck converter, the derivation of the output voltage error prediction is not direct if the output voltage error aspect is not symmetric about the mean. In this case, the binary output voltage error prediction is most easily constructed from two binary samples of the defined error voltage in time separated but steady state, one of which is usually positive and the other is negative. For example, the first sample is taken at 1/4 (OFFmin + OFFmax) (before the start of the switching cycle) after the OFF time, and the second sample is after the subsequent ON time (indicating the start of the switching cycle) 1 Can be obtained at / 4 (ONmin + ONmax), allowing output voltage error prediction to be configured and allowing a timely selected duty cycle to effect the OFF operation inherent in the selected duty cycle. If both these samples are positive, the error prediction is positive; If both samples are negative, the error prediction is negative. If one sample is positive and the other is negative, the error prediction does not change from the previous value.

Whether it is a buck converter or a boost converter, the duty cycle selector 252 selects DQmin or DQmax on a cycle basis, wherein the DQmin and DQmax are extracted from the table 242 indexed by DT; Select DQmin when the output voltage error prediction is positive (when the undistorted output voltage is higher than the desired output voltage), and select DQmax when the output voltage error prediction is negative.

The structure and contents of the duty cycle pair table 242 is shown in FIG. Determination of DQmin and DQmax for a given value of DT is a two step process, the first step is the enumeration of quantized cycles in the vicinity of DT, and the second step is the selection of DQmin and DQmax from the possibilities listed above. Systematic enumeration of quantized duty cycles is achieved by generating a set of quantized ON time / OFF time pairs, wherein each pair of quantized ON time / OFF times are determined independently of each other. There is; That is, the sum of the ON time / OFF time is not fixed; It is confined to a set of discrete values {Tswi} (i = 1,2, ... I) and varies from pair to pair, where Tswi is an integer multiple of Δt. This set of quantized pairs is conventionally transformed into a set of quantized duty cycles. More switching cycle possibilities translate into more duty cycle possibilities, making it easier to select a duty cycle close to DT, which is an important factor in minimizing quantized-induced output voltage ripple.

One way to select DQmin and DQmax is to search the space of the quantized duty cycle around the DT and select the one closest to either side of the DT. Experience has shown that these choices can be problematic (for output voltage ripple) when one of the selected duty cycles is close to DT and the other is relatively far apart. In that case, it is desirable to reject anything closer to the second (or third) close duty cycle of the "side" of the DT, such as the rejected duty cycle. Once DQmin and DQmax are determined, the associated ON time / OFF time pairs specified by (ON, OFF) min and (ON, OFF) max are derived plainly.

To predict the size of the table 242, consider an example of a duty cycle control mechanism with a 20 MHz clock that controls the power stage at a nominal switching frequency of 1.25 MHz (16 clocks per nominal switching cycle), where switching Cycles are allowed to vary by one clock cycle from the nominal. If the ON and OFF times associated with DQmax are encoded for the ON and OFF times associated with DQmin, the resulting table may be configured as 12 X 128.

The simplicity of the duty cycle control mechanism described above is significant. The computational advantage of having a table of duty cycle pairs available is sometimes due to the cost of a reasonable amount of memory that is accessed. However, the combination of variable-frequency duty cycle quantization and co-frequency output voltage feedback greatly improves static and dynamic performance. Although the duty cycle control mechanism described above has inherent performance limitations inherently similar to conventional duty cycle control mechanisms, the effect on the performance of duty cycle quantization is substantially reduced regardless of the application.

4 shows a switch-mode power converter according to the present invention, comprising: a power stage 103 for converting an input voltage Vin into an output voltage Vout; A control device 153 included in the power stage for turning on / off the controllable switching device 113; And a duty cycle control mechanism 203 that controls the duty cycle of the switching device 113.

An additional feature of the control device 153 is that both the ON and OFF times of the controllable switching device are limited to an integer multiple of Δt due to the temporal decomposition (Δt) of the control device. Since the control device 153 is not a fixed-frequency control device, the ON time and the OFF time must be input in order to turn ON / OFF the switching device 113.

The duty cycle control mechanism predicts the target duty cycle DT and the undistorted output voltage error VE from the target duty cycle predictor / output voltage error predictor 233, the output voltage error signal or the input voltage signal, or a combination of both. Mechanisms; A variable-frequency duty cycle quantizer (223) for determining a quantized duty cycle (DQ) closest to the target duty cycle prediction (DT); And output-voltage-error-drive duty cycle selector 213, by generating a set of three quantized duty cycles (Dmin, DQ, and DQmax in order from smallest to largest) for the value of each DQ. And determining the ON and OFF times of the switching device 113 by selecting DQmin or DQ or DQmax (and corresponding ON time / OFF time pairs) on a cycle basis, and selecting to continuously minimize the amplitude of the output voltage error. It includes a mechanism.

In a digital implementation, target duty cycle predictor 233 often takes the form of a digital PID filter that operates on an output voltage error signal. According to the invention, the filter operates on the input voltage signal instead of or in addition to the output voltage error signal. Similarly, output voltage error predictor 233 is often implemented as a PID filter. PID filters offer improved signal-to-noise ratios and the possibility of compromise of delay. If delay is to be minimized and dynamic response is important, the three-value output voltage error estimate derived through the ternary comparator (binary comparator with dead zone) is simple and effective. That is an attribute of the output voltage error predictor 233. Further, in the duty cycle control mechanism 230, the prediction of the output voltage error is sampled by the duty cycle selector 213 and applied in a timely manner after the switching cycle is started and before the selection of the duty cycle is determined (the duty cycle selector ( 123) ferment the OFF operation inherent in the selected duty cycle.

In a buck converter, if the output voltage error behavior is symmetric about the mean, the output voltage error prediction is directly derived by sampling the ternary comparator. The ideal sampling time is determined from the ON times of DQmin and DQmax; Specifically, the sampling time for the start of the switching cycle is 1/4 (ONmin + ONmax) cut (if necessary) to the nearest multiple of Δt. The calculation of the sampling time should be done as often as the DQ changes.

(The 3-valued output voltage error estimate may be constructed from two separate 2-valued error samples in time, where the 2-valued samples are normally positive and one sample negative in the steady state.)

In a boost converter, if the output voltage error pattern is not symmetrical with respect to the mean, derivation of the output voltage error estimate is not direct. In this case, the 3-valued output voltage error can be very easily constructed from two separated 2-valued samples in time, characterized in that one sample is usually positive and the other sample is negative in steady state. For example, the first sample is taken after the OFF time (before the start of the switching cycle) 1/4 (OFFmin + OFFmax), and the second sample is 1/4 after the subsequent ON time (indicating the start of the switching cycle). Taken at (ONmin + ONmax), the output voltage error prediction is constructed and the selected duty cycle can timely effect the OFF operation inherent in the selected duty cycle. If both these samples are positive, the error prediction is positive; If both samples are negative, the error estimate is zero (not negative or positive).

Whether it is a buck converter or a boost converter, the duty cycle selector 213 selects DQmin or DQmax (and its corresponding ON time / OFF time pair) in units of cycles; Select DQmin when the output voltage error estimate is positive (that is, when the non-distorted output voltage is higher than the desired output), select DQmax when the output voltage error estimate is negative, and when the output voltage error estimate is zero (positive) Not negative) DQ is selected.

Determination of DQ for the value of a given DT is accomplished by the variable-frequency duty cycle quantizer 223 via a two step process, where the first step is an enumeration of the quantized duty cycles in the vicinity of the DT and the second step is The choice of DQ from the possibilities listed above. Systematic enumeration of quantized duty cycles is achieved by generating a set of quantized ON time / OFF time pairs, wherein the quantized ON time and OFF time of each pair (in the set) is not fixed; It is limited to a pair of discrete values {Tswi} (i = 1,2, ... I) and turns into a pair-to-pair, where Tswi is an integer multiple of Δt. This set of quantized pairs is conventionally transformed into a set of quantized duty cycles. More switching cycle possibilities are transformed into more duty cycle possibilities, making it possible to select a duty cycle closer to DT, which is an important factor in minimizing quantized-induced output voltage ripple. DQ is chosen as the closest but less duty cycle to DT, and the associated ON time / OFF time pairs are derived plainly.

Determination of DQmin and DQmax is made by the duty cycle selector 213. While many options are available, simple and cost effective options are set up as follows:

ONmin = ONq -1 x Δt OFFmin = OFFq + 1 x Δt

ONq = ONq OFFq = OFFq

ONmax = ONq + 1 x Δt OFFmax = OFFq -1 x Δt

As noted above, the 3-valued output voltage error prediction determines the ON time and adjusts ONq with a -1, 0, or +1 clock. The OFF time is implicitly determined by adjusting OFFq in the opposite direction. These values allow the converter to effectively respond to changes in line and load conditions at the expense of good output voltage ripple.

The second simple and cost effective option is set as follows:

ONmin = ONq -1 x Δt OFFmin = OFFq

ONq = ONq OFFq = OFFq

ONmax = ONq OFFmax = OFFq -1 x Δt

As noted above, the 3-valued output voltage error prediction determines the ON time and adjusts ONq with a -1, 0, or +1 clock. The OFF time is determined by adjusting OFFq to 0, 1, or -1. These values allow the converter to reduce output voltage ripple at the expense of increasing sensitivity to changes in line and load conditions.

The simplicity of the aforementioned duty cycle is attractive. In addition, three-valued output voltage feedback at the same frequency significantly improves static and dynamic performance. The duty cycle control mechanism described above has an inherent performance limitation that is essentially similar to conventional duty cycle control mechanisms, but in terms of performance the effect of duty cycle quantization is substantially reduced without incurring application dependencies.

5 shows a switch mode DC / DC power converter according to the present invention, comprising: a power stage 104 for converting an input voltage Vin into an output voltage Vout; A control device (154) included in the power stage (104) for turning on / off the controllable switching device (114); And a duty cycle control mechanism 204 that controls the duty cycle of the switching device 114.

An additional feature of controller 154 is that both the ON / OFF operating time of the controllable switching device is limited to a government multiple of Δt due to the temporal resolution Δt of the controller. Since the control device 154 is not a fixed-frequency control device, the ON time and the OFF time must be input to turn on / off the switching device 114.

The duty cycle control mechanism is adapted to correct the target duty cycle DT and the non-distorted output voltage error VE from a target duty cycle predictor / output voltage error predictor 234, an output voltage error signal or an input voltage signal, or a combination of both. Predictive mechanism; A variable-frequency duty cycle quantizer (224) for determining the quantized duty cycle (DQ) closest to the duty cycle prediction (DT); Output-voltage-error-drive duty cycle selector 214, generating six quantized duty cycle sets (DQmin, DQmn, DQn DQx, DQmx, DQmax) arranged from lowest to highest for the value of each DQ By selecting DQmin or DQmn or DQn or DQx or DQmx or DQmax (and corresponding ON / OFF time pairs) to determine the ON / OFF operating time of the switching device 114 and the amplitude of the output voltage error It includes a mechanism for selecting to be minimal.

In digital implementations, it often takes the form of a digital proportional-integral-differential (PID) filter that operates on the output voltage error signal. In accordance with the present invention, the filter may operate on an input voltage signal instead of or in addition to the output voltage error signal. Similarly, the output voltage error predictor 234 is often implemented as a PID filter. PID filters offer the possibility of compromise between delay and improved signal-to-noise ratio. If delay should be minimized and both static and dynamic responses are important, more accurate output voltage error predictions derived from multiple samples will be appropriate. This is an attribute of the output voltage error predictor 234. Also, in the duty cycle control mechanism 204, the prediction of the output voltage error is sampled once by the duty cycle selector 214 through a ternary comparator after the switching cycle begins but before the OFF operating time is determined. After the OFF operation time but before the final determination of the duty cycle and its implied ON operation time, it is sampled again via a binary comparator. The duty cycle selector 214 applies the first sample to limit the selection of the duty cycle and thus determine the OFF operating time; Applying a second sample to eventually select the selection of the duty cycle; Thus determining the ON operating time; Marks the end of the switching cycle. Both selections are made immediately upon sampling and timely effect the OFF and ON operating times inherent within the selected duty cycle.

For buck converters, if the output voltage error behavior is symmetric about the mean, the output voltage error prediction can be derived directly by sampling the ternary comparator. The ideal sampling time is determined from the on / off times of DQmin and DQmax. For the start of the switching cycle, the first sampling time is 1/4 (ONmin + ONmax) cut (if necessary) to the nearest multiple to Δt; For the OFF operation time the second sampling time is 1/4 (OFFmin + OFFmax) cut in multiples (if necessary) closest to DELTA t. The calculation of the sampling time should be done as often as the DQ changes.

(Note that the 3-valued output voltage error prediction may be constructed from two 2-valued samples, designated as one sample is usually positive and the other sample is negative in time separated but steady state. Also note that two If a two-value sample is used to obtain a three-value output voltage error estimate, then the three-value estimate can be scheduled during switch on when DT> .5 and during switch off when DT <.5. In this case, the two-value prediction may be scheduled during switch-on when DT <.5 and during switch-off when DT> .5.)

For a boost converter, if the output voltage error behavior is not symmetric about the mean, derivation of the output voltage error prediction is not direct. In this case, the 3-valued output voltage error estimate is very easily constructed from two 2-valued samples of the error voltage, designated as one sample is usually positive and the other sample is negative in time separated but steady state. For example, the first sample is taken at 1/4 (OFFmin + OFFmax) after the OFF operating time (before the beginning of the switching cycle), and the second sample is after the continuing ON operating time (indicating the beginning of the switching cycle) 1 Taken at / 4 (ONmin + ONmax); The output voltage error prediction can be configured and the selected duty cycle can timely effect the OFF operation inherent in the selected duty cycle. If these two samples are positive, the error prediction is positive; If both samples are negative, the error prediction is negative. If one sample is positive and the other sample is negative, the error prediction is zero (not positive).

Thus, the duty cycle selector 214 selects DQmin, DQmn, DQn, DQx, DQmx, or DQmax (and its corresponding ON time / OFF time pair) in cycles; Select DQmin when the total output voltage error estimate is the highest, select DQmax when the total output voltage error estimate is the lowest, and one of the remaining intermediate duty cycles when the total output voltage error is one of the corresponding intermediate values. Select.

Determination of DQ for the value of a given DT is accomplished by the variable-frequency duty cycle quantizer 223 via a two-step process, where the first step is an enumeration of duty cycles in which the DT is quantized nearby and the second step Is the choice of DQ from the possibilities listed above. Systematic enumeration of quantized duty cycles is achieved by generating a set of quantized ON time / OFF time pairs, wherein each pair of quantized ON time / OFF times is determined independently of each other; That is, the sum of the ON time and the OFF time is not fixed; It can be varied by being constrained by a set of discrete values {Tswi} (i = 1,2, ... I), where Tswi is an integer multiple of [Delta] t. This set of quantized pairs is usually transformed into a set of quantized duty cycles. More switching cycle possibilities translate into more duty cycle possibilities, making it possible to select a duty cycle closer to DT, which is an important factor in minimizing quantized-induced output voltage ripple. DQ is chosen to be closest to the DT but smaller, and the associated ON time / OFF time pair is usually derived.

Determination of DQmin to DQmax is made by the duty cycle selector 213. While many options are available, simple and cost effective options are set up as follows:

ONmin = ONq -1 x Δt OFFmin = OFFq + 2 x Δt

ONq = ONq -1 x Δt OFFmn = OFFq

ONn = ONq OFFn = OFFq + 1 x Δt

ONx = ONq OFFn = OFFq-1 x Δt

ONmx = ONq + 1 x Δt OFFmx = OFFq

ONmax = ONq + 1 x Δt OFFmax = OFFq-2 x Δt

As noted above, the 3-valued output voltage error estimate determines the ON time and adjusts ONq by a -1, 0, or +1 clock. The second two-value predictor determines the OFF time and adjusts OFFq by +2, +1, 0, -1, or -2 clocks in accordance with the values of the two predictions. These values allow the converter to respond effectively to changes in line and load conditions, and limit the output voltage ripple to steady state.

The simplicity of the duty cycle control mechanism is attractive. In addition, the application of twice the same cycle output voltage feedback significantly improves static and dynamic performance. The duty cycle control mechanism described above has inherent performance limitations that are essentially similar to conventional duty cycle control mechanisms, but in terms of performance the effect of duty cycle quantization is substantially reduced without incurring application dependencies.

While the power converter is operating in continuous conduction mode, the duty cycle control mechanism described above (implementing the PWM scheme) can provide effective output voltage regulation, but the power converter must be in discontinuous conduction mode to provide efficient operation at light loads. When switching to, it is often necessary to add a low power or power-saving control mechanism to regulate the output voltage. The mechanism for regulating in discontinuous conduction mode (DCM) typically implements a pulse frequency modulation (PFM) scheme, where the controllable switch has a predetermined threshold for predicting output voltage error for a fixed period of time. It turns ON every time it falls down. In this case, it is necessary to devise a mechanism to detect the transition to and departure from DCM and smoothly transition from one duty cycle control mechanism to another. Such a mechanism must deal with the rapid change as well as the gradual change of the load.

Rapid resumption of the load (from low load conditions) presents a more serious challenge for the designer of the power supply regulator. In the case of a buck converter, for example, a slam is usually detected when the (slam-induced) drop in the output voltage triggers a threshold detection mechanism, which is probably the same mechanism used to turn on the switch in PFM mode. do. The transition from PFM to PWM is done directly by keeping the switch ON until the energy stored in the converter is sufficient to supply a new load at the desired output voltage level (via the PWM duty cycle control mechanism).

In the case of boost converters, however, recovery from the slam is a bit more complicated due to the flyback nature of the boost technique. The switch cannot remain ON until the energy stored in the capacitor is sufficient to support the new load, but must be cycled. One way to enable the transition from PFM to PWM in this case is to detect the slam by a series of duty cycles converging (from above) to the duty set of operation DQk of the duty cycle generated by the PWM duty cycle control mechanism. Will immediately switch to OWM.

Claims (31)

In a switched-mode DC / DC converter generating one or more output voltages (Vout), One or more power stages that convert the input voltage Vin into an output voltage Vout and each include one or more controllable switching devices; A control device for turning on / off the controllable switching device; And A duty cycle control mechanism for controlling the duty cycle of the controllable switching device, The control device is limited by the temporal resolution (Δt) of the control device so that the ON time and the OFF time of the controllable switching device are limited to an integer multiple of Δt, The duty cycle control mechanism, A mechanism for predicting an output voltage error that is a difference between the non-distorted output voltage and the desired output voltage Vdo; A mechanism for predicting a target duty cycle, which is a duty cycle essential for obtaining the desired output voltage Vdo; Determine a first set of one or more quantized ON time / OFF time pairs suitable for controlling the controllable switching device for a target duty cycle estimate, and for each pair of quantized ON time / OFF times (of the first set) The sum of is defined as a set of discrete values {Tswi} [(i = 1,2, ... I), where I is a positive integer and Tswi is an integer multiple of Δt; And The ON time of the controllable switching device by selecting the ON time / OFF time pair in cycle units from a second set of two or more quantized ON time / OFF time pairs derived from the first set and defined as in the first set; And a selector mechanism that determines an OFF time and selects in such a way that the amplitude of the output voltage error is continuously minimized. The method of claim 31, wherein The converter is a buck converter. The method of claim 31, wherein The converter is a multi-phase buck converter. The method of claim 31, wherein And said converter is a boost converter. The method of claim 31, wherein And said converter is an inverting buck-boost converter. The method of claim 31, wherein And said converter is an up-down converter. The method of claim 31, wherein And said converter is a forward converter. The method of claim 31, wherein And said converter is a flyback converter. The method of claim 31, wherein Said converter is a multi-output converter comprising two or more controllable switching devices. The method of claim 31, wherein And the mechanism for predicting the target duty cycle uses an algorithm comprising the input voltage Vin. The method of claim 31, wherein And the mechanism for predicting the target duty cycle uses an algorithm comprising the output voltage (Vout). The method of claim 31, wherein The duty cycle quantization mechanism (DQ) is one or more quantized ON time / OFF determined for the predicted target duty cycle taking into account the difference between the duty cycle indicated by the preliminary ON time / OFF time pair and the predicted target duty cycle. Determining whether to include the preliminary ON time / OFF time pair in a first set of time pairs. The method of claim 31, wherein The duty cycle quantization mechanism (DQ) calculates the difference between the duty cycle indicated by the preliminary ON time / OFF time pair and the predicted target duty cycle, and the duty cycle indicated by each of the other preliminary ON time / OFF time pairs. Considering the difference between the target duty cycles determined, determining whether to include the preliminary ON time / OFF time pair in a first set of one or more quantized ON time / OFF time pairs determined for the predicted target duty cycle. Conversion method characterized in that. The method of claim 31, wherein The duty cycle quantization mechanism (DQ) determines a first set of one or more quantized ON time / OFF time pairs for target duty cycle prediction by accessing a set of tables indexed by target duty cycle prediction. How to convert. The method of claim 31, wherein The second set of two or more ON time / OFF time pairs is a set of j pairs (j = 1, 2, ... J) ordered by the duty cycle indicated from lowest to highest; The output voltage error estimate is a j-value ordered from highest to lowest; The selector mechanism SM selects an ON time / OFF time pair having the lowest duty cycle indicated when the current output voltage error estimate is the highest, and an ON having the duty cycle highest indicated when the output voltage error estimate is the lowest. Selecting a time / off time pair and selecting one of the remaining intermediate pairs when the current output voltage error is one of the corresponding intermediate values. The method of claim 31, wherein After the switching cycle begins and before the OFF operating time inherent in the selected pair, the current output voltage error prediction is generated and the ON time / OFF time pair is a second of two or more quantized ON time / OFF time pairs. A conversion method selected from the set. The method of claim 31, wherein After the switching cycle begins and after the OFF operating time inherent in the selected pair, the current output voltage error prediction is generated and the ON time / OFF time pair is a second of two or more quantized ON time / OFF time pairs. A conversion method selected from the set. The method of claim 31, wherein The second set of two or more ON time / OFF time pairs is exactly a set of two pairs arranged by a duty cycle indicated from Low to High; The output voltage error prediction is high and low two-valued; The selector mechanism SM selects an ON time / OFF time pair with a low displayed duty cycle when the current output voltage error prediction is high, and ON with a high displayed duty cycle when the current output voltage error prediction is low. A conversion method characterized by selecting a time / off time pair. The method of claim 18, After the switching cycle begins and before the OFF operating time inherent in the selected pair, the current output voltage error prediction is generated and the ON time / OFF time pair is selected. The method of claim 19, The predicted output voltage error is an output of a binary comparator. The method of claim 31, wherein And said second set of two or more quantized ON time / OFF time pairs is dynamically adjusted to compensate for load-dependent parasitic effects. The method of claim 21, The mechanism used to adjust the second set of two or more quantized ON time / OFF time pairs uses one or more counters and one or more comparators. The method of claim 31, wherein And said second set of two or more ON time / OFF time pairs is constrained by said selector mechanism (SM) to prevent excessive electromagnetic interference (EMI). The method of claim 23, The constraint is that the longest of the switching cycles represented by the ON time / OFF time pairs has the form of a requirement that the shortest differs by a maximum of nx Δt (n = 1,2, ... N). Characterized by the conversion method. The method of claim 31, wherein Part of the functionality of the mechanism for predicting the output voltage error is implemented in software in a microprocessor. The method of claim 31, wherein Part of the functionality of the mechanism for predicting the target duty cycle is implemented in software in a microprocessor. The method of claim 31, wherein Part of the functionality of the duty cycle quantization mechanism (DQ) is implemented in software in a microprocessor. The method of claim 31, wherein A part of the function of said selector mechanism (SM) is implemented in software in a microprocessor. The method of claim 3, wherein And said selector mechanism further ensures that the arrangement of each phase of said multi-phase buck converter is in accordance with a standard multi-phase case. The method of claim 9, The selector mechanism further ensures that the controllable switching device is not switched ON at the same time. A method of converting an input voltage into an output voltage by a switching mode DC / DC converter, The input voltage Vin is converted into an output voltage Vout by the power stage PS, The power stage includes one or more controllable switching devices CS that are ON / OFF operated by a control device CD, By the temporal resolution? T of the control device, both the ON time / OFF time of the controllable switching device is limited to an integer multiple of? T; The duty cycle control mechanism (DC) for controlling the duty cycle of the controllable switching device, A mechanism for predicting an output voltage error that is the difference between the undistorted output voltage and the desired output voltage Vdo; A mechanism for predicting a target duty cycle, which is an essential duty cycle to achieve a desired output voltage Vdo; Duty cycle quantization mechanism (DQ), where each pair (of the first set) determines a first set of one or more quantized ON time / OFF time pairs suitable for controlling the controllable switching device, for a target duty cycle. The sum of the quantized ON time / OFF time of is defined as a set of discrete values {Tswi} [(i = 1,2, ... I), where I is a positive integer and Tswi is an integer multiple of Δt] -; And ON / OFF of the controllable switching device by selecting an ON time / OFF time pair on a cycle basis from a second set of two or more quantized ON time / OFF time pairs derived from the first set and defined like the first set A selector mechanism (SM) for determining an operating time and for selecting in such a way that the amplitude of the output voltage error continues to be minimized; Conversion method characterized in that it comprises a.

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