KR20070089441A - Direct tunneling memory cell and cell array - Google Patents

Abstract

A memory cell and a memory cell array of a direct tunneling memory device are provided to reduce the voltage applied to the memory cell, to improve a data write speed and to decrease the consumption of power by storing warm electrons of a high energy state in a charge storing layer. A memory cell of a direct tunneling memory device includes a semiconductor substrate(50), a first junction region(52a) in the substrate, a second junction region, a channel region and a stacked structure. The second junction region(52b) is spaced apart from the first junction region in the substrate. A forward bias is applied to the second junction region in a first write process. The channel region is defined between the first and the second junction regions in the substrate. The stacked structure is formed on the channel region. The stacked structure is composed of a tunnel insulating layer(54), a charge storing layer(56), a control insulating layer(58) and a control gate electrode(60).

Description

DIRECT TUNNELING MEMORY CELL AND CELL ARRAY}

1 and 2 are cross-sectional views of memory cells of a conventional nonvolatile memory device.

3 is a cross-sectional view of a memory cell of the memory device according to the first embodiment of the present invention.

Fig. 4 is an equivalent circuit diagram of a memory cell array of the memory device according to the first embodiment of the present invention.

5 is a cross-sectional view of a memory cell of the memory device according to the second embodiment of the present invention.

Fig. 6 is an equivalent circuit diagram of a cell array of a memory device according to the second embodiment of the present invention.

7 to 11 are operations of memory cells of the memory device according to the first embodiment of the present invention.

12 to 16 illustrate a method of operating memory cells of a memory device according to a second embodiment of the present invention.

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to memory cells and memory cell arrays of semiconductor memory devices, and more particularly to memory cells and memory cell arrays of nonvolatile memory devices.

In order to achieve high integration of DRAM devices, researches on hybrid DRAM devices in which transistors and capacitors are combined, and in recent years, research on direct tunneling memory devices having a structure similar to flash memory has been actively conducted.

In general, a flash memory includes a tunnel insulating film having a thickness of about 10 nm between a channel region and a floating gate, and is connected to the floating gate by FN tunneling or channel hot carrier injection (CHI). Store the charge.

1 is a cross-sectional view illustrating a conventional flash memory device in which electrons are stored in a floating gate by FN tunneling, and FIG. 2 is a view illustrating a conventional flash memory device in which electrons are stored in a floating gate by channel hot carrier injection. It is a section for.

Referring to FIG. 1, a conventional flash memory device includes a first junction region 12s and a second junction region 12d, a first junction region 12s, and a second junction region formed in a semiconductor substrate 10. The tunnel insulating film 14, the charge storage layer 16, and the control insulating film 18 are included on the channel region defined between 12d. The gate electrode 20 is formed on the control insulating film 18. The charge storage layer 16 may be an insulating layer having a floating gate in which charge is stored or a trap site in which charge is trapped.

The tunnel insulating film 14 of the flash memory device has a thickness of about 10 nm, and applies 10 V to the gate electrode 20 and 0 V to the channel region, thereby allowing the charge storage layer 16 to pass through the tunnel insulating film 14. Stores the electron in).

Referring to FIG. 2, a flash memory device programmed by channel hot carrier injection applies 5V to a gate electrode and 3V to a second junction region 12d to store electrons in the charge storage layer 16. High energy electrons generated near the second junction region are injected into the charge storage layer 16 over the potential barrier of the tunnel insulating layer 14.

In flash memory devices, program and erase are disadvantageous in that high voltage is required and the tunnel insulation film deteriorates in repeated program / erase cycles. The recently introduced direct tunneling memory device has a structure similar to that of a flash memory device, and like FN tunneling, programming and erasing are performed by using a voltage difference between the gate electrode and the channel region. The direct tunneling memory device has a tunnel insulating film about 1 nm to 3 nm thinner than the flash memory device, and electrons are stored in the charge storage layer through the tunnel insulating film through direct tunneling rather than FN tunneling or hot carrier injection. . Tunnel current passing through the insulating film increases exponentially with decreasing thickness of the insulating film. Therefore, the direct tunneling memory device requires a relatively low gate voltage, has a very low power consumption characteristic, and has a high operating speed and excellent durability compared to FN tunneling.

Direct tunneling memory devices have the advantages of lower power consumption and faster operating speed than flash memory devices, but it is important to realize lower power consumption and operating speed due to high integration. SUMMARY OF THE INVENTION The present invention is to provide a memory cell that is similar in geometry to a memory cell of a conventional direct tunneling memory device and can realize lower power consumption and faster operating speed.

Furthermore, the present invention is to provide a memory cell array structure capable of high capacity multi-bit storage and advantageous for high integration.

In order to achieve the above technical problem, the present invention provides a direct tunneling memory device that is programmed using warm carrier injection.

The memory cell of this storage device includes a semiconductor substrate, a first junction region formed in the semiconductor substrate, and a second junction region formed in the semiconductor substrate spaced apart from the first junction region. The second junction region is applied with a forward bias with the semiconductor substrate during a write operation. A channel region is defined in the semiconductor substrate between the first junction region and the second junction region, and includes a tunnel insulation layer, a charge storage layer, a control insulation layer, and a control gate electrode sequentially stacked on the channel region.

The present invention provides a memory cell array of a direct tunneling memory device having an integration degree of 6F2 and 4F2. Here, 'F' means the minimum feature size of the design rule, nF2 means that the size occupied by one memory cell is n times the minimum feature area. The 6F2 cell array includes a plurality of pairs of bit lines arranged in parallel, a source line disposed between the first bit line and the second bit line constituting the bit line pair, and a word line crossing the bit line pair and the source line. It includes.

A plurality of memory cells are disposed between the first bit line and the source line such that second junction regions are connected to the first bit line and first junction regions are connected to the source line. In addition, a plurality of other memory cells are disposed between the second bit line and the source line such that second junction regions are connected to the second bit line and first junction regions are connected to the source line. In this embodiment, the gate electrodes of the memory cells are connected to the word line, and the memory cells connected to the same bit line are connected to different word lines.

The 4F2 cell array includes a plurality of parallel bit line pairs and a plurality of word lines crossing the bit line pair, and a plurality of memory cells are disposed between the first bit line and the second bit line forming the bit line pair. do. First junction regions of the memory cells are connected to the first bit line, second junction regions are connected to the second bit line, and gate electrodes are connected to the word line. In this embodiment, memory cells connected to the same bit line are connected to different word lines.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. However, the present invention is not limited to the embodiments described herein and may be embodied in other forms. Rather, the embodiments introduced herein are provided to ensure that the disclosed subject matter is thorough and complete, and that the spirit of the present invention to those skilled in the art will fully convey. In the drawings, the thicknesses of layers and regions are exaggerated for clarity. Where a layer is said to be "on" another layer or substrate it may be formed directly on the other layer or substrate or a third layer may be interposed therebetween. In addition, where one component is said to be adjacent to another component, it may be in direct contact with another component or spaced apart by intervening third components therebetween. Portions denoted by like reference numerals denote like elements throughout the specification.

3 is a cross-sectional view showing a memory cell of the direct tunneling memory device according to the first embodiment of the present invention.

Referring to Fig. 3, these memory cells have similar geometrical structures in conventional flash memory devices and direct tunneling memory devices. The memory device is formed in the semiconductor substrate 50 with the first junction region 20a and the second junction region 20b spaced apart from each other by a predetermined distance. A channel region is defined in the substrate between the first junction region 20a and the second junction region 20b. A tunnel insulating layer 54, a charge storage layer 56, and a control insulating layer 58 are stacked on the channel region, and a gate electrode 60 is formed on the control insulating layer 58. The tunnel insulating film 54 has a thickness of about sub-nano to about 3 nm, and preferably has a thickness of about 1 nm to about 1.5 nm. The charge storage layer 56 may be a floating gate made of a conductive film or a semiconductor film, a nanoscale conductor or an insulator in which semiconductor quantum dots are spread therein, or may have its own trap site. It may be an insulator having a site and an interface trap site. Since the tunnel insulating layer 54 is thinner than the flash memory device, data retention may be lower than that of the flash memory device, which is a nonvolatile memory device. However, the retention characteristics of the conventional direct tunneling memory device, such as suppressing charge tunneling from the charge storage layer 56 to the channel region by increasing the flat band potential as the doping concentration of the channel region increases. Can improve.

In the write operation of the conventional direct tunneling memory device, 0 V is applied to the first junction region, the second junction region, and the channel region, and a voltage of 6 V is applied to the gate electrode. However, the second junction region of the direct tunneling memory device of the present invention is characterized in that a forward bias is applied to the junction of the second junction region during a write operation. For example, a voltage of -4V is applied to the second junction region 52b in a write operation, and a voltage of 4V relatively lower than that of a conventional direct memory device is applied to the gate electrode. As forward bias is applied to the junction of the second junction region, electrons flow into the substrate and the channel to increase the potential of the electron, and the junction of the first junction region 52a is reversely biased. Similar to conventional channel hot carrier injection, electrons accelerated along the channel region toward the first junction region 52a produce a warm carrier in a relatively lower energy state than the hot carrier in the vicinity of the first junction region. It is attracted to a gate electric field and tunnels directly through the tunnel insulating film 54. Worm electrons, which are in a relatively high energy state compared to tunneling electrons of the conventional direct tunneling memory device, are stored in the charge storage layer 56 through the tunnel insulating film 54 even at a low gate voltage. Thus, the memory cell has an information storage region in the charge storage layer in a portion adjacent to the first junction region opposite to the second junction region which is forward biased.

In the memory cell according to the present invention, direct tunneling occurs even at a low gate voltage as compared with a conventional direct tunneling memory device. In addition, since a negative voltage is applied to the second junction region, it is possible to implement a cell array having a structure that can reduce program disturbance.

4 is an equivalent circuit diagram illustrating a cell array of a direct tunneling memory device according to a first embodiment of the present invention.

Referring to FIG. 4, the memory cell array includes a plurality of word lines arranged in a row direction, a plurality of pairs of bit lines and a source line intersecting the word lines. The bit lines include a first bit line BLn and a second bit line / BLn. The source line SLn is disposed between the first bit line BLn and the second bit line / BLn. A first memory cell group composed of a plurality of memory cells is disposed between the first bit line BLn and the source line SLn, and also between the second bit line / BLn and the source line SLn. A second memory cell group consisting of a plurality of memory cells is arranged. Second junction regions of the first memory cell group are connected to the first bit line BLn, and second junction regions of the second memory cell group are connected to the second bit line / BLn. The memory cells of the first memory cell group and the memory cells of the second memory cell group correspond to one-to-one to share a first junction region, and the first junction regions are connected to the first source line SLn. The gate electrode of the memory cells is connected to a word line. At this time, the gate electrodes of the memory cells in each group are connected to different word lines, and the gate electrodes of the memory cells belonging to different cell groups and sharing the first junction region are connected to the same word line. Therefore, memory cells connected to the same bit line are connected to different word lines, so that memory cells connected to the bit line are not disposed between repeated pairs of bit lines.

In the memory cell selected in the direct tunneling memory device according to the present invention, -4 V is applied to the write operation bit line / BLn, 0 V is applied to the source line SL1, and 4 V is applied to the word line Wsel. A negative voltage of -4V is applied to the bit line / BLn, so that the second junction region junction of the NMOS memory cell is forward biased and near the first junction region connected to the source line SL1 to which 0V is applied. Data Bit is stored in a storage area located in the charge storage layer. In this manner, the write operation can be performed by randomly accessing the memory cells constituting the cell array. The erase operation may be performed by applying a negative erase voltage to the gate electrode and / or a positive erase voltage to the channel region, applying a negative erase voltage to the gate electrode, and applying a positive voltage to the first junction region. The generated hot holes may be injected into the charge storage layer and erased.

5 is a cross-sectional view showing a memory cell of the direct tunneling memory device according to the second embodiment of the present invention.

Referring to FIG. 5, the direct tunneling memory device according to the second embodiment includes a charge storage layer divided into a portion 106a adjacent to the first junction region 102a and a portion 106b adjacent to the second junction region 102b. Has

As illustrated, a channel region is defined in the semiconductor substrate 100 between the first junction region 102a and the second junction region 102b, and the tunnel insulating layer 104 and the charge storage layer are formed on the channel region. 106a and 106b and the control insulating film 108 are laminated. The charge storage layer is divided into a first portion 106a adjacent to the first junction region 102a and a second portion 106b adjacent to the second junction region 102b, and the first portion 106a. ) And the second portion 106b are interposed therebetween to electrically separate them. The gate electrode 110 is formed on the control insulating layer 108.

Like the first embodiment described above, the memory cell of the second embodiment is also characterized in that a forward bias is applied to the second junction region 102b during a write operation. For example, a voltage of -4V is applied to the second junction 102b and a voltage of 4V is applied to the gate electrode in the write operation. The electrons accelerated along the channel region toward the first junction region 102a generate a warm carrier in an energy state relatively lower than that of the hot carrier in the vicinity of the first junction region and are attracted to the gate electric field to form the tunnel insulating layer 104. Tunneled directly through. The memory cell array shown in Fig. 4 can be constructed by using the memory cells according to the second embodiment. In this case, the storage region Bit1 is disposed in the first portion adjacent to the first junction region instead of the second junction region to which the forward bias is applied.

The memory cells according to the first and second embodiments shown in FIGS. 3 and 5 may also be used as multi-bit memory cells capable of storing two bits of data in one memory cell. In the case of a multi-bit memory cell, the charge storage layer may be an insulator having a trap site rather than a floating gate or an insulator in which quantum dots are spread.

6 is an equivalent circuit diagram illustrating a memory cell array according to a second exemplary embodiment of the present invention.

Referring to FIG. 6, the memory cell array includes a plurality of word lines WLn arranged in a row direction and a plurality of pairs of bit lines arranged in a column direction crossing the word lines. Each bit line pair is composed of a first bit line BLn and a second bit line / BLn. A memory cell group consisting of a plurality of memory cells is disposed between the first bit line BLn and the second bit line / BLn. A gate electrode of a memory cell is connected to the word line WLn, a first junction region is connected to the first bit line BLn, and a second junction region is connected to the second bit line / BLn. . The memory cells selected in this cell array have a first storage region Bit1 and a second storage region Bit2 at portions adjacent to the first junction region and portions adjacent to the second junction region, respectively.

7 to 11 illustrate the write, erase and read operations of a selected memory cell when the memory cell array shown in FIG. 6 is configured using the memory cell structure shown in FIG. 3.

Referring to FIG. 7, according to a state in which electrons are stored in the first storage area Bit1 and the second storage area Bit2, the memory devices of the present invention may correspond to '00', '01', '10' and '11'. It can have a logical value. The threshold voltage difference of the memory cells according to the potentials of the first and second storage regions Bit1 and Bit2 may be determined.

The first writing operation in which electrons are stored in the first storage area Bit2 near the first junction area 102a is the same as that shown in FIG. 3. Accordingly, a write voltage of 4 V is applied to the word line WL2 of the selected memory cell, 0 V is applied to the first bit line BL2, and -4 V is applied to the second bit line / BL2, thereby providing the first bit line. Data is stored in the first storage area Bit1 near the first junction area 102a connected to BL2.

In the second write operation (write 2) for storing electrons in the second storage area Bit2, a voltage is applied to the first junction region 102a and the second junction region 102b as opposed to the first write operation (write1). do. That is, a negative voltage is applied to the first bit line BLn to which the first junction region 102a is connected so that a forward bias is applied to the first junction region 102a, and the second junction region 102b is Electrons are stored in the second storage area Bit2 adjacent to the second bit line / BLn by applying 0V to the connected second bit line / BLn.

8 and 9 are diagrams for explaining the read operation of this memory cell.

Referring to FIG. 8, an operation for reading data stored in the first storage region Bit1 may include 2V at the gate electrode 60, 0V at the first junction region 52a, and 1.5V at the second junction region 52b. Is authorized.

When electrons are not stored in the first storage area Bit1 and the second storage area Bit2, the memory cell has a threshold voltage of a first level. The second storage area Bit2 is located on the depletion area of the second junction area 52b and has a low influence on the on / off of the channel area. Therefore, when electrons are stored only in the second storage area Bit2, the threshold voltage is higher than the first level, and when only electrons are stored in the first storage area Bit1, the third level is higher than the second level. Has a threshold voltage of. When electrons are stored in both the first and second storage regions Bit1 and Bit2, the threshold voltage of the fourth level is higher than the threshold voltage of the third level. When the threshold voltages of the first level, the second level, the third level, and the fourth level are provided, logic values of '00', '01', '10', and '11' are assigned to provide 2-bit data. Can be identified.

Referring to FIG. 9, the operation for reading data stored in the second storage area Bit2 is 2V at the gate electrode 60, 0V at the first junction area 52a and 1.5V at the second junction area 52b. Is authorized.

Accordingly, two bits of data can be identified by sensing a change in the threshold voltage in the read direction shown in FIG. 8 or 9, and the first storage area Bit1 and the second storage area Bit2 are read through bidirectional reading. If there are no electrons in all storage areas by sensing whether electrons are stored in the storage area, only the first storage area is stored, only the second storage area is stored, and the electrons are stored in all storage areas, respectively, '00' and '01 Logical values of ',' 10 'and' 11 'can be assigned to identify two bits of data.

10 and 11 are diagrams for describing a method of erasing data stored in the first storage area Bit1 and data stored in the second storage area Bit2, respectively.

Referring to FIG. 10, −6 V is applied to the gate electrode 60, 10 V is applied to the first junction region 52a, and 0 V is applied to the first junction region 52a to hot the first storage region Bit1. Inject holes to erase data.

Conversely, referring to FIG. 11, -6V is applied to the gate electrode 60, 0V is applied to the first junction region 52a, and 10V is applied to the first junction region 52a to the second storage region Bit2. Hot holes are injected to erase data.

Using this erase method, the memory cell array shown in Fig. 6 can erase each bit by randomly accessing the memory cells. In addition to this method, block erasing can be performed using FN tunneling or direct tunneling by dividing the memory cell array into blocks and applying an erase voltage between the substrate and the gate electrode.

The memory cell shown in FIG. 3 is characterized in that it has a charge storage layer 56 having a portion adjacent to the first junction region and a portion adjacent to the second junction region. In this case, when writing and erasing data in the first storage area Bit1 and the second storage area Bit2, write and erase disturbances may occur. The structure which can solve such a problem is the memory cell structure shown in FIG.

12 to 16 are diagrams for describing write, erase, and read operations when the memory cell array shown in FIG. 6 is configured with the memory cells shown in FIG.

12 to 16, the write, erase and read operations of this embodiment are the same as those described with reference to Figs. However, the charge storage layer of the memory cell is divided into a first portion 106a adjacent to the first junction region 102a and a second portion 106b adjacent to the second junction region 102b. Since no charge storage layer is formed on the central portion of the electrons, the electrons do not tunnel from the central portion of the channel region to the charge storage layer. Therefore, electrons are stored in the second storage area Bit2 while writing data in the first storage area Bit1, or electrons are stored in the first storage area Bit1 while writing data in the second storage area Bit2. It is also possible to have the advantage that the write disturbance that is stored does not occur.

As described above, according to the present invention, by storing the warm energy worm electrons in the charge storage layer by the direct tunneling method, the voltage applied to the memory cell can be lowered, the writing speed can be improved, and the power consumption can be reduced. .

In addition, in a cell array consisting of memory cells having an NMOS structure, since a negative voltage is applied to the bit line, bit line disturbance in which information stored in the non-selected memory cell is soft erased when a positive voltage is applied to the bit line. It can also be suppressed.

Furthermore, by separating the charge storage region into a portion adjacent to the first junction region and a portion adjacent to the second junction region, two bits of information are stored in one memory cell, so that a geometrical density of 4F2 is achieved in a cell array having a geometrical density of 8F2. Data can be saved.

Claims (10)

Semiconductor substrates; A first junction region formed on the semiconductor substrate; A second junction region formed on the semiconductor substrate spaced apart from the first junction region, and having a forward bias applied to the semiconductor substrate during a first write operation; A channel region defined in the semiconductor substrate between the first junction region and the second junction region; And And a tunnel insulating film, a charge storage layer, a control insulating film, and a control gate electrode sequentially stacked on the channel region. The method according to claim 1, And the tunnel insulating film has a thickness of 1 nm to 1.5 nm. The method according to claim 1, And a storage area in which charge is stored during the first write operation. And said storage region is a trap site of said charge storage layer near said first junction region. The method according to claim 1, And the charge storage layer is one selected from an insulating film, a semiconductor film and a conductive film. The method according to claim 1, And the charge storage layer is divided into a first portion adjacent to the first junction and a second portion adjacent to the second junction. The method according to claim 5, And said first portion and said second portion are spaced apart by an insulating film. The method according to claim 5, And a forward voltage is applied to said second junction region in a second write operation. The method according to claim 7, A first storage region in which charge is stored in the first write operation, and a second storage region in which charge is stored in the second write operation, And said first storage area is a trap site of said first portion and said second storage area is a trap site of said second portion. A cell array consisting of memory cells of any one of claims 1 to 6, A plurality of pairs of bit lines arranged in parallel; A source line disposed between the first bit line and the second bit line constituting the bit line pair; And A word line crossing the bit line pair and the source line; A plurality of memory cells are disposed between the first bit line and the source line such that second junction regions are connected to the first bit line and first junction regions are connected to the source line, A plurality of other memory cells are disposed between the second bit line and the first junction region such that second junction regions are connected to the second bit line and first junction regions are connected to the source line, And gate electrodes of the memory cells are connected to the word line, and memory cells connected to the same bit line are respectively connected to different word lines. A cell array consisting of memory cells of any one of claims 1 to 3 and 5 to 8, A plurality of parallel bitline pairs; And A plurality of word lines intersecting the bit line pair; A plurality of memory cells are disposed between the first bit line and the second bit line constituting the bit line pair, the first junction regions of the memory cells are connected to the first bit line, and the second junction regions are the second bit line. And a memory cell connected to a bit line and gate electrodes connected to the word line, wherein memory cells connected to the same bit line are connected to different word lines.

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