KR20070088922A - Semiconductor memory device for screening weak cell - Google Patents

Abstract

A semiconductor memory device is provided to improve yield and reliability of chip by screening a weak cell during a wafer test. A memory cell is connected to a pair of bit lines and a word line. A bit line sense amplifier is enabled by a sense driving voltage to amplify the potential of the bit line pair. A word line enable unit enables the word line in response to an active signal. A sense driving voltage generation unit drives the sense driving voltage after delay as long as sensing margin from the enable time of the word line during a normal mode, and drives the sense driving voltage after delay shorter than the sensing margin during a test mode.

Description

Semiconductor memory device for weak cell screens {SEMICONDUCTOR MEMORY DEVICE FOR SCREENING WEAK CELL}

1 is a block diagram illustrating a partial configuration of a low pass of a conventional memory device.

2 is a circuit diagram illustrating some components of a memory core block.

3A and 3B are circuit diagrams illustrating power supply drivers for explaining embodiments of a circuit configuration.

4 is a timing diagram illustrating a process of amplifying a general pair of bit lines.

5 is a configuration diagram illustrating a partial configuration of a low pass of a memory device according to the present invention.

6 is a circuit diagram for explaining a sense active signal generation unit according to the present invention.

7 is a timing diagram showing a sense amplifier enable time in accordance with the present invention.

* Explanation of symbols for the main parts of the drawings

620: first delay unit 640: second delay unit

660: selection unit

The present invention relates to a semiconductor memory device, and more particularly, to a semiconductor memory device for screening weak cells during wafer level testing.

Typically, after designing and manufacturing, the semiconductor memory device determines whether a chip is defective through a wafer-level test process and a post-package test process.

Wafer testing is often done in large quantities at once, such as 64 parallel or 128 parallel. In addition, since the frequency is low at the time of the test, the noise caused by the external noise or the clock intervention cannot be considered, and the test method is mainly performed by reducing the external voltage or the internal voltage.

Basically this way, most errors are screened, but so-called wick cells, where one or a few bits die due to charge sharing, become difficult to screen.

Weak cells occur as chip densities become more and more, technology becomes more and more fine, and operating power potentials become less and less.In the past, chip fail occurs because packaging the weak cells is not filtered out in wafer-level testing, resulting in increased package yield. There will be a drop.

On the other hand, in a conventional memory device, when an active command is issued by external and internal commands, a delay until a word line is enabled by row addresses and sufficient charging sharing between the right bit line and the sub bit line is achieved. The bit line sense amplifier is configured to be enabled later.

This is because after the word line is enabled, the data stored in the memory cell must be charged with the potential of the precharged bit line, and then the bit line detection amplifier must be driven to detect the correct cell data.

At this time, even if the weak cell exists, if the sensing margin time is sufficient, the weak cell does not screen and appears as a bit fail.

1 shows a partial configuration of a low pass of a conventional memory device.

Referring to FIG. 1, a word line driver 120 for activating a word line in response to an active signal ACT and an application of sense driving power (that is, power to RTO and SB) are enabled. A bit line sense amplifier 140 for amplifying a potential of a pair of bit lines, and a sense drive power generation unit 160 for driving the sense drive power after a delay of a sensing margin time from an activation time of the word line. It is configured to include.

The sense driving power generator 160 may generate a sense active signal sa_act in response to the active signal ACT, and a power driver 166 in response to the sense active signal sa_act. A control unit 164 for generating a control signal sap, san, and a power driver 166 for supplying driving power to the power lines RTO, SB of the sense amplifier in response to the control signals sap, san. do.

Detailed circuit configurations of the word line driver 120 and the controller 164 are well known and thus will not be described in detail herein. However, detailed circuit embodiments of the sense active signal generator 162, the power driver 166, and the bit line sense amplifier 140 which are closely related to the present invention will be described.

The sense active signal generator 162 generates an activated sense active signal sa_act after a predetermined time delay from the activation time of the word line based on the active signal ACT, that is, after the sensing margin time, and generates the sensing margin time. Delay elements to obtain.

2 illustrates some components of a memory core block, memory cells 210 connected to a pair of bit lines BL and / BL and a word line WL, and switching elements 220 for bit line separation. ), A block 230 for precharging and equalizing bit lines, and a latch type bit line sense amplifier 240 connected between a pull-up driving power line RTO and a pull-down driving power line SB. .

3A and 3B show embodiments of the circuit configuration of the power driver 166.

3A and 3B, power voltages VCORE and VDDCLP are supplied to the pull-up driving power line RTO by the control signals sap and san output from the controller 164 and the pull-down driving power line SB. ) Is supplied with the ground voltage VSSA. An overdriving scheme may be applied at an early stage of enabling the sense amplifier. FIG. 3A illustrates a case where an overdriving scheme is applied.

4 is a timing diagram illustrating a process of amplifying a pair of bit lines in the memory device as described above. This is the case when an overdriving scheme is applied.

As mentioned above, when the active command ACT is issued by external and internal commands, the word line WL selected by the row address is enabled as logic 'high' (t1), thereby equalizing. And the potential difference between the pre-charged positive bit line BL and the sub bit line / BL is generated according to the data value stored in the memory cell. After the word line is enabled and delayed by the sensing margin time (i.e., t2-t1), if the control signals sap1 and san are activated at logic high at time t2, the pull-up driving power line RTO The voltage rises gradually to the clamp voltage VDDCLP and the pull-down drive power line SB gradually falls to the ground voltage VSSA. When the control signal sap1 becomes logic 'low' at time t3 and the control signal sap2 becomes logic 'high', the voltage of the pull-up driving voltage terminal RTO becomes the core voltage VCORE. .

As described above, since the sensing margin time t2-t1 is set in the conventional memory device, the time set during the wafer test, as described above, can only be used during the wafer test screen. Therefore, even if a weak cell is present, it is not filtered and packaged in a wafer level test, so that the package is packaged in a state where a 1-bit or a few-bit fail occurs finally. Redundancy cells can not be replaced, causing problems in yield and chip reliability.

SUMMARY OF THE INVENTION The present invention has been proposed to solve the above problems of the prior art, and provides a semiconductor memory device for screening a weak cell during wafer testing to improve yield and chip reliability. There is a purpose.

The present invention for achieving the above object is a memory cell connected to a pair of bit lines and word lines; A bit line sense amplifier which is enabled by application of a sense driving power source and amplifies the potential of the pair of bit lines; Means for activating the word line in response to an active signal; And driving the sense driving power after a delay of a sensing margin time from an activation time of the word line in a normal mode, and a value smaller than the sensing margin time from an activation time of the word line in a test mode for a weak cell screen. A semiconductor memory device comprising a sense drive power generation means for driving the sense drive power after a delay.

Hereinafter, the most preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art can easily implement the technical idea of the present invention. .

5 is a partial configuration of a low path of a memory device showing a characteristic configuration of the present invention.

Referring to FIG. 5, a memory cell 510 connected to a pair of bit lines and a word line, and a bit line sense amplifier 520 for enabling amplification of the potential of the pair of bit lines by being enabled by application of a sense driving power source. And a word line driver 530 for activating the word line WL in response to an active signal ACT, and driving the sense driving power after a delay of a sensing margin time from an activation time of the word line in normal mode. And a sense driving power generator 540 for driving the sense driving power after a delay having a value less than the sensing margin time from the time of activation of the word line in a test mode for the weak cell screen.

The sense driving power generation unit 540 responds to the sense active signal generation unit 542 generating the sense active signal sa_act in response to the active signal ACT and the test signal PT, and the sense active signal sa_act. Control unit 544 for generating control signals sap and san, and power driver 546 for supplying sense driving power to the RTO line and the SB line in response to the control signal control signals sap and san. ).

As described above with reference to FIGS. 3A and 3B, the power driver 546 may be applied with an overdriving scheme at an early stage of enabling the sense amplifier, and the bit line sense amplifier 520 may be a pull-up driving power line (RTO) and a pull-down driving. It consists of a latch type sense amplifier connected between the power lines (SB).

The detailed technical configuration (circuit configuration) of the word line driver 530 and the controller 542 is as known to those skilled in the art.

A characteristic configuration of the present invention is a sense active signal generation unit 542 for generating a sense active signal sa_act, so that the sense active signal generation unit 542 is driven by being controlled by the test signal PT, and also during normal driving. In order to shorten the sensing margin time (charge sharing time) during the test, the active signal is generated with a different active time (shortened) as the control of the test signal PT.

6 shows a detailed circuit configuration of the sense active signal generation unit 542.

Referring to FIG. 6, the sense active signal generator 542 generates a first sense active signal sa_act_int1 activated after a predetermined time delay from an activation time of the word line in response to an active signal. And a second delay unit for generating an activated second sense active signal sa_act_int2 after delaying the output of the first delay unit 620 by a sensing margin time from an activation time of the word line WL. 640 and in response to the test signal PT, the second sense active signal sa_act_int2 is selected in the normal mode, and the first sense active signal sa_act_int1 is selected in the test mode and output as the sense active signal sa_act. And a selector 660. Substantially, the signal int input to the first delay unit 620 is an internal signal based on the active signal.

The selector 660 may include a NAND gate NAND2 receiving the first sense active signal sa_act_int1 and the test signal PT, a first inverter INV4 for inverting an output signal of the NAND gate NAND2, and A second NOR gate NOR2 receiving the output signal of the second sense active signal sa_act_int2 and the first inverter INV4, and an output signal of the NOR gate NOR2, and outputting the sense active signal sa_act. It consists of an inverter INV5.

Meanwhile, the first delay unit 620 includes a plurality of inverters connected in series for generating different delay times, and includes a fuse unit for selecting and outputting any one of the outputs of the respective inverters by fuse blowing. Can be. In addition, it may include an option processing unit for selecting any one of the output of each inverter by the metal option processing.

7 is a timing diagram illustrating a sense amplifier enable timing according to the present invention. This is the case when an overdriving scheme is applied. Referring to FIG. 7, an operation of a memory device according to the present invention will be described.

When the active command ACT is issued by external and internal commands, the word line WL selected by the row address is enabled with logic 'high' (t1), thereby maintaining the equalized and precharged maintenance. The potential difference of the line BL and the sub bit line / BL starts to occur according to the data value stored in the memory cell.

When the test signal PT is activated with logic 'high', the control signals sap1 and san are activated with logic 'high' at the time t2 by the first sense active signal sa_act_int1 and the bit line sense amplifier is enabled. As a result, the potential of the bit line pair is amplified.

On the other hand, when the test signal PT is deactivated to logic 'low' (that is, in the normal mode), the control signal sap1 at the time t2 by the second sense active signal sa_act_int2 output from the second delay unit 640. , san) is activated as logical 'high'.

As a result, the present invention allows the charge sharing time to be shortened during the test unlike the normal driving under the control of the test signal (that is, to shorten the sensing margin time after the word line is activated until the sense amplifier is disabled). You can test screen the cell.

Although the technical idea of the present invention has been described in detail according to the above preferred embodiment, it should be noted that the above-described embodiment is for the purpose of description and not of limitation. In addition, those skilled in the art will understand that various embodiments are possible within the scope of the technical idea of the present invention.

The present invention described above can perform a test by reducing the sensing margin time (charge sharing time of the bit line), so that the weak cell can be screened and the weak cell filtered during the test screen is redundant. ) And can be packaged, resulting in an improvement in yield and chip reliability.

Claims (8)

Memory cells connected to a pair of bit lines and word lines; A bit line sense amplifier which is enabled by application of a sense driving power source and amplifies the potential of the pair of bit lines; Means for activating the word line in response to an active signal; And In the normal mode, the sensing driving power is driven after the delay of the sensing line time from the activation time of the word line, and in the test mode for the weak cell screen, the delay is less than the sensing margin time from the activation time of the word line. And a sense drive power generation means for driving the sense drive power thereafter. A semiconductor memory device having a. The method of claim 1, The sense drive power generating means, Sense active signal generation means for generating a sense active signal in response to the active signal and the test signal; Control means for generating a control signal of the bit line sense amplifier in response to the sense active signal; A power driver driving the sense driving power in response to the control signal A semiconductor memory device comprising a. The method of claim 2, The sense active signal generating means A first delay unit configured to generate an activated first sense active signal after a predetermined time delay from an activation time of the word line in response to the active signal; A second delay unit configured to delay an output of the first delay unit to generate an activated second sense active signal after a delay of a sensing margin time from an activation time of the word line; A selection unit for selecting the second sense active signal in the normal mode and the first sense active signal in the test mode and outputting the output power as the sense active signal in response to the test signal; A semiconductor memory device comprising a. The method of claim 3, The selection unit, A NAND gate configured to receive the first sense active signal and the test signal; A first inverter for inverting an output signal of the NAND gate; A NOR gate configured to receive the second sense active signal and the output signal of the first inverter; And A second inverter outputting the sense active signal by inverting the output signal of the NOR gate A semiconductor memory device comprising a. The method of claim 3, The first delay unit includes a plurality of inverters connected in series for generating different delay times; And And a fuse unit configured to select and output any one of the outputs of the respective inverters by fuse blowing. The method of claim 3, The first delay unit includes a plurality of inverters connected in series to generate different delay times; And And an option processor which selects and provides any one of the outputs of the respective inverters by the metal option process. The method of claim 1, The bit line sense amplifier And a latch type sense amplifier connected between a pull-up drive power line and a pull-down drive power line. The method of claim 7, wherein The control means And overdriving the pull-up driving power supply line at an initial stage of enabling sense amplifier.

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