JP3815712B2 - Semiconductor memory device and wafer test method thereof - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor memory device and a wafer test method thereof, and more particularly to a semiconductor memory device and a wafer test method thereof that can be tested by an easy method.
[0002]
[Prior art]
Conventionally, in order to adjust the delay signal for controlling the operation timing of the internal circuit constituting the semiconductor memory device, as disclosed in, for example, Japanese Patent Application Laid-Open No. 2-91900 and Japanese Patent Application Laid-Open No. A method for changing a voltage level input from an input terminal is known.
[0003]
An example of a method for adjusting the delay time by changing the voltage level input from the external input terminal will be described with reference to FIG. FIG. 6 is a block diagram for explaining a schematic configuration of a conventional SRAM.
[0004]
This semiconductor memory device includes an input buffer circuit / control signal circuit 100, an ATD (address transition detector) generation circuit 200, a row / column decoder circuit 300, a delay circuit (timing circuit) 400, a memory cell array 500, a sense An amplifier circuit 600, an output buffer circuit 700, and a delay time adjustment circuit 800 are provided, and these are connected to the power supply terminal Vcc.
[0005]
When an address is input to the semiconductor memory device, an address change is input from the input buffer circuit 100 to the ATD generation circuit 200 via the node 1, and the ATD generation circuit 200 signals that the address has changed (ATD signal). Is generated. The ATD signal is input to the delay circuit 400 via the node 2, and the delay circuit 400 generates a delay signal from the ATD signal. The delayed signal is input to the sense amplifier circuit 600 through the node 3 and is output to the output buffer circuit 700 through the node 4.
[0006]
As the control signal system input, for example, a CE (chip enable) input, an OE (output enable) input, or the like is input. In the case of the OE input, a control signal generated by the control signal circuit 100 is output via the node 7 to the output buffer circuit. And the output buffer circuit 700 is controlled.
[0007]
The address information output from the input buffer circuit 100 is input to the row / column decoder circuit 300 via the node 8, and after the row signal and column signal are generated, the address information is input to the memory cell array 500 via the node 9. .
[0008]
The memory cell array 500 includes a plurality of memory cells. A memory cell that matches the row signal and the column signal generated by the row / column decoder 300 is selected, and the memory cell information is read out via the node 11. And input to the sense amplifier 600.
[0009]
The sense amplifier 600 determines “0” or “1” based on the memory cell information, which is input to the output buffer 700 via the node 12, and data is output from the output buffer 700.
[0010]
The delay time adjustment circuit 800 is provided for adjusting the delay time, and generates an adjustment signal according to the voltage level supplied from the external input terminal via the node 5. By inputting this adjustment signal to the delay circuit 400 via the node 6, the timing of the delay signal is adjusted.
[0011]
FIG. 7 is a circuit diagram for explaining the read operation of the SRAM. Here, the bit line precharge circuit 10, the memory cell 20, and the sense amplifier circuit 30 are shown. The precharge circuit 10 is provided for precharging the potentials of the bit lines BL and BL bar to the Vcc level while the equalize signal EQ1 is at the Lo level. FIG. 8 is a waveform diagram for explaining the operation timing of FIG. 7 and the potential change of the bit lines BL and BL bar. Here, the description will be made on the assumption that the GND level (0 V) is written in the node N1 of the memory cell 20 and the Vcc level (Vcc) is written in the node N2, and data “0” is read out.
[0012]
At time t0 in FIG. 8, the equalization signals EQ1 and EQ2 applied from the delay circuit to the bit line precharge circuit 10 and the sense amplifier circuit 30 are enabled (Lo level), so that the bit lines BL and BL are changed from t0 to t3. Time is precharged to the Vcc level.
[0013]
At time t3, the word line drive signal WL applied from the row / column decoder to the memory cell 20 rises to a high level and becomes conductive when the transistors Q1 and Q2 of the memory cell 20 reach the threshold voltage VthN. 20, data stored in inverters I1 and I2 is read out to bit lines BL and BL bar.
[0014]
At this time, the bit line BL is precharged to the Vcc level by the precharge circuit 10, but since the node N1 of the memory cell 20 is at the GND level (0 V), the potential of the bit line BL decreases due to charge transfer. On the other hand, since the node N2 of the memory cell 20 is at the Vcc level (Vcc), the bit line BL bar holds the precharged Vcc level. The bit line potential lowering speed is determined by the drive current capability of the Nch transistor constituting the inverter I2 and the junction capacitance connected to the bit line BL. Therefore, the bit line potential lowering speed is relatively slow. .
[0015]
Next, at time t4, the sense amplifier drive signal (sense start signal) SAE given from the delay circuit to the sense amplifier circuit 30 becomes High level, and the sense amplifier circuit 30 starts the sensing operation. The sense amplifier circuit 30 compares the potential levels of the bit lines BL and BL bar, and in this example, the GND level is output to the sense amplifier output SAOUT.
[0016]
[Problems to be solved by the invention]
In the sense amplifier circuit 30 described above, in order to perform a stable read operation, it is desirable to start the sense operation when the potential of the bit line BL decreases as much as possible. However, if the start time of the sense operation is delayed, there is a problem that the operation speed (access time) of the SRAM is delayed. On the other hand, when the start time of the sensing operation is early, the operation of the sense amplifier circuit 30 may become unstable and malfunction may occur.
[0017]
The limit point of time for preventing the sense amplifier circuit 30 from malfunctioning varies depending on the order of access and the combination of data written in the memory cell 20, and it is difficult to accurately calculate and obtain the limit point. . For this reason, the start time of the sensing operation is normally set to a time later than the limit point obtained from a prototype experiment or the like.
[0018]
However, as the capacity of a semiconductor memory device is increased, a defect occurs in a memory cell due to dust or the like mixed during manufacture, and the cell current is reduced due to a decrease in transistor capability in one or more memory cells in the memory cell array. It is conceivable that the potential decrease rate of the bit line BL decreases. As a result, the limit point for the normal operation of the sense amplifier is also delayed.
[0019]
As described above, if the limit point at which the sense amplifier operates normally is later than the start time of the sense operation in the chip having the memory cell at which the limit point at which the sense amplifier operates normally is delayed, the chip is Since it does not operate normally, it can be removed by wafer test. However, when the limit point at which the sense amplifier normally operates is earlier than the start time of the sense operation, the wafer operates normally in the wafer test and cannot be removed by the wafer test.
[0020]
In such memory cells, the limit point for normal operation of the sense amplifier is located in the vicinity of the start time of the sense operation, so the sense operation becomes unstable, and even if it becomes a non-defective product in the wafer test, the second half test after assembly It may become defective.
[0021]
Further, when the transistor is deteriorated due to a stress such as burn-in performed to remove the initial failure, the cell current is decreased due to a decrease in transistor capability or an increase in contact resistance, and the potential decrease of the bit line BL is further delayed. . For this reason, the limit point at which the sense amplifier normally operates becomes later than the start time of the sense amplifier, and a defect occurs.
[0022]
As described above, when an abnormal memory cell exists in the chip, there is a problem in that it affects the yield of the latter half process and the reliability of the device. Therefore, it is important to remove in advance at the wafer stage a chip having a memory cell (limit memory cell) at which the limit point at which the sense amplifier normally operates is delayed.
[0023]
Usually, since the start time of the sense operation is designed with a margin, the chip having the abnormal memory cell as described above can be removed as a defective product by the wafer test by increasing the start time of the sense operation. it can.
[0024]
Conventionally, a method of adjusting a delay time by changing a voltage level input from an external input terminal is used. However, this method requires the delay time adjustment circuit 800 as shown in FIG. 6 and increases the layout area.
[0025]
The present invention has been made to solve such problems of the prior art, and can adjust a delay time without increasing a layout area and remove a chip having an abnormal memory cell by a wafer test. An object of the present invention is to provide a semiconductor memory device and a wafer test method thereof.
[0026]
[Means for Solving the Problems]
According to another aspect of the semiconductor memory device of the present invention, in the semiconductor memory device including a delay circuit that generates a delay signal and controls the operation timing of the internal circuit, a second power supply terminal that supplies a voltage to the delay circuit includes the semiconductor memory device. It is provided separately from the first power supply terminal for supplying a voltage to other circuits constituting the device, thereby achieving the above object.
[0027]
The semiconductor memory device of the present invention includes an ATD generation circuit that generates an ATD signal and notifies a change in an address input from the outside, and has a second power supply terminal that supplies a voltage to the ATD generation circuit. The semiconductor memory device is provided separately from the first power supply terminal for supplying a voltage to the other circuits constituting the semiconductor memory device, thereby achieving the above object.
[0028]
It is preferable that the first power supply terminal and the second power supply terminal are arranged adjacent to each other in the chip.
[0029]
The semiconductor memory device of the present invention can be configured to include an input buffer circuit, a control signal circuit, an ATD generation circuit, a row / column decoder circuit, a delay circuit, a memory cell array, a sense amplifier circuit, and an output buffer circuit.
[0030]
A wafer test method for a semiconductor memory device according to the present invention is a method for testing the semiconductor memory device according to the present invention at a wafer stage, and is output from a delay circuit by changing a voltage supplied to the second power supply terminal. An operation test is performed by adjusting the pulse width of the delay signal to detect abnormal memory cells, thereby achieving the above object.
[0031]
The voltage supplied to the second power supply terminal can be higher than the voltage supplied to the first power supply terminal.
[0032]
The operation of the present invention will be described below.
[0033]
In the present invention, the delay circuit or the ATD generation circuit is provided with a power supply terminal (second power supply terminal) different from other circuits, and the pulse width of the delay signal is adjusted according to the power supply voltage. During the wafer test, the power supply voltage supplied to the power supply terminal (second power supply terminal) of the delay circuit or the ATD generation circuit is set higher than the power supply voltage supplied to the power supply terminal (first power supply terminal) of another circuit. By doing so, the pulse width of the delay circuit can be shortened.
[0034]
Normally, the start time of the sense operation is set with a margin in the delay circuit, so in a chip that does not have an abnormal memory cell, the pulse width of the delay circuit is slightly shortened and the start time of the sense operation is advanced. Also works fine and passes the wafer test. However, in a chip having an abnormal memory cell, the sense operation start time is earlier than the limit point at which the sense amplifier normally operates. Therefore, the chip does not operate normally in the wafer test and can be removed at the wafer stage.
[0035]
The power supply terminal (second power supply terminal) of the delay circuit or ATD terminal and the power supply terminal (first power supply terminal) of another circuit are arranged adjacent to each other in the chip, and the power supply terminals are wired to each other in the second half process. By connecting to the lead frame by bonding, it can be used as a semiconductor memory device having a single power supply as usual.
[0036]
DETAILED DESCRIPTION OF THE INVENTION
(Embodiment 1)
FIG. 1 is a block diagram for explaining a schematic configuration of an SRAM which is an embodiment of a semiconductor memory device of the present invention. Here, a read operation of the SRAM will be described.
[0037]
This semiconductor memory device includes an input buffer circuit / control signal circuit 100, an ATD (address transition detector) generation circuit 200, a row / column decoder circuit 300, a delay circuit (timing circuit) 400, a memory cell array 500, a sense An amplifier circuit 600 and an output buffer circuit 700 are provided. In the present embodiment, a delay circuit 400 is connected to the power supply terminal Vcc2, and a circuit other than the delay circuit is connected to the power supply terminal Vcc1.
[0038]
When an address is input to the semiconductor memory device, an address change is input from the input buffer circuit 100 to the ATD generation circuit 200 via the node 1, and the ATD generation circuit 200 signals that the address has changed (ATD signal). Is generated. The ATD signal is input to the delay circuit 400 via the node 2, and the delay circuit 400 generates a delay signal from the ATD signal. A sense start signal (SAE signal) is input to the sense amplifier circuit 600 via the node 3. A signal for controlling the output buffer circuit 700 is input to the output buffer circuit 700 via the node 4.
[0039]
Information of the memory cell designated by the row / column decoder circuit 300 is read from the memory cell array 500 and compared by the sense amplifier circuit 600, and the latched data is output from the output buffer circuit 700.
[0040]
The operation of the bit lines BL and BL bar will be described below with reference to FIG. 2 and FIG. 7 described above when one bit or a plurality of bits are defective in the memory cell array 500.
[0041]
At time t10 in FIG. 2, the bit lines BL and BL bar are precharged to the Vcc level (Vcc1). Here, assuming that data “0” is written in the memory cell 20 of FIG. 7, when the word line driving signal WL rises at time t10 of FIG. 2, the node N1 of the memory cell 20 of FIG. Therefore, the charge transfer occurs through the transistor Q1, and the potential of the bit line BL decreases. On the other hand, since the node N2 of the memory cell 20 in FIG. 7 is at the Vcc level, the potential of the bit line BL bar maintains the precharge level.
[0042]
In the case of a normal memory cell, the potential of the bit line BL is lowered as shown by characteristic (1) in FIG. 2, but in the case of an abnormal memory cell, the cell current capability is reduced. Characteristic (2) is obtained, and the rate of decrease of the bit line potential is slower than that of characteristic (1). The limit point at which the sense amplifier operates normally is time t12 in the case of a normal memory cell, and time t13 in an abnormal memory cell.
[0043]
Usually, the start time of the sense operation is designed with a margin, and the sense amplifier starts the operation at time t11. However, in this case, since the sense operation start time t11 is later than the limit point t13 at which the sense amplifier of the abnormal memory cell operates normally, the abnormal memory cell passes the test.
[0044]
In order to remove a chip having such an abnormal memory cell at the wafer test stage, for example, the start time of the sensing operation is set at time t14. As a result, the sense amplifier of the abnormal memory cell becomes earlier than the limit point t13 at which normal operation is performed, so that a defect can be detected by the test.
[0045]
Therefore, in the present embodiment, the sense start signal generated by the delay circuit 400 is set by setting the voltage of the power supply terminal Vcc2 for the delay circuit shown in FIG. 1 higher than the voltage of the power supply terminal Vcc1 for other circuits. SAE is started earlier than when the power supply terminals Vcc1 and Vcc2 are at the same potential. As a result, the start time of the sensing operation can be set from time t11 to time t14, and an abnormal memory cell can be detected as defective by the wafer test. In addition, since the start time of the sensing operation can be arbitrarily changed according to the power supply voltage of the power supply terminal Vcc2, various abnormal memory cells can be detected.
[0046]
Hereinafter, how the delay signal changes depending on the power supply voltage applied to the delay circuit will be described with reference to FIGS. 3 and 4. FIG.
[0047]
In general, the delay circuit generates a delay signal by an inverter delay as shown in FIG.
[0048]
In FIG. 3, for example, when the power supply voltage of the power supply terminal Vcc2 for the delay circuit is 3.3V, and the ATD signal generated by the power supply voltage 3.3V from the power supply terminal Vcc1 by the ATD generation circuit is input to the delay circuit, The equalize signal EQ generated and output by the delay circuit (given as EQ1 and EQ2 shown in FIG. 7 to the precharge circuit 10 and the sense amplifier circuit 30 as EQ1 and EQ2 in FIG. 7) and the sense start signal SAE are As shown in the waveform b of FIG.
[0049]
In FIG. 3, for example, when the power supply voltage of the power supply terminal Vcc2 for the delay circuit is 3.6V, the drive current capability of the transistors constituting the inverter is higher than when the power supply voltage is 3.3V. Therefore, the sense start signal SAE generated and output by the delay circuit is earlier by Δt than the case where the power supply voltage of the power supply terminal Vcc2 is 3.3 V as shown by the waveform a in FIG.
[0050]
Further, in FIG. 3, for example, when the power supply voltage of the power supply terminal Vcc2 for the delay circuit is set to 3.0V, the drive current capability of the transistors constituting the inverter becomes lower than when the power supply voltage is set to 3.3V. Therefore, the sense start signal SAE generated and output by the delay circuit is delayed by Δt as compared with the case where the power supply voltage of the power supply terminal Vcc2 is 3.3 V as shown by the waveform c in FIG. In FIG. 4, the pulse width of the equalize signal EQ also changes. When the EQ pulse width is shortened, the bit line may become insufficiently precharged. Even if the width changes slightly, no problem occurs and the circuit operation does not change.
[0051]
As described above, according to the present embodiment, the external input terminal and the delay time adjusting circuit are not required as in the prior art, and the power supply voltage applied to the delay circuit is changed to change the setting of the start time of the sensing operation. An abnormal memory cell can be detected, and a defect can be detected and removed by an easy method in a wafer test.
[0052]
(Embodiment 2)
FIG. 5 is a block diagram for explaining a schematic configuration of an SRAM which is an embodiment of the semiconductor memory device of the present invention. Here, a read operation of the SRAM will be described.
[0053]
This semiconductor memory device includes an input buffer circuit / control signal circuit 100, an ATD (address transition detector) generation circuit 200, a row / column decoder circuit 300, a delay circuit (timing circuit) 400, a memory cell array 500, a sense An amplifier circuit 600 and an output buffer circuit 700 are provided. In the present embodiment, the ATD generation circuit 200 is connected to the power supply terminal Vcc2, and circuits other than the ATD generation circuit are connected to the power supply terminal Vcc1.
[0054]
When an address is input to the semiconductor memory device, an address change is input from the input buffer circuit 100 to the ATD generation circuit 200 via the node 1, and the ATD generation circuit 200 signals that the address has changed (ATD signal). Is generated. The ATD signal is input to the delay circuit 400 via the node 2, and the delay circuit 400 generates a delay signal from the ATD signal. A sense start signal (SAE signal) is input to the sense amplifier circuit 600 via the node 3.
[0055]
Information of the memory cell designated by the row / column decoder circuit 300 is read from the memory cell array 500 and compared by the sense amplifier circuit 600, and the latched data is output from the output buffer circuit 700.
[0056]
In the first embodiment, the setting of the sense start signal SAE is changed by changing the power supply voltage applied to the delay circuit. However, in this embodiment, the power supply voltage applied to the ATD generation circuit is changed and input to the delay circuit. By changing the pulse width of the ATD signal, the equalize signal and the sense start signal generated by the delay circuit are changed.
[0057]
Hereinafter, how the delay signal changes depending on the power supply voltage applied to the ATD generation circuit will be described with reference to FIGS.
[0058]
FIG. 10 shows an example of an ATD generation circuit. An ATD pulse is generated and output by a change in input (IN).
[0059]
In FIG. 11, for example, when the power supply voltage of the power supply terminal Vcc2 for the ATD generation circuit is 3.3 V and the power supply voltage of the power supply terminal Vcc1 for the delay circuit is 3.3 V, the ATD signal generated by the ATD generation circuit is as shown in FIG. 12 waveform b is input to the delay circuit.
[0060]
When the ATD signal is input to the delay circuit, the delay circuit generates an equalize signal EQ and a sense start signal SAE as shown by the waveform b in FIG. 12, and outputs the signal from the delay circuit.
[0061]
In FIG. 11, for example, when the power supply voltage of the power supply terminal Vcc2 for the ATD generation circuit is 3.6 V, the drive current capability of the transistors constituting the inverter is higher than when 3.3 V is used. Therefore, the ATD signal generated and output by the ATD generation circuit has a pulse width shorter than that of the waveform b as shown by the waveform a in FIG. 12, and the equalization signal EQ and the sense start signal SAE output from the delay circuit are also obtained. Similarly, the pulse width is faster by Δt than the waveform b as shown by the waveform a in FIG.
[0062]
Further, in FIG. 11, for example, when the power supply voltage of the power supply terminal Vcc2 for the ATD generation circuit is set to 3.0V, the drive current capability of the transistors constituting the inverter is lower than when 3.3V is used. Therefore, the ATD signal generated and output by the ATD generation circuit has a longer pulse width than the waveform b as shown by the waveform c in FIG. 12, and the equalization signal EQ and the sense start signal SAE output from the delay circuit are also generated. Similarly, the pulse width is delayed by Δt compared to the waveform b as shown by the waveform c in FIG.
[0063]
In FIG. 13, the pulse width of the equalize signal EQ also changes. If the EQ pulse width is shortened, the bit line may become insufficiently precharged. Even if the width changes slightly, no problem occurs and the circuit operation does not change.
[0064]
As described above, according to the present embodiment, the setting of the start time of the sensing operation is changed by changing the power supply voltage applied to the ATF generation circuit without requiring an external input terminal or a delay time adjustment circuit as in the prior art. Can detect abnormal memory cells and
Although the first embodiment and the second embodiment have described the SRAM, the present invention can similarly adjust the delay time for a semiconductor memory device other than the SRAM (for example, a delay circuit in a mask ROM or DRAM).
[0065]
Further, in the wafer test, a delay signal can be set according to the power supply voltages of the power supply terminals Vcc1 and Vcc2. In the latter half of the process, the power supply terminals Vcc1 and Vcc2 are connected to the lead frame by wire bonding so that they can be used as a single power supply as usual. In this case, the power supply terminals Vcc1 and Vcc2 are preferably arranged adjacent to each other in the chip.
[0066]
【The invention's effect】
As described above in detail, according to the present invention, a chip having an abnormal memory cell can be removed by a wafer test. Therefore, the yield of the second half test can be improved and the reliability of the device can be improved. In addition, since the delay time can be adjusted by the voltage of the power supply terminal for the delay circuit or the ATD generation circuit, an external input terminal, a delay time adjusting circuit and the like are not required as in the prior art. Therefore, the layout area can be reduced with a simple circuit configuration.
[Brief description of the drawings]
FIG. 1 is a block diagram for explaining a schematic configuration of an SRAM according to a first embodiment;
FIG. 2 is a timing chart for explaining timings of bit lines and sense operations;
FIG. 3 is a diagram for explaining adjustment of a delay time according to a power supply voltage of a delay circuit in the first embodiment.
FIG. 4 is a timing chart for explaining a change in delay time when the power supply voltage applied to the delay circuit is changed.
FIG. 5 is a block diagram for explaining a schematic configuration of an SRAM according to a second embodiment;
FIG. 6 is a block diagram for explaining a schematic configuration of a conventional SRAM;
FIG. 7 is a circuit diagram for explaining data reading from an SRAM;
FIG. 8 is a timing chart for explaining the timing of SRAM data read operation;
FIG. 9 is a circuit diagram showing an example of a delay circuit.
FIG. 10 is a circuit diagram showing an example of an ATD generation circuit.
FIG. 11 is a diagram for explaining adjustment of a delay time according to a power supply voltage of an ATD generation circuit according to the second embodiment.
FIG. 12 is a timing chart for explaining a change in delay time when the power supply voltage applied to the ATD generation circuit is changed.
[Explanation of symbols]
1, 2, 3, 4, 5, 6, 7, 8, 9, 11, 12 nodes
10 Precharge circuit
20 memory cells
30 sense amplifier circuit
100 Input buffer circuit / control signal circuit
200 ATD generation circuit
300 Row / column decoder circuit
400 Delay circuit (timing circuit)
500 memory cell array
600 sense amplifier circuit
700 Output buffer circuit
800 Delay time adjustment circuit
ATD ATD signal
BL, BL bar Bit line
EQ, EQ1, EQ2 Equalize signal
I1, I2 inverter
N1, N2 nodes
Q1, Q2 transistors
SAE sense start signal
SAOUT Sense amplifier output
Vcc, Vcc1, Vcc2 power supply terminals
WL Word line control signal

Claims (5)

A plurality of memory cells arranged in a matrix, and a memory cell array in which data stored in each of the plurality of memory cells is read by a pair of bit lines;
A row / column decoder for selecting each of the plurality of memory cells in the memory cell array;
A sense amplifier circuit for determining data of the memory cell selected by the row / column decoder based on a potential level of the pair of bit lines;
An output buffer for outputting data determined by the sense amplifier circuit to the outside;
An input buffer circuit to which an address for selecting the memory cell and a control signal of the output buffer circuit are input;
An ATD (address transition detector) generating circuit for outputting a predetermined signal according to a change in an address input to the input buffer circuit;
A delay circuit that delays an operation start time of the sense amplifier circuit by the predetermined signal output from the ATD generation circuit;
A first power supply is provided to supply a first power supply voltage to the memory cell array, the row / column decoder, the sense amplifier circuit, the output buffer, the input buffer circuit, and the ATD generation circuit. A semiconductor memory device comprising a chip having a power supply terminal of
The chip is provided with a second power supply terminal for supplying a second power supply voltage to the delay circuit;
2. A semiconductor memory device according to claim 1, wherein an operation start delay time in the sense amplifier circuit is adjusted by a change in the second power supply voltage. A plurality of memory cells arranged in a matrix, and a memory cell array in which data stored in each of the plurality of memory cells is read by a pair of bit lines;
A row / column decoder for selecting each of the plurality of memory cells in the memory cell array;
A sense amplifier circuit for determining data of the memory cell selected by the row / column decoder based on a potential level of the pair of bit lines;
An output buffer for outputting data determined by the sense amplifier circuit to the outside;
An input buffer circuit to which an address for selecting the memory cell and a control signal of the output buffer circuit are input;
An ATD (address transition detector) generating circuit for outputting a predetermined signal according to a change in an address input to the input buffer circuit;
A delay circuit that delays an operation start time of the sense amplifier circuit by the predetermined signal output from the ATD generation circuit;
A first power supply is provided for supplying a first power supply voltage to the memory cell array, the row / column decoder, the sense amplifier circuit, the output buffer, the input buffer circuit, and the delay circuit . A semiconductor memory device constituted by a chip having a power supply terminal,
The chip is provided with a second power supply terminal for supplying a second power supply voltage to the ATD generation circuit ,
2. A semiconductor memory device according to claim 1, wherein an operation start delay time in the sense amplifier circuit is adjusted by a change in the second power supply voltage. The semiconductor memory device according to claim 1 or claim 2, wherein said first power supply terminal and the second power supply terminal is located adjacent within the chip. A method for testing the semiconductor memory device according to claim 1 at a wafer stage,
Supplies the first power supply voltage to the first power supply terminal, the second power supply voltage so that the potential difference which is preset for the first power supply voltage to the second power supply terminal In the supplied state, an address is input to the input buffer, the memory cell is selected according to the address, and the selected data is selected based on whether the data of the memory cell is output from the output buffer. A method for wafer test of a semiconductor memory device, wherein an abnormality of the memory cell is detected . 5. The wafer test method for a semiconductor memory device according to claim 4 , wherein the second power supply voltage supplied to the second power supply terminal is set to a higher potential than the first power supply voltage .

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