KR20070084787A - Shielding method of coupling noise at sense amplifier - Google Patents

Abstract

A method for preventing a coupling noise in an amplifying circuit is provided to improve a sensing voltage margin and to reduce the size of a cell by removing a coupling noise in a sensor amplifier without increasing a layout area by using a shield plug and a dual layer. A method for preventing a coupling noise in an amplifying circuit includes the step of: using at least one of a method which forms a sensing line into a dual layer and a method which forms a shield plug between the sensing lines of a sensor amplifier terminal. A top cell array and a bottom cell array share a sensor amplifier commonly. A bit line(BL) and a bit line bar(/BL) on the cell array, and both amplifying terminals of the sensor amplifier are composed of the same material using the same layer process. The shield plug is formed between the bit line(BL) and the bit line bar(/BL) so that a coupling capacitance does not exist between the bit line(BL) and the bit line bar(/BL).

Description

Shielding method of coupling noise at sense amplifier

1 is a block diagram of a cell array and sensing associated with the prior art,

2 is a block circuit diagram related to a sense amplifier used in the prior art,

3 is a timing diagram illustrating a conventional cell array and sensing related operation;

4 is a diagram showing a conventional cell array and sense amplifier array layout configuration;

5 is a cross-sectional view of a sense amplifier amplifier stage layer of the prior art,

6 is a diagram illustrating a shield plug configuration in a cell array and sense amplifier array layout according to a first embodiment of the present invention;

7 is a cross-sectional configuration diagram of the shield plug and the shield layer in the cross-sectional configuration of the sense amplifier amplifier stage layer of the present invention;

8 is a cross-sectional configuration of the dual layer in the cross-sectional configuration of the sense amplifier amplifier stage layer according to the second embodiment of the present invention,

9 is a cross-sectional configuration diagram of a dual layer and a dual shield layer in the cross-sectional configuration of the sense amplifier amplifier stage layer according to the third embodiment of the present invention.

The present invention relates to a method of preventing coupling noise in an amplification circuit, and more particularly, a coupling using a shield plug and a dual layer to remove coupling noise in a sense amplifier amplifier stage. The present invention relates to a noise prevention method.

As the operating voltage of the memory chip decreases, an operating voltage margin of the threshold voltage of the NMOS transistor and the PMOS transistor is insufficient, resulting in deterioration of an operating characteristic of a sense amplifier.

In particular, the threshold voltage difference between both PMOS transistors of the amplifier is greater than the threshold voltage difference between both NMOS transistors of the amplifier, so that the offset voltage of the PMOS amplifier is much larger than the offset voltage of the NMOS amplifier. In low voltage operation, this becomes even more important as the amplifier's ability to drive amplification falls.

In addition, a coupling capacitance value exists between both amplification stages of the sense amplifier and the amplification stages of the adjacent sense amplifiers, thereby causing a bit line sensing voltage due to coupling noise according to a data pattern. ) Will cause deterioration.

As the size of the layout pattern becomes smaller and the voltage becomes lower, the coupling noise between these sense amplifier amplifier stages increases. This will be described through the prior art.

1 is a block diagram of a cell array and sensing related to the prior art. Referring to FIG. 1, a cell array and a sensing related block use a folded bit line structure and a latched sense amplifier.

The DRAM cell consists of one NMOS transistor and one capacitor controlled by a word line. One drain terminal of the NMOS transistor is connected to the bit line, and the other source terminal is connected to one electrode of the capacitor. Defined as the storage node (SN) where is stored.

The other PL electrode of the capacitor is connected to a common cell plate and applied with a VCP voltage. VCP voltage is defined as Half VDD. The VDD voltage is defined as the cell's high operating voltage.

When the bit line BL and the bit line bar / BL are connected and the word line WL0 is activated and the cell data is transferred to the bit line, the bit line bar / BL supplies the reference voltage REF. Input and output of data buffers and sense amplifiers are performed by LDB and LDBB.

2 is a block circuit diagram related to a sense amplifier used in the prior art. Referring to Figure 2, the pull-up activation stage of the latch type sense amplifier is adjusted by the SAP, the pull-down activation stage is adjusted by the SAN.

The VBLP voltage is supplied using the BLEQ signal for bit line BL and bit line bar / BL precharge. VBLP is defined as Half VDD. The sense amplifier, LDB, LDBB, and data input / output are performed by the column select signal YI. The data exchange between the bit line BL and the bit line bar / BL between the amplification unit of the sense amplifier and the cell array unit is performed by the BISH and BISL signals which are bit line BL selection signals.

In addition, the BLEQ signal is used to equalize the voltage between the bit line BL and the bit line bar / BL.

3 shows an operation timing diagram for a conventional sense amplifier. Referring to FIG. 3, the bit line BL, the bit line bar / BL, the SAN, and the SAP are precharged with the VBLP voltage in the precharge period. The VBLP voltage is defined as the HalfVDD voltage and half the voltage of VDD which is the cell high voltage.

In the charge share period, the word line WL is activated and the data of the cell is loaded on the bit line BL.

In the sense amplification period, the SAN transitions to ground voltage and SAP to VDD voltage to amplify the signals of the bit line BL and bit line bar / BL. Will be amplified.

In the restore section, the amplified signal of the bit line BL and bit line bar / BL is rewritten to the cell. When the restore operation is completed, it returns to the precharge state.

4 is a diagram illustrating a conventional cell array and sense amplifier array layout configuration. Referring to FIG. 4, a plurality of bit line BL and bit line bar / BL pairs are configured on a top cell array, and recovery bit line BL and bit line bar / BL pairs are configured on a bottom cell array. do.

The top cell array and the bottom cell array share a common sense amplifier. In this case, the amplifier stage of the sense amplifier array includes a plurality of SLs and / SLs. Bit line BL, bit line bar / BL on cell array, and SL, both amplification stages of sense amplifiers. / SL is composed of the same material using the same layer process.

5 shows a cross-sectional configuration of a sense amplifier amplifier stage layer of the prior art. Referring to FIG. 5, a plurality of SL and / SL lines of the same layer are disposed adjacent to each other. Therefore, coupling capacitance exists between adjacent SL and / SL lines, thereby generating coupling capacitance noise.

Therefore, the sensing voltage (Sensing Voltage) signal between the adjacent SL, / SL will cause degradation.

The present invention has been made to solve the above problems, and an object of the present invention is to remove coupling noise from a sense amplifier stage by using a shield plug.

In addition, the dual layer to remove the coupling noise in the sense amplifier stage for another purpose.

In order to achieve the above object, the present invention provides a method for forming a shield plug between sensing lines of a sense amplifier amplifier stage and a dual layer (Dual) to remove the coupling noise in the sense amplifier amplifier stage. At least one method of forming a layer) is used.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

FIG. 6 shows a shield plug configuration in an array and sense amplifier array layout configuration according to a first embodiment of the present invention. Referring to FIG. 6, a plurality of bit line BL and bit line bar / BL pairs are configured on a top cell array, and recovery bit line BL and bit line bar / BL pairs are configured on a bottom cell array. do.

The top cell array and the bottom cell array share a common sense amplifier. In this case, the amplifier stage of the sense amplifier array includes a plurality of SLs and / SLs. Bit line BL, bit line bar / BL on cell array, and SL, both amplification stages of sense amplifiers. / SL is composed of the same material using the same layer process.

In addition, a shield plug is formed between BL, / BL, SL, and / SL to shield the coupling capacitance component so that coupling capacitance does not exist between each BL, / BL, SL, and / SL.

Figure 7 shows a cross-sectional configuration of the shield plug and the shield layer in the cross-sectional configuration of the sense amplifier amplifier stage layer of the present invention. Referring to FIG. 7, a plurality of SLs and / SLs of the same layer are disposed adjacent to each other. The shield plug is formed such that there is no coupling capacitance between adjacent SLs and / SLs, and each shield plug is configured to be connected to each other using a shield layer. Therefore, the sensing voltage signal between the adjacent SL and / SL is not caused to deteriorate.

8 is a cross-sectional configuration diagram of a dual layer in the cross section of the sense amplifier amplifier stage layer according to the second embodiment of the present invention. Referring to FIG. 8, in order to alleviate the coupling capacitance component, the SLs use a 1 ^st split layer and the / SLs use a second split layer as a dual layer. Configure

9 is a cross-sectional configuration diagram of a dual layer and a dual shield layer in the cross section of the sense amplifier amplifier stage layer according to the third embodiment of the present invention. Referring to Figure 9, SL in order to ease the coupling capacitance components in a dual-layer using a first split layer (1 ^st split layer) and / SL are used to portion the second split layer (2nd split layer) SL, / SL Configure Also configure a shield layer between each SL and a shield layer between / SL. Therefore, the SL and / SL signals use the dual layer and the shield line also uses the dual shield layer so as not to cause deterioration of the sensing voltage signals between the adjacent SL and / SL.

As described above, the present invention has the effect of improving the sensing voltage margin and reducing the cell size by eliminating coupling noise in the sense amplifier without additional layout area by using the shield plug and the dual layer.

In addition, preferred embodiments of the present invention are disclosed for the purpose of illustration, those skilled in the art will be able to various modifications, changes, additions, etc. within the spirit and scope of the present invention, these modifications and changes should be seen as belonging to the following claims. something to do.

Claims (1)

As a method of removing coupling noise in the sense amplifier amplifying stage, Using at least one of a method of forming a shield plug between the sensing line of the sense amplifier amplifier stage and a method of forming the sensing line in a dual layer A method of preventing coupling noise in an amplifier circuit.

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