KR20060030170A - Memory device of semiconductor - Google Patents

Abstract

The present invention relates to a semiconductor memory device, and more particularly, by separating plate lines of semiconductor memory devices to correspond to bit lines and bit line bars, thereby preventing noise in a highly integrated semiconductor memory device and without delaying a tRCD value. A semiconductor memory device capable of amplifying data of a memory cell is provided.

Folded, bitline, tRCD, sensing, amplification.

Description

Semiconductor memory device             

1 is a circuit diagram illustrating a sensing method according to a semiconductor memory device having a conventional quasi folded bit line structure.

FIG. 2 is a timing diagram for describing the operation of FIG. 1.

3 is a semiconductor memory device according to a preferred embodiment of the present invention.

4 is a circuit diagram illustrating a sensing method of a semiconductor memory device according to an exemplary embodiment of the present invention.

5 is a timing diagram for describing an operation of FIG. 4.

Description of the main parts of the drawing-

100a: first memory cell array 100b: second memory cell array

S: memory cell 120: sense amplifier

130: first equalization circuit 140: second equalization circuit

300: sensing circuit S1: first switch

S2: second switch S3: third switch

ISO1: first control signal ISO2: second control signal                 

ISO3: third control signal BL1, BL2, BL3: bit line

/ BL1, / BL2, / BL3: Bitline Bars

Plate line: PL1, PL2, PL3, PL11, PL12, PL13

WL1, WL2, WL11, WL12: word line

The present invention relates to a semiconductor memory device, and more particularly, to a semiconductor memory device capable of amplifying data in a memory cell without delay of a tRCD value while preventing noise in a highly integrated semiconductor memory device.

The semiconductor memory device is composed of a plurality of memory cells, each memory cell consisting of one transistor and one capacitor. Such a semiconductor memory device may be divided into a folded bit line structure and an open bit line structure according to an implementation method thereof. An open bitline structure is used to implement a highly integrated DRAM cell with a minimum cell size of 4F ² / 6F ² , which has the disadvantage of being susceptible to bit line sensing noise. Accordingly, a quasi folded bit line structure has been proposed in which an open bit line structure has a reference line for sensing as a plate line to compensate for the disadvantage of the open bit line structure.

1 is a circuit diagram illustrating a sensing method according to a semiconductor memory device having a conventional semi-folded bit line structure.

As shown in FIG. 1, a semiconductor memory device according to the related art includes a memory cell array 10, a sense amplifier 20, and an equalization circuit 30. The memory cell array 10 includes a plurality of memory cells S connected between a bit line BL and a plate line PL. One memory cell S includes a cell transistor Q and a capacitor C connected in series between the bit line BL and the plate line PL. At this time, the gate of the cell transistor Q becomes a word line. In addition, the isolation transistor S1 is connected between the plate line PL and the sense amplifier 20, and the isolation transistor S2 is connected between the bit line BL and the bit line bar / BL, and the bit line BL is connected. ) And the sense transistor 20 are connected to the isolation transistor S3. The isolation transistor S1 is turned on by the isolation signal ISO1, the isolation transistor S2 is turned on by the isolation signal ISO2, and the isolation transistor S3 is turned on by the isolation signal ISO3. The equalization circuit 30 is composed of transistors T1, T2 and T3 controlled by the equalization signal BLEQB, so that the bit line BL, the bit line bar / BL and the plate line PL are set to Vcore / 2. Precharge. In this case, the plate line PL is connected to one of the bit line BL and the bit line bar / BL in the form of a flat plate. Therefore, in the related art, amplification is possible only after a switching operation is performed to separate one plate line PL shared by the bit line BL and the bit line bar / BL to sense data of the memory cell S. The disadvantage is that.

A sensing method of a semiconductor memory device according to the prior art will be described with reference to the timing diagram of FIG. 2.

Referring to FIG. 2, in the precharge period (˜t0; the period in which the ISO1, ISO2, ISO3, and BLEQB are high states), Vcore / Precharge to 2. In the sensing period t0 to t1, a voltage between the bit line BL and the plate line PL is sensed. At this time, assuming that data "0" is stored in the memory cell S of FIG. 1, the potential of the bit line BL is lowered by ΔV _L. In the amplification period t1 to t2, the sense amplifier power SAP is turned high to turn off the isolation transistor S1 while the isolation transistor S2 is turned on to amplify the sensed data. Then, amplification is performed by lowering the bit line BL potential and increasing the potential of the bit line bar / BL. As described above, the plate line PL is conventionally formed as one flat plate on the bit line BL and the bit line bar / BL adjacent thereto, so that the bit line BL and the bit line bar / BL are one. As the plate lines PL are shared, the turn-off operation of the isolation transistor S1 for separating the plate lines PL and the isolation transistor for connecting the bit line bar / BL and the sense amplifier 20 are performed. There is a problem that amplification is possible only after the turn-on operation of S2 is performed. This acts as a delay factor of the time between Ras & Cas access (tRCD) value in the semiconductor memory device.

Accordingly, an object of the present invention is to provide a semi-folded bit line structure semiconductor memory capable of amplifying data in a memory cell without delay of tRCD value while preventing noise in a highly integrated semiconductor memory device. To provide a device.

According to the present invention for achieving the above object, a plate comprising a plurality of word lines and bit lines and a plurality of memory cells connected to the plurality of word lines and bit line bars, the plate connected to the plate electrode of the cell capacitor of the memory cell And a plurality of sensing circuits for sensing and amplifying data stored in the memory cells in pairs of a plurality of memory cell arrays including lines and two neighboring memory cell arrays, and separating the plate lines to correspond to the bit lines. A semiconductor memory device is provided.

The sensing circuit may include: a first equalization circuit for precharging a divided voltage to the bit line, the plate line, and the bit line bar according to a first equalization signal, a first switch for switching the connection of the bit line and the plate line; A second switch for switching the connection between the bit line and the bit line bar, a sense amplifier and the sense amplifier for sensing and amplifying data of the memory cell before separating the bit line and the plate line through the first switch; And a third switch for switching the connection with the bit line.

The sensing circuit may further include a second equalization circuit for precharging the plate line according to a second equalization signal.                     

The first switch consists of a transistor connected between the sense amplifier and the plate line.

The second switch consists of a transistor connected between the bit line bar and the first equalization circuit.

The third switch is composed of a transistor connected between the bit line and the sense amplifier.

That is, the present invention is formed by separating the plate line connected to the memory cell capacitor of the semiconductor memory device into a structure corresponding to the bit line and the bit line bar, so that the bit line and the plate line for data sensing of the bit line and the bit line bar are formed. Before proceeding with the separation operation, the potential difference between the bit line and the plate line can be amplified. Accordingly, a semiconductor memory device having a quasi-folded bit line structure capable of amplifying data of a memory cell without delay of tRCD and preventing noise of the semiconductor memory device can be implemented.

Hereinafter, the present invention will be described in more detail with reference to Examples. These examples are only for illustrating the present invention, and the scope of protection of the present invention is not limited to these examples.

3 is a semiconductor memory device according to a preferred embodiment of the present invention.

Referring to FIG. 3, in a semiconductor memory device according to an embodiment of the present invention, the first and second memory cell arrays 100a and 100b and the first and second memory cell arrays 100a and 100b are paired. A plurality of sensing circuits 300 for sensing and amplifying data stored in the plurality of memory cells (S). The first memory cell array 100a includes bit lines BL1, BL2, BL3,... Formed in a direction perpendicular to the plurality of word lines WL1, WL2,..., And word lines WL1, WL2,. Includes ..) The second memory cell array 100b also includes bit line bars / BL1, / BL2, which are formed in a direction perpendicular to the plurality of word lines WL11, WL12, ..., and word lines WL11, WL12, .... / BL3, ...). A plurality of memory cells S are connected between the word lines WL1, WL2,..., And the bit lines BL1, BL2, BL3, ... of the first memory cell array 100a. In addition, plate lines PL1, PL2, PL3, ... corresponding to the respective bit lines BL1, BL2, BL3, ... are provided, and each plate line PL1, PL2, PL3, ... ...) is connected to the plate electrode of the capacitor (C) of the memory cell (S). For example, the memory cell S is connected between the bit line BL1 and the plate line PL1, and the word line WL1 is connected to the gate of the cell transistor Q of each memory cell S.

Since the structure of the second memory cell array 100b is not different from that of the first memory cell array 100a, a description thereof will be omitted.

As described above, according to the present invention, instead of the plate line having a single flat plate type structure, the plate line is separated to correspond to each bit line and the bit line bar, thereby enabling the semi-folded bit line to be implemented. The sensing operation can be started immediately without waiting for the switching time between the line and sense amplifiers and the switching time between neighboring bitline bars and sense amplifiers. That is, before the operation of disconnecting the bit line and the plate line and connecting the bit line and the bit line bar, the sensing and amplification operation is performed through the bit line and the plate line.

4 is a detailed circuit diagram illustrating a part of a sensing circuit 300 and a first memory cell array 100a in order to explain a sensing method of a semiconductor memory device according to an exemplary embodiment of the present invention.

Referring to FIG. 4, the sensing circuit 300 includes a first equalization circuit 130, a sense amplifier 120, and first to third switches S1, S2, and S3. The first equalization circuit 130 is composed of three NMOS transistors T1, T2, and T3. For example, when the first equalization signal BLEQB1 is high when the first to third switches S1, S2, and S3 are turned on, the transistors T1, T2, and T3 are turned on to turn on the bit line BL1. , The plate line PL1 and the bit line bar / BL1 are precharged with a voltage of Vcore / 2. The sense amplifier 120 is composed of NMOS transistors N1 and N2 and PMOS transistors P1 and P2. For example, if the potential of the bit line BL1 rises after the above-described pre-autonomous operation, the NMOS transistor N1 is turned on, so that the potential of the node K1 becomes the ground potential (/ S is the ground potential). Since the node K1 becomes the ground potential / S, the PMOS transistor P1 is turned on, so that the potential of the node K2 becomes the Vcore potential (the RTO is usually a positive potential). Therefore, the bit line BL1 goes up to the Vcore potential RTO and the potential of the bit line bar / BL1 goes down to the ground potential / S.

On the contrary, when the potential of the bit line bar / BL1 is higher than the precharge potential Vcore / 2, the NMOS transistor N1 is turned on so that the potential of the node K2 becomes the ground potential / S. When the node K2 becomes the ground potential / S, the PMOS transistor P2 is turned on, so that the potential of the node K1 becomes the RTO potential (positive potential). Accordingly, the bit line bar / BL1 rises to the RTO potential, while the potential of the bit line BL1 falls to the ground potential / S.

Meanwhile, the sensing circuit 300 may further include or may not include the second equalization circuit 140. The second equalization circuit 140 provides the distribution voltage Vcore / 2 to the plate line PL1 connected to the plate electrode of the cell capacitor C of the memory cell S, thereby providing the cell capacitor C of the memory cell S. It is possible to prevent the overload phenomenon of the cell capacitor C of the memory cell S by reducing the potential difference in the quadrature.

The operation of FIG. 4 will be described in more detail with reference to FIG. 5.

In the precharge section ˜ t0, all of the first to third control signals ISO1, ISO2, and ISO3 become high level H, and thus, the first to third switches S1, S2, and S3; Turn on). At this time, when the first bit line equalization signal BLEQB1 is input at the high level H, the bit lines BL1 connected as the first to third switches S1, S2, and S3 (see FIG. 4) are turned on. And plate line PL1 and bitline bar / BL1 are both precharged to Vcore / 2.

In the sensing period t0 to t1, the second control signal ISO2, the first bit line equalization signal BLEQB1, and the second bit line equalization signal BLEQB2 become the low level L, and thus, the second switch S2; 4) is turned off, so that the bit line bar / BL1 and the bit line BL1 are separated and the bit line BL1 and the plate line PL1 except for the bit line bar / BL1 are separated. Data can be sensed. At this time, assuming that data "0" is stored in the memory cell S (see FIG. 4) of the first memory cell array 100a (see FIG. 4), the potential of the bit line BL1 is as low as ΔV _L. You lose.

In the amplification period t1 to t2, the sense amplifier driving signal SAP becomes the high level H, and the bit line BL1 and the plate line PL1 detected by the sense amplifier 120 in the sensing period t0 to t1. Amplifies the potential difference ΔV _L ). That is, unlike the conventional use of only the bit line bar / BL1 as a reference line in the amplification operation, in the present invention, the plate line PL1 is separated to correspond to the bit line BL1 and the bit line bar / BL1. Even during the amplification operation, the plate line PL1 can be used as a reference line, thereby amplifying the potential difference between the bit line BL1 and the plate line PL1. As mentioned above, the present invention makes it possible to prevent noise by using the plate line PL1 as a reference line in sensing and amplifying operations.

When the first control signal ISO1 reaches the low level L, the first switch S1 (see FIG. 4) is turned off to separate the bit line BL1 and the plate line PL1. When the second control signal ISO2 reaches the high level H, the second switch S2 (see FIG. 4) is turned on, so that the data of the bit line BL1 and the bit line bar / BL1 are turned on. It can sense and amplify. That is, in the semiconductor memory device according to the preferred embodiment of the present invention, the turn-off operation of the first switch S1 (see FIG. 4) and the bit line BL1 for separating the bit line BL1 and the plate line PL1 may be performed. As the amplification is performed through the sense amplifier 120 (see FIG. 4) before the turn-on operation of the second switch S2 (see FIG. 4) for connecting the bit line bar / BL1, the amplification time (= t1) was faster to reduce the sensing interval. Therefore, the quasi-folded bit line structure can be implemented in the semiconductor memory device without delay of tRCD.

However, after the amplification operation using the bit line BL1 and the plate line PL1, if the Vcore voltage is applied to the plate line PL1 throughout the amplification period, the potential difference between the plate line PL1 and the bit line BL1 becomes too large. The problem that excessive stress is applied to the cell capacitor C of the cell S occurs. Accordingly, to prevent this, one NMOS transistor T4 (see FIG. 4) connected to the plate line PL1 between the first switch S1 (see FIG. 4) and the first memory cell array 100a (see FIG. 4) is used. By implementing the second equalization circuit 140 (refer to FIG. 4), the voltage value of the plate line PL1 is set to Vcore / 2 by the second bit line equalization signal BLEQB2 so that the cell capacitor of the memory cell S ( The potential difference of C) can be reduced. This prevents the overload of the cell capacitor C of the memory cell S. FIG.

In addition, in the amplification section t1 to t2, when a certain point is reached after the operation of the sense amplifier 140 (see FIG. 4), the adjacent bit line bars / BL1 are referred to instead of the plate line PL1 corresponding to the bit line BL1. Perform an amplification operation on the line.

As described above, according to the present invention, when sensing data of a memory cell in a semiconductor memory device, noise can be prevented by using a plate line as a reference line.

In addition, since the plate lines connected to the memory cell capacitors of the semiconductor memory device are formed in a structure corresponding to the bit lines and the bit line bars, a highly integrated semiconductor memory device may be realized without delay of tRCD of the semiconductor memory device.

Claims (6)

A plurality of memory cell arrays including a plurality of word lines and bit lines and a plurality of memory cells connected to the plurality of word lines and bit line bars, and a plate line connected to a plate electrode of a cell capacitor of the memory cell; And And a plurality of sensing circuits for sensing and amplifying data stored in the memory cells in pairs of two neighboring memory cell arrays, and separating the plate line to correspond to the bit line. The method of claim 1, wherein the sensing circuit, A first equalization circuit for precharging the bit line, the plate line, and the bit line bar according to a first equalization signal; A first switch for switching the connection of the bit line and the plate line; A second switch for switching the connection of the bit line and the bit line bar; A sense amplifier configured to sense and amplify data of the memory cell before separating the bit line and the plate line through the first switch; And And a third switch for switching the connection between the sense amplifier and the bit line. The semiconductor memory device of claim 1, wherein the sensing circuit further comprises a second equalization circuit for precharging the plate line according to a second equalization signal. The semiconductor memory device of claim 2, wherein the first switch comprises a transistor connected between the sense amplifier and a plate line. 3. The semiconductor memory device of claim 2, wherein the second switch comprises a transistor connected between the bit line bar and the first equalization circuit. The semiconductor memory device of claim 2, wherein the third switch comprises a transistor connected between the bit line and the sense amplifier.

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