KR20070082989A - Method for fabricating flash memory device - Google Patents

Abstract

A method for fabricating a flash memory device is provided to simplify a fabricating process by one titanium deposition process and one annealing process by eliminating the necessity for re-formation of a titanium silicide layer on a drain contact. A semiconductor substrate is prepared which has an interlayer dielectric with a drain contact hole. A part of the drain contact hole is partially filled with a drain contact(23). A metal contact hole is formed in the interlayer dielectric. A refractory metal layer and a first metal nitride layer are sequentially formed on the resultant structure. A silicide layer is formed on an interface of the drain contact and the refractory metal layer and on an interface of the semiconductor substrate under the metal contact hole and the refractory metal layer. A first conductive layer is formed on the front surface including the metal contact hole, and the front surface is polished to expose the interlayer dielectric so that a metal contact(27a) is formed. A bitline(30) and a metal line are formed on the drain contact and the metal contact, having a stack layer of a second metal nitride layer and a second conductive layer. The process for forming the drain contact includes the following steps. A polysilicon layer is formed on the front surface including the drain contact hole. The polysilicon layer is recessed to expose the upper part of the interlayer dielectric and the drain contact hole.

Description

Method for fabricating flash memory device

1A to 1E are cross-sectional views illustrating a manufacturing process of a flash memory device according to the prior art.

2A through 2E are cross-sectional views illustrating a manufacturing process of a flash memory device according to an exemplary embodiment of the present invention.

<Explanation of symbols for main parts of the drawings>

23: drain contact 25a: titanium film

25b: titanium nitride film 25: first barrier film

26: titanium silicide film 27a: metal contact

28: second barrier layer 30: bit line

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a flash memory device, and more particularly, to secure ohmic characteristics between a drain contact and a bitline, and to reduce capacitance between bitlines. It relates to a manufacturing method of.

As part of improving device performance in high-density NAND flash memory devices, efforts are being made to reduce the bit line RC delay time in order to reduce program time.

Increasing the thickness of the bit line can reduce the bit line resistance, but it is difficult to reduce the RC delay time because the capacitance between neighboring bit lines increases. Thus, efforts are being made to reduce the bit line resistance while reducing the bit line thickness.

Hereinafter, the prior art will be described with reference to the accompanying drawings.

1A to 1E are cross-sectional views illustrating a manufacturing process of a flash memory device according to the prior art.

First, as shown in FIG. 1A, an interlayer insulating film 12 is formed on a semiconductor substrate 10 on which a cell region and a peripheral circuit region are defined, and a predetermined lower structure including the device isolation film 11 is formed, and the planarization process is performed. Thus, the surface of the interlayer insulating film 12 is planarized.

The lower structure formed in the cell region includes a plurality of unit cell strings including a drain select line connected in series between the drain region and the source region, memory cell transistors, and a source select line. The lower structure formed in the peripheral circuit region includes peripheral transistors and the like.

Next, drain contact holes exposing the drain regions formed in the cell region are formed by a photolithography process. Subsequently, a polysilicon film is deposited on the entire surface including the drain contact holes, and the polysilicon film is chemical mechanical polished (CMP) to expose the interlayer insulating film 12 to form a drain contact 13.

Next, as shown in FIG. 1B, a metal contact hole exposing the semiconductor substrate 10 in which the junction region of the peripheral transistor is formed is formed by a photolithography process. In the embodiment shown in the drawings, the metal contact hole is formed in the junction region of the peripheral transistor, but may be formed in a portion other than the junction region, such as a polysilicon gate of the peripheral transistor.

Then, the first titanium film (Ti) 14a and the first titanium nitride film (TiN) 14b are sequentially deposited on the entire surface to form the first barrier film 14, and then subjected to an annealing process. A first titanium silicide film (TiSix) 15 is formed at the interface between the semiconductor substrate 10 and the first titanium film 14a under the metal contact hole, and at the interface between the drain contact 13 and the first titanium film 14a. do.

The first titanium silicide layer 15 may include a poly-Si component of the drain contact 13, titanium (Ti) of the first titanium layer 14a, and a lower metal contact hole semiconductor substrate 10 by an annealing process. Silicon (Si) component and titanium (Ti) of the first titanium film 14a react to each other, and have low resistance.

Subsequently, the first tungsten film 16 is deposited on the entire surface including the metal contact hole to fill the metal contact hole, and as illustrated in FIG. 1C, the front surface is polished so that the interlayer insulating film 12 is exposed to the metal contact 16a. To form. As the polishing process, a chemical mechanical polishing (CMP) process is preferably used.

When the first barrier layer 14 remains on the interlayer insulating layer 12 after the polishing process, the drain contacts 13 are shortened with each other. An additional polishing process is added to prevent this phenomenon. To be carried out. At this time, the first titanium silicide layer 15 formed on the drain contact 13 is removed.

Then, as shown in FIG. 1D, a second titanium film (Ti) 17a and a second titanium nitride film (TiN) 17b are sequentially deposited on the entire surface to form a second barrier film 17, and then annealed ( An anneal process is performed to form a second titanium silicide film (TiSix) 18 at the interface between the drain contact 13 and the second titanium film 17a. The second titanium silicide layer 18 is formed by reacting the silicon (Si) component of the drain contact 13 with the titanium (Ti) component of the second titanium layer 17a. The second titanium silicide layer 18 is formed by the second titanium silicide layer 18. An ohmic characteristic between the drain contact 13 and the bit line is secured.

Then, a second tungsten film 19 is formed on the second barrier film 17, and the second tungsten film 19 and the second barrier film 17 are patterned by a photolithography process as shown in FIG. 1E. The bit line 100 and the metal line 200 are formed on the drain contact 13 and the metal contact 16a, respectively.

In the above-described conventional technique, since the first titanium silicide film 15 formed on the drain contact 13 is removed during the additional polishing process, the second barrier film 17 may be removed to re-form the silicide film on the drain contact 13. It is formed of a laminated film of the second titanium film 17a and the second titanium nitride film 17b.

When the second barrier layer 17 is formed of a laminated layer of the second titanium layer 17a and the second titanium nitride layer 17b, ohmic characteristics between the drain contact 13 and the bit line 100 may be secured. Since the height of the bit line 100 is increased due to the 2 titanium film 17a, the capacitance between the bit lines is increased. Since the bit-line capacitance in the highly integrated NAND flash memory device is very sensitive to a change in the thickness of the second barrier layer 17, an improvement is required.

The present invention has been made to solve the above-described problems of the prior art, to ensure the drain contact (ohmic) characteristics between the bit (drain contact) and the bit line, it is possible to reduce the capacitance (bit capacitance) between the bit line (bit line) It is an object of the present invention to provide a method of manufacturing a flash memory device.

A method of manufacturing a flash memory device according to the present invention includes providing a semiconductor substrate having an interlayer insulating film having a drain contact hole, forming a drain contact partially filling the drain contact hole, and forming a metal contact in the interlayer insulating film. Forming a hole, sequentially forming a high melting point metal film and a first metal nitride film on the entire surface including the drain contact and the metal contact hole, an interface between the drain contact and the high melting point metal film, and the metal contact Forming a silicide film at an interface between the lower hole semiconductor substrate and the high melting point metal film, forming a first conductive film on the entire surface including the metal contact hole, and polishing the entire surface to expose the interlayer insulating film to form a metal contact; And a laminated film of a second metal nitride film and a second conductive film on the drain contact and the metal contact. Forming the formed bit lines and the metal lines.

Hereinafter, with reference to the accompanying drawings will be described a preferred embodiment of the present invention. However, the present invention is not limited to the embodiments disclosed below, but may be implemented in various forms, and the scope of the present invention is not limited to the embodiments described below. Only this embodiment is provided to complete the disclosure of the present invention and to fully inform those skilled in the art, the scope of the present invention should be understood by the claims of the present application.

2A through 2E are cross-sectional views illustrating a manufacturing process of a flash memory device according to an exemplary embodiment of the present invention.

First, as shown in FIG. 2A, an interlayer insulating film 22 is formed on a semiconductor substrate 20 on which a cell region and a peripheral circuit region are defined and a predetermined substructure including the device isolation film 21 is formed, and a planarization process is performed. This makes the surface of the interlayer insulating film 22 flat.

The lower structure formed in the cell region has a plurality of unit cell strings including a drain select line connected in series between the drain region and the source region, memory cell transistors, and a source select line. The lower structure formed in the peripheral circuit region includes a peripheral transistor and the like.

Subsequently, drain contact holes are formed to expose the drain regions formed in the cell region by a photolithography process, and a polysilicon layer is deposited on the entire surface including the drain contact holes. It is preferable to use a doped polysilicon film (doped poly) as the polysilicon film.

Then, the polysilicon layer is recessed to form a drain contact 23 under the drain contact hole. By the recess process, the surface of the interlayer insulating layer 22 is exposed and the upper portion of the drain contact hole is exposed. At this time, the thickness of the recessed polysilicon film is about 10 ~ 2000Å.

The method of recessing the polysilicon layer may include planarizing the polysilicon layer so that the interlayer insulating layer 22 is exposed after embedding the polysilicon layer, and then etching the polysilicon layer on the drain contact hole by etching the entire surface. One of the methods using only the etching process is used. Here, it is preferable that the leveling method uses CMP. As is well known, the CMP process has a higher process cost than the front etching process, so it is preferable to use the latter method rather than the former.

Next, a metal contact hole 24 exposing the semiconductor substrate 20 in which the junction region of the peripheral transistor is formed by a photolithography process is formed. In the embodiment shown in the drawing, the metal contact hole 24 is formed in the semiconductor substrate 20 in which the junction region of the peripheral transistor is formed. However, the metal contact hole 24 may be formed in a portion other than the junction region, such as a polysilicon gate of the peripheral transistor. have.

Then, as shown in FIG. 2B, a titanium film (Ti) 25a and a titanium nitride film (TiN) 25b are sequentially deposited on the entire surface to form a first barrier film 25, and then annealed. A titanium silicide film (TiSix) 26 is formed at the interface between the drain contact 23 and the titanium film 25a and at the interface between the semiconductor substrate 20 and the titanium film 25a under the metal contact hole 24. To form.

The titanium silicide layer 26 is formed of polysilicon (poly-Si) of the drain contact 23, titanium (Ti) of the titanium layer 25a, and silicon of the semiconductor substrate 20 under the metal contact hole 24 by an annealing process. (Si) and titanium (Ti) of the titanium film 25a react with each other, and have low resistance.

A seam is generated in the drain contact 23 when the polysilicon film is recessed using the above-described entire etching process, and since the seam is sufficiently filled with the first barrier film 25, the titanium silicide film 26 is formed. The drain contact resistance can be secured.

Subsequently, the first tungsten film 27 is deposited on the entire surface including the metal contact hole 24, and the front surface is polished to form the metal contact 27a in the metal contact hole 24 as shown in FIG. 2C. It is preferable to use a CMP process as the polishing process.

If the first barrier layer 25 remains on the interlayer insulating layer 22 after the polishing process, the short contact between the drain contacts 23 or between the drain contact 23 and the metal contact 27a does not occur. In order to prevent this, an additional polishing process, that is, an over CMP process, is performed on the target just before the titanium silicide film 26 formed on the drain contact 23 is attacked. The further polishing process has a good uniformity because of the targeting of the polishing process.

Subsequently, as shown in FIGS. 2D and 2E, the second barrier layer 28 is formed using a titanium nitride layer TiN having a minimum thickness for adhesion and metal diffusion prevention, and the second barrier layer 28 is formed on the second barrier layer 28. After the second tungsten film 29 is formed, the second tungsten film 29 and the second barrier film 28 are patterned by a photolithography process to form bit lines on the drain contact 23 and the metal contact 27a, respectively. 30 and metal lines 31 are formed.

In the present invention described above, since the titanium silicide film 26 formed on the drain contact 23 is not removed during the additional polishing step performed after the metal contact 27a is formed, the titanium silicide film does not need to be formed again. Therefore, processes (titanium film formation process and annealing process) for reforming the titanium silicide film on the drain contact can be omitted.

In addition, since the second barrier layer 28 is formed of only a titanium nitride layer having a minimum thickness for adhesion and metal diffusion prevention, not a double layer of titanium and titanium nitride layer, the bit line height is lowered, thereby reducing capacitance between bit lines.

In addition, in the polysilicon recess process for forming the drain contact, a low-cost front etching process is used instead of an expensive CMP process, thereby reducing manufacturing cost. In addition, since the seam that may be generated during the polysilicon full surface etching process is sufficiently filled using the first barrier layer 25 and the titanium silicide layer 26 is formed, stable drain contact resistance is secured.

In the above-described embodiment, the titanium film 25a is used to interface the drain contact 23 and the titanium film 25a and the interface between the semiconductor substrate 20 and the titanium film 25a under the metal contact hole 24. Although only the case of forming the titanium silicide film (TiSix) 26 is mentioned, a high melting point metal such as tungsten (W), tantalum, molybdenum, etc. is used instead of the titanium film, and a tungsten silicide film and tantalum are used instead of the titanium silicide film. A high melting point silicide film such as a silicide film and a molybdenum silicide film may be formed. Instead of the titanium nitride films of the first and second barrier films 25 and 28, metal nitride films such as tungsten nitride film, tantalum nitride film, and molybdenum nitride film may be used, and the first and second tungsten films 27 ( 29) turns out that it can be replaced with conductive films such as polysilicon and titanium films.

As described above, the present invention has the following effects.

First, the titanium silicide layer formed on the drain contact may not be removed during the additional polishing process performed after the metal contact is buried, so that the titanium silicide layer may not be formed on the drain contact. Therefore, since one titanium deposition process and one annealing process can be omitted, the process can be simplified.

Second, the thickness of the second barrier layer may be reduced by configuring the second barrier layer as a single layer of titanium nitride.

Third, since the thickness of the second tungsten film can be increased by the reduced thickness of the second barrier film, the bit line resistance can be reduced.

Fourth, since the thickness of the second barrier film is reduced, the capacitance between bit lines is reduced. Therefore, the bit line RC delay time can be improved, thereby reducing the program time.

Fifth, since the seam generated in the drain contact during the polysilicon film recess process is sufficiently filled by using the first barrier film and a titanium silicide film is formed, a stable drain contact resistance can be secured, thereby ensuring the stability of the on-current. have.

Sixth, it is possible to reduce the cost because the front-side etching process is used instead of the expensive CMP process when polysilicon film recesses.

Claims (8)

Providing a semiconductor substrate having an interlayer insulating film having a drain contact hole; Forming a drain contact partially filling the drain contact hole; Forming a metal contact hole in the interlayer insulating film; Sequentially forming a high melting point metal film and a first metal nitride film on the entire surface including the drain contact and the metal contact hole; Forming a silicide film at an interface between the drain contact and the high melting point metal film and at an interface between the lower metal contact hole semiconductor substrate and the high melting point metal film; Forming a metal contact by forming a first conductive layer on the entire surface including the metal contact hole and polishing the entire surface to expose the interlayer insulating layer; And Forming a bit line and a metal line formed of a stacked layer of a second metal nitride film and a second conductive film on the drain contact and the metal contact. The method of claim 1, Forming a polysilicon film on the entire surface of the drain contact including the drain contact hole; And And recessing the polysilicon layer to expose the interlayer insulating layer and the upper portion of the drain contact hole. The method of claim 2, Recessing the polysilicon film may include planarizing the polysilicon film to expose the interlayer insulating film; And And etching the entire polysilicon layer so that the upper portion of the drain contact hole is exposed. The method of claim 2, And recessing the polysilicon layer includes etching the entire surface of the polysilicon layer to expose the upper portion of the interlayer insulating layer and the drain contact hole. The method of claim 1, And the silicide layer is formed by reacting a metal component of the high melting point metal layer with a silicon component of the semiconductor substrate under the drain contact and the metal contact hole by an annealing process. The method of claim 1, And performing an additional polishing process on a point at which the silicide film formed on the drain contact is not attacked after the polishing process. The method of claim 1, A method of manufacturing a flash memory device, wherein the first conductive film and the second conductive film are formed using a tungsten film. The method of claim 1, And forming the first metal nitride film and the second metal nitride film using a titanium nitride film.

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