KR20070080638A - Manufacturing method of liquid crystal display - Google Patents

Abstract

A method for manufacturing an LCD(Liquid Crystal Display) is provided to simplify the manufacturing process, by performing a polysilicon thin film patterning process and an impurity doping process for forming a lower storage electrode through one mask so as to decrease the number of mask used to manufacture the LCD. A polysilicon thin film(7) is formed on an insulating substrate(30). A photoresist pattern(60) is formed on the polysilicon thin film. The polysilicon thin film is pattern-etched by using the photoresist pattern as a mask. A portion of the photoresist pattern is removed. Impurities are doped in a portion of the polysilicon thin film, which are exposed by removing the portion of the photoresist pattern. The photoresist pattern has a stepped portion due to difference of thickness, wherein the photoresist pattern is formed by using a diffraction exposure mask.

Description

MANUFACTURING METHOD OF LIQUID CRYSTAL DISPLAY}

1 is a plan view illustrating one sub-pixel in a thin film transistor substrate of a liquid crystal display according to an exemplary embodiment of the present invention.

FIG. 2 is a cross-sectional view of one sub pixel taken along the line II-II 'shown in FIG. 1; FIG.

3 is a cross-sectional view illustrating a CMOS thin film transistor included in a driving circuit in a thin film transistor substrate of a liquid crystal display according to an exemplary embodiment of the present invention.

4A to 4C are plan views and cross-sectional views illustrating a first mask process in a method of manufacturing a thin film transistor substrate according to an exemplary embodiment of the present invention.

5A through 5C are cross-sectional views illustrating in detail the first mask process illustrated in FIG. 4B.

6A to 6C are plan views and cross-sectional views illustrating second and third mask processes in a method of manufacturing a thin film transistor substrate according to an exemplary embodiment of the present invention.

7A and 7B are cross-sectional views illustrating in detail the second and third mask processes illustrated in FIG. 6C.

8A through 8C are plan and cross-sectional views illustrating a fourth mask process in a method of manufacturing a thin film transistor substrate according to an exemplary embodiment of the present invention.

9A to 9C are plan views and cross-sectional views illustrating a fifth mask process in a method of manufacturing a thin film transistor substrate according to an exemplary embodiment of the present invention.

10A to 10C are plan views and cross-sectional views illustrating a sixth mask process in a method of manufacturing a thin film transistor substrate according to an exemplary embodiment of the present invention.

11A and 11B are plan and cross-sectional views illustrating a seventh mask process in a method of manufacturing a thin film transistor substrate according to an exemplary embodiment of the present invention.

12A and 12B are plan views and cross-sectional views illustrating an eighth mask process in a method of manufacturing a thin film transistor substrate according to an exemplary embodiment of the present invention.

<Description of Main Parts of Drawing>

2: gate line 4: storage line

6, 46: gate electrodes 8, 48: active layer

8S, 48S: source region 8D, 48D: drain region

10: storage lower electrode 12S, 12D, 52S, 52D, 20: contact hole

14: data line 15, 25: NMOS TFT

16, 56: source electrode 18, 58: drain electrode

22 pixel electrode 24 reflective electrode

30: insulating substrate 32: buffer film

34 gate insulating film 36 interlayer insulating film

38: organic insulating film 40: through hole

60, 80: photoresist pattern 70: diffraction exposure mask

72 mask substrate 74 blocking pattern

76: slit

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a liquid crystal display device using low temperature polysilicon, and more particularly to a method of manufacturing a liquid crystal display device which can reduce the number of processes.

A liquid crystal display (LCD) displays an image by causing each of the liquid crystal subpixels arranged in a matrix form on a liquid crystal display panel (hereinafter, referred to as a liquid crystal panel) to adjust light transmittance according to a video signal. The liquid crystal display uses a thin film transistor (TFT) as a switch element for driving an active matrix. The TFT uses an amorphous silicon thin film or a low temperature poly silicon (LTPS) thin film. The LTPS thin film is a thin film obtained by crystallizing an amorphous silicon thin film by a laser annealing method, so the electron mobility is very high, and the circuit is highly integrated, and thus, the driving circuit of the image display unit may be embedded on the substrate. The driving circuit incorporated in the liquid crystal panel using LTPS includes a plurality of PMOS TFTs, NMOS TFTs, and CMOS TFTs.

Each of the liquid crystal subpixels arranged in a matrix form in the image display portion of the liquid crystal panel includes a TFT connected to the gate line and the data line, and a liquid crystal capacitor and a storage capacitor connected in parallel with the TFT. The liquid crystal capacitor is connected to the TFT so that the pixel electrode formed on the TFT substrate overlaps with the common electrode formed on the color filter substrate with the liquid crystal interposed therebetween, and the storage capacitor has an active layer extended from the active layer of the TFT interposed between the insulating film. It overlaps with the storage line and is formed on the TFT substrate. The active layer constituting the storage capacitor becomes conductive by doping with impurities.

Therefore, the conventional liquid crystal display device has a problem in that the number of processes is complicated as a mask process for forming an active layer of a TFT and a storage capacitor and a mask process for doping impurities in an active layer of a storage capacitor are required.

Accordingly, the present invention is to provide a method for manufacturing a liquid crystal display device that can reduce the number of steps to solve the conventional problems.

To this end, the manufacturing method of the liquid crystal display according to the present invention comprises the steps of forming a polysilicon thin film on an insulating substrate; Forming a photoresist pattern on the polysilicon thin film; Patterning the polysilicon thin film using the photoresist pattern as a mask; Removing a portion of the photoresist pattern; Doping impurities in a portion of the polysilicon thin film exposed by removing the photoresist pattern.

Forming the photoresist pattern includes forming a photoresist pattern having a step with a thickness difference using a diffraction exposure mask.

Removing a portion of the photoresist pattern may include removing a region of a relatively low thickness from the stepped photoresist pattern.

Patterning the polysilicon thin film to form an active layer of a thin film transistor and a storage lower electrode connected to the active layer; The impurities are doped to the storage lower electrode.

The method of manufacturing a liquid crystal display according to the present invention may include forming a first insulating film on the insulating substrate on which the active layer and the storage lower electrode are formed: a gate overlapping a portion of the active layer on the first insulating film. Forming an electrode, a gate line connected to the gate electrode, and a storage line overlapping the lower storage electrode; Forming a source region and a drain region by doping an impurity in a region not overlapped with the gate electrode in the active layer; Forming a second insulating film on the first insulating film on which the gate electrode, the gate line, and the storage line are formed, and exposing a source region and a drain region of the active layer, respectively; Forming a source electrode and a drain electrode connected to the source and drain regions of the active layer, respectively, and a data line connected to the source electrode; Forming a third insulating film on the second insulating film on which the source electrode, the drain electrode, and the data line are formed and exposing the drain electrode; And forming a pixel electrode connected to the drain electrode on the second insulating film.

Doping an impurity in the active layer includes doping a first impurity in some active layers and a second impurity in the remaining active layers in a plurality of active layers.

In addition, the manufacturing method of the liquid crystal display according to the present invention comprises the steps of: forming an organic insulating film with the third insulating film and forming a through hole penetrating the organic insulating film; The method may further include forming a reflective electrode on the third insulating layer on which the pixel electrode is formed to expose the pixel electrode formed in the transmission hole.

Other features and advantages of the present invention in addition to the above technical problem will become apparent from the description of the preferred embodiment of the present invention with reference to the accompanying drawings.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to FIGS. 1 to 12B.

1 is a plan view illustrating one subpixel in a thin film transistor substrate of a transflective LTPS liquid crystal display according to an exemplary embodiment of the present invention, and FIG. 2 is a cross-sectional view of one subpixel along a line II-II ′ of FIG. 1. to be.

The thin film transistor substrate of the LTPS liquid crystal display according to the present invention is divided into a display area in which a plurality of sub pixels are arranged in a matrix form to display an image, and a drive circuit area in which a driving circuit for driving the display area is formed. The driving circuit of the thin film transistor substrate is composed of a plurality of signal lines and CMOS TFTs in which a plurality of NMOS TFTs, PMOS TFTs, NMOS TFTs, and PMOS TFTs are connected in parallel.

1 and 2 illustrate an NMOS TFT 15 connected to a gate line 2 and a data line 14, and a pixel electrode 22 connected to an NMOS TFT 15 and formed in a sub pixel region. ) And a reflective electrode 24 connected to the NMOS TFT 15 and defining the reflective region RA and the transmissive region TA of the sub-pixel region.

The gate line 2 and the data line 14 define a sub pixel area in which the pixel electrode 22 is formed by crossing the interlayer insulating layer 36 therebetween. The storage line 4 is formed alongside the gate line 2 to cross the data line 14 with the interlayer insulating layer 36 therebetween.

The NMOS TFT 15 supplies the video signal of the data line 14 to the pixel electrode 22 in response to the gate signal of the gate line 2. For this purpose, the NMOS TFT 15 includes a gate electrode 6 connected to the gate line 2, a source electrode 16 connected to the data line 14, a drain electrode 18 connected to the pixel electrode 22, The active layer 8 which forms a channel between the source electrode 16 and the drain electrode 18 is provided. The active layer 8 is formed on the insulating substrate 30 with the buffer film 32 therebetween. The active layer 8 is formed of an LTPS thin film, and a dopant source having n + impurities is formed between the channel region 8C overlapping the gate electrode 6 with the gate insulating layer 34 therebetween, and the channel region 8C interposed therebetween. A region 8S and a drain region 8D are provided. The source region 8S and the drain region 8D of the active layer 8 are connected to the source electrode 16 and the drain electrode through each of the contact holes 12S and 12D passing through the interlayer insulating film 36 and the gate insulating film 34. It is connected with 18, respectively. The active layer 8 further includes a lightly doped drain (LDD) region (not shown) in which n- impurity is implanted between the channel region 8C, the source region 8S, and the drain region 8D to reduce the off current. It may be provided.

The organic insulating film 38 formed on the NMOS TFT 15 includes a transmission hole 40 formed in the transmission area TA along with a third contact hole 20 exposing the drain electrode 18. The transmission hole 40 compensates for the difference in the optical path between the external light emitted through the liquid crystal layer twice in the reflection area RA and the internal light emitted through the liquid crystal layer once in the transmission area TA. The through hole 40 may pass through the organic insulating layer 38 and the interlayer insulating layer 36 to expose the gate insulating layer 34, or may be formed through the gate insulating layer 34. An inorganic insulating film may be further formed on and / or under the organic insulating film 38.

The pixel electrode 22 is formed in each sub pixel region via the organic insulating layer 38 and the transmission hole 40 and is connected to the drain electrode 18 through the contact hole 20. The pixel electrode 22 is formed of a transparent conductive material having a high transmittance to transmit internal light from the backlight unit. The reflective electrode 24 is formed in the reflective region RA of each sub pixel region and is connected to the drain electrode 18 through the pixel electrode 22 below it. In each sub-pixel region, the region where the reflective electrode 24 is formed is a region where the reflective electrode 24 is not formed, that is, the pixel electrode 22 is exposed through the through hole of the reflective electrode 24. The area is defined as the transmission area TA. The reflective electrode 24 is formed of a conductive material having high reflectance to reflect external light. In order to increase the reflection efficiency, the surface of the organic insulating film 38 may be formed to have an embossed surface so that the reflective electrode 24 has an embossed surface. The outer portion of the reflective electrode 22 is formed to overlap one side of the gate line 2 and the data line 14 and is formed to cover the NMOS TFT 15 and the storage capacitor Cst. The pixel electrode 22 and the reflective electrode 24 charge a data signal supplied through the NMOS TFT 15 to generate a potential difference with a common electrode formed on a color filter substrate (not shown). Due to this potential difference, the liquid crystal filled between the thin film transistor substrate and the color filter substrate is rotated by dielectric anisotropy so that the amount of reflection of external light incident on the reflection region via the color filter substrate is adjusted, and passes through the pixel electrode 22 from the backlight unit. The amount of internal light incident thereon is adjusted.

The storage capacitor Cst is formed so that the storage line 4 extends from the active layer 8 and overlaps the storage lower electrode 10 made of the LTPS thin film doped with n + impurities and the gate insulating layer 34 therebetween. The storage capacitor Cst compensates for the off leakage current of the NMOS TFT 15 so that the pixel electrode 22 and the reflective electrode 24 can maintain a constant voltage.

3 is a cross-sectional view showing a CMOS TFT, that is, an NMOS and a PMOS TFT, formed in a driving circuit region of an LTPS thin film transistor substrate according to the present invention.

The NMOS TFT 25 of the drive circuit shown in FIG. 3 has the same configuration as the NMOS TFT 15 in the display area shown in FIG. The PMOS TFT 45 overlaps the channel region 48C of the active layer 48 with the active layer 48 formed on the buffer layer 32 on the insulating substrate 30 and the gate insulating layer 34 interposed therebetween. A source electrode connected to the source region 48S and the drain region 48D of the active layer 48, respectively, through the gate electrode 46 and the contact holes 52S and 52D passing through the interlayer insulating layer 36. 56 and a drain electrode 58. The source region 46S and the drain region 48 of the active layer 48 of the PMOS TFT 45 are formed by doping with p impurities.

In the transflective LTPS liquid crystal display according to the exemplary embodiment of the present invention, the patterning process of the LTPS thin film forming the active layers 8 and 48 and the storage lower electrode 10, and doping n + impurities to the storage lower electrode 10 only. Is performed in one mask process using a diffraction exposure mask. Accordingly, in the present invention, since the number of mask processes is reduced, the process can be simplified to reduce manufacturing costs. Hereinafter, a method of manufacturing a thin film transistor substrate of a transflective LTPS liquid crystal display according to an exemplary embodiment of the present invention will be described in detail.

4A to 4C are plan views and cross-sectional views illustrating a first mask process in a method of manufacturing an LTPS thin film transistor substrate according to an exemplary embodiment of the present invention, and FIGS. 5A to 5C specifically illustrate a first mask process of the present invention. It is sectional drawing for description.

4A through 4C, the buffer layer 32 is formed on the insulating substrate 30, and the active layers 8 and 48 of the display region and the driving circuit region are formed on the buffer layer 32 by a first mask process. The storage lower electrode 10 integrated with the active layer 8 of the display area is formed.

Specifically, as shown in FIG. 5A, the buffer film 32 and the LTPS thin film 7 are stacked on the insulating substrate 30. The buffer layer 32 is formed by depositing an inorganic insulating material such as silicon oxide on the insulating substrate 30 by a deposition method such as plasma enhanced chemical vapor deposition (PECVD). The LTPS thin film 7 forms an amorphous silicon thin film on the buffer film 32 by PECVD or the like, and then crystallizes by laser annealing or the like to form the LTPS thin film 7. Dehydrogenation may be further performed to remove hydrogen atoms present in the amorphous silicon thin film before laser crystallization. Subsequently, a photoresist pattern 60 having a step is formed on the LTPS thin film 7 by a photolithography process using the first mask 70, which is a diffraction exposure mask. The photoresist pattern 60 may include a first photoresist pattern 60A corresponding to a blocking portion in which the blocking pattern 74 is formed on the substrate 72 of the mask 70, and a plurality of slits 76 in the blocking pattern 74. ) Is formed of a second photoresist pattern 60B having a thickness thinner than that of the first photoresist pattern 60A. By patterning the LTPS thin film 7 by an etching process using the photoresist pattern 60 as a mask, the active layer 8 and the storage lower electrode 10 are formed as shown in FIG. 5B. The photoresist pattern 60 is ashed to remove the second photoresist pattern 60B and the thickness of the first photoresist pattern 60A is reduced to expose the storage lower electrode 10 as shown in FIG. 5C. And then doping with n + impurities to make the lower storage electrode 10 conductive. The reduced first photoresist pattern 60A is then removed by a strip process.

6A to 6C are plan views and cross-sectional views illustrating second and third mask processes in a method of manufacturing an LTPS thin film transistor substrate according to an exemplary embodiment of the present invention, and FIGS. 7A and 7B illustrate second and third mask processes. Sectional drawing for demonstrating concretely.

6A through 6C, a gate insulating layer 34 is formed on the buffer layer 32 on which the active layers 8 and 48 and the storage lower electrode 10 are formed, and the second and second layers are formed on the gate insulating layer 34. A gate metal pattern including the gate line 2, the gate electrodes 6 and 46, and the storage line 4 in a three-mask process, and source and drain regions 8S and 8D doped with n + impurities in the active layer 8. Source and drain regions 48S and 48D doped with p impurities are formed in the active layer 48.

The gate insulating layer 34 is formed by depositing an inorganic insulating material such as silicon oxide on the buffer layer 32 on which the active layers 8 and 48 and the storage lower electrode 10 are formed by full deposition. Subsequently, the gate metal layer is formed on the gate insulating film 34 by a deposition method such as a sputtering method. As the gate metal layer, molybdenum (Mo), aluminum (Al), chromium (Cr), and the like and alloys thereof are laminated and used in a single layer or a multilayer structure. Next, the gate metal layer is patterned by a photolithography process and an etching process using a second mask to form a gate metal pattern including the gate line 2, the gate electrodes 6 and 46, and the storage line 10. In this case, the gate electrode 46 overlapping the active layer 48 of the driving circuit region is formed to have a large area so as to completely cover the active layer 48 as shown in FIG. 7A. The source region 8S and the drain region 8D of the active layer 8 doped with N + impurities are doped by doping N + impurities into the non-overlapping active layer 8 with the gate electrode 6 using the gate metal pattern as a mask. To form. In this case, the N + impurity may be doped while the photoresist pattern remains on the gate metal pattern.

Next, a photoresist pattern 80 is formed by a photolithography process using a third mask to repattern the gate electrode 46 of the driving circuit region, as shown in FIG. 7B, and then non-overlapping with the gate electrode 46. By doping the P impurity in the active layer 46, the source region 48S and the drain region 48D doped with impurities are formed. The photoresist pattern 80 is removed by a strip process.

8A through 8C are plan views and cross-sectional views illustrating a fourth mask process in a method of manufacturing an LTPS thin film transistor substrate according to an exemplary embodiment of the present invention.

8A to 8C, an interlayer insulating layer 36 including a plurality of contact holes 12S, 12D, 52S, and 52D is formed in a fourth mask process. The interlayer insulating film 36 is formed by depositing an inorganic insulating material such as silicon oxide, silicon nitride, or the like on the gate insulating film 34 on which the gate metal pattern is formed by the entire deposition method, such as PECVD. Subsequently, the source regions 8S and 48S and the drain regions 8D and 48D of the active layers 8 and 48 penetrate through the interlayer insulating layer 36 and the gate insulating layer 34 by a photolithography process and an etching process using a fourth mask. A plurality of contact holes 12S, 12D, 52S, and 52D are formed to expose each of the plurality of contact holes.

9A to 9C are plan views and cross-sectional views illustrating a fifth mask process in the method of manufacturing the LTPS thin film transistor substrate according to the exemplary embodiment of the present invention.

9A through 9C, a source / drain metal pattern including a data line 14, source electrodes 16 and 56, and drain electrodes 18 and 58 on an interlayer insulating layer 36 in a fifth mask process. Is formed. The source / drain metal pattern is formed by forming a source / drain metal layer on the interlayer insulating layer 36 by a deposition method such as sputtering, and then patterning the source / drain metal layer by a photolithography process and an etching process using a fifth mask. The source electrode 16 and the drain electrode 18 are connected to the source region 8S and the drain region 8D of the active layer 8 through the contact holes 12S and 12D, respectively, so that the display region and the driving circuit region may be connected to each other. NMOS TFTs 15 and 25 are formed. The source electrode 56 and the drain electrode 58 are connected to the source region 48S and the drain region 48D of the active layer 48 through the contact holes 52S and 52D, respectively, so that the PMOS TFTs of the driving circuit region are formed. Form 45.

10A to 10C are plan views and cross-sectional views illustrating a sixth mask process in the method of manufacturing the LTPS thin film transistor substrate according to the exemplary embodiment of the present invention.

10A through 10C, an organic insulating layer 38 including a contact hole 20 and a transmission hole 40 is formed on the interlayer insulating layer 38 on which the source / drain metal pattern is formed in the sixth mask process. . The organic insulating layer 38 is formed by coating an organic insulating material such as an acryl-based organic compound, BCB, or PFCB by spin coating, spinless coating, or the like. Subsequently, a contact hole 20 and a through hole 40 penetrating the organic insulating layer 38 are formed by a photolithography process and an etching process using a sixth mask. In this case, an inorganic insulating layer may be additionally formed on and / or under the organic insulating layer 38, and the contact hole 20 and the transmission hole 40 may be formed to penetrate the added inorganic insulating layer. Furthermore, the transmission hole 40 may extend to penetrate the interlayer insulating film 34 or the gate insulating film 32.

11A and 11B are plan views and cross-sectional views illustrating a seventh mask process in a method of manufacturing an LTPS thin film transistor substrate according to an exemplary embodiment of the present invention.

11A and 11B, the pixel electrode 22 passing through the organic insulating layer 38 and the transmission hole 40 is formed in the seventh mask process to be connected to the drain electrode 8 through the contact hole 20. do. The pixel electrode 22 is formed on the organic insulating film 38 and the gate insulating film 32 by a deposition method such as sputtering, and then patterned by a photolithography process and an etching process using a seventh mask. Is formed. As the transparent conductive layer, indium tin oxide (ITO), tin oxide (TO), indium zinc oxide (IZO), or ITZO are used.

12A and 12B are plan views and cross-sectional views illustrating an eighth mask process in a method of manufacturing an LTPS thin film transistor substrate according to an exemplary embodiment of the present invention.

12A and 12B, the reflective electrode 24 is formed on the organic insulating layer 38 on which the pixel electrode 22 is formed in the eighth mask process. The reflective electrode 24 is formed on the pixel electrode 22 and the organic insulating layer 38 by forming a metal layer having good reflectivity by a deposition method such as sputtering, and then patterning each sub pixel region by patterning the photolithography and etching processes using an eighth mask. And a reflection area RA and a transmission area TA.

As described above, the method for manufacturing the LTPS thin film transistor substrate according to the present invention includes the LTPS thin film patterning process of forming the active layers 8 and 48 and the storage lower electrode 10 using a diffraction exposure mask, and the storage lower electrode 10. By performing the step of doping the N + impurities in one mask process, the number of mask processes can be reduced to eight mask processes. The method of manufacturing the LTPS thin film transistor substrate of the present invention is similarly applied to the method of manufacturing the transmissive LTPS thin film transistor substrate to which the transmission hole 40 of the reflective electrode 24 and the organic insulating film 38 is not applied.

As described above, in the method of manufacturing the liquid crystal display according to the present invention, a mask process is performed by performing a LTPS thin film patterning process using a diffraction exposure mask and a process of forming a storage lower electrode by doping N + impurities in one mask process. The total number of mask processes can be reduced from the existing nine mask processes to eight mask processes. As a result, it is possible to simplify the process by reducing the number of processes to improve productivity and to increase the manufacturing cost.

Those skilled in the art will appreciate that various changes and modifications can be made without departing from the technical spirit of the present invention. Therefore, the technical scope of the present invention should not be limited to the contents described in the detailed description of the specification but should be defined by the claims.

Claims (7)

Forming a polysilicon thin film on the insulating substrate; Forming a photoresist pattern on the polysilicon thin film; Patterning the polysilicon thin film using the photoresist pattern as a mask; Removing a portion of the photoresist pattern; And doping an impurity in a portion of the polysilicon thin film exposed by removing the photoresist pattern. The method of claim 1, Forming the photoresist pattern is Forming a photoresist pattern having a step with a difference in thickness by using a diffraction exposure mask. The method of claim 2, Removing a portion of the photoresist pattern is And removing a region of a relatively low thickness from the stepped photoresist pattern. The method of claim 3, wherein Patterning the polysilicon thin film to form an active layer of a thin film transistor and a storage lower electrode connected to the active layer; And the dopant is doped into the lower storage electrode. The method of claim 4, wherein Forming a first insulating film on the insulating substrate on which the active layer and the lower storage electrode are formed; Forming a gate electrode overlapping a portion of the active layer, a gate line connected to the gate electrode, and a storage line overlapping the lower storage electrode on the first insulating layer; Forming a source region and a drain region by doping an impurity in a region not overlapped with the gate electrode in the active layer; Forming a second insulating film on the first insulating film on which the gate electrode, the gate line, and the storage line are formed, and exposing a source region and a drain region of the active layer, respectively; Forming a source electrode and a drain electrode connected to the source and drain regions of the active layer, respectively, and a data line connected to the source electrode; Forming a third insulating film on the second insulating film on which the source electrode, the drain electrode, and the data line are formed and exposing the drain electrode; And forming a pixel electrode connected to the drain electrode on the second insulating film. The method of claim 5, Doping the active layer with impurities And doping a first impurity in some active layers and a second impurity in the remaining active layers in the plurality of active layers. The method according to any one of claims 5 and 6, Forming an organic insulating film with the third insulating film and forming a through hole penetrating the organic insulating film; And forming a reflective electrode on the third insulating film on which the pixel electrode is formed to expose the pixel electrode formed in the transmission hole.

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