KR20070079140A - Display device - Google Patents

Abstract

A display device is provided to compensate for voltage drop due to a line resistance of a scanning signal line by adjusting the proportion of a width to a length of a channel in a pixel. A plurality of pixels(PX) include switching transistors that transmit a data signal to a liquid crystal capacitor and are arranged in a matrix form. A gate driver unit(400) is formed in a column direction at one side of the pixels and supplies a scanning signal to the pixels. A data driver unit(500) supplies the data signal to the pixels. The switching transistors of the plurality of pixels forming a row have different device characteristics. The device characteristics of the switching transistors vary depending on the proportion of a width to a length of a channel. The proportion of the width to the length of the channel becomes larger as it is farther from the gate driver unit.

Description

Display device {DISPLAY DEVICE}

1 is a block diagram of a liquid crystal display according to an exemplary embodiment of the present invention.

2 is an equivalent circuit diagram of one pixel of a liquid crystal display according to an exemplary embodiment of the present invention.

3 is a layout view of a liquid crystal display according to an exemplary embodiment of the present invention.

4 is a cross-sectional view of the liquid crystal display of FIG. 3 taken along the line IV-IV.

FIG. 5 is a cross-sectional view of the liquid crystal display of FIG. 3 taken along the line VV. FIG.

6 is a signal waveform diagram illustrating an operating characteristic of a transistor of a liquid crystal display according to an exemplary embodiment of the present invention.

The present invention relates to a liquid crystal display device.

In recent years, with the reduction in weight and thickness of personal computers and televisions, display devices are also required to be lighter and thinner, and cathode ray tubes (CRTs) are being replaced by flat panel displays.

Such flat panel displays include liquid crystal displays (LCDs), field emission displays (FEDs), organic light emitting displays, plasma display panels (PDPs), and the like. There is this.

In general, in an active matrix flat panel display, a plurality of pixels are arranged in a matrix form, and an image is displayed by controlling the light intensity of each pixel according to given luminance information. Among them, the liquid crystal display includes two display panels including a pixel electrode and a common electrode, and a liquid crystal layer having dielectric anisotropy interposed therebetween. The liquid crystal display device applies an electric field to the liquid crystal layer, and adjusts the intensity of the electric field to adjust the transmittance of light passing through the liquid crystal layer to obtain a desired image.

In such a liquid crystal display, as the size increases, a problem in which the area near the gate driver becomes brighter (Gate Whitish) is problematic. This is because a region far from the gate driver in the display panel receives a lower voltage according to a signal delay and a voltage drop according to the line resistance of the scan signal line for transmitting the scan signal. In order to solve this problem, a method of applying a kick back voltage when a scan signal of a square wave falls has applied a scan signal having the same waveform to the entire display panel.

However, when the scan signal of the square wave falls, the method of applying the kickback voltage to the entire display panel to apply the kickback voltage requires a separate circuit for applying the kickback voltage, thereby increasing the unit cost.

Accordingly, an object of the present invention is to provide a liquid crystal display device capable of compensating for the influence of the line resistance of the scan signal line.

In accordance with an aspect of the present invention, a display device includes a liquid crystal capacitor and a switching transistor configured to transfer a data signal to the liquid crystal capacitor, and includes a plurality of pixels arranged in a matrix and one side of the pixels. And a gate driver for supplying a scan signal to the pixel, and a data driver for supplying the data signal to the pixel, wherein the switching transistors of the plurality of pixels forming a row have different device characteristics. Have

Device characteristics of the switching transistor may vary depending on the ratio of the width to the length of the channel.

The ratio of the width to the length of the channel may increase as the distance from the gate driver increases.

The ratio of the width to the length of the channel of the switching transistor of the pixels forming a column may be the same.

The switching transistor up to a predetermined distance from the gate driver may have a width with respect to the length of the channel reduced at a predetermined rate with respect to the switching transistor outside the predetermined distance.

The switching transistor may be an n-type thin film transistor.

DETAILED DESCRIPTION Embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art may easily implement the present invention.

In the drawings, the thickness of layers, films, panels, regions, etc., are exaggerated for clarity. Like parts are designated by like reference numerals throughout the specification. When a part of a layer, film, region, plate, etc. is said to be "on" another part, this includes not only the other part being "right over" but also another part in the middle. On the contrary, when a part is "just above" another part, there is no other part in the middle.

A display device according to an embodiment of the present invention will now be described in detail with reference to the accompanying drawings.

1 is a block diagram of a liquid crystal display according to an exemplary embodiment of the present invention, which is a block diagram of a liquid crystal display including pixels, and FIG. 2 is a block diagram of one pixel of the liquid crystal display according to the exemplary embodiment of the present invention. Equivalent circuit diagram.

As shown in FIG. 1, a liquid crystal display according to an exemplary embodiment of the present invention includes a liquid crystal panel assembly 300, a gate driver 400, a data driver 500, and a data driver connected thereto. And a gray voltage generator 550 connected to the signal 500, and a signal controller 600 for controlling the gray voltage generator 550.

The liquid crystal panel assembly 300, when viewed as an equivalent circuit, includes a plurality of display signal lines G ₁ -G _n , D ₁ -D _m , and a plurality of pixels PX connected thereto and arranged in a substantially matrix form. It includes.

The display signal lines G ₁ -G _n and D ₁ -D _{m each} include a plurality of scan signal lines G ₁ -G _n transmitting scan signals and a plurality of data lines D ₁ -D _m transferring data signals. Include.

The scan signal lines G ₁ -G _n extend substantially in the row direction and are substantially parallel to each other, and the data lines D ₁ -D _m extend substantially in the column direction and are substantially parallel to each other.

As shown in Fig. 2, each pixel PX, for example, the i-th (i = 1, 2, ..., n) video scanning signal line G _i and the j-th (j = 1, 2,. .., m) The pixel PX connected to the data line D _j includes a switching element Q connected to the signal lines G _i and D _j , a liquid crystal capacitor C _lc , and a storage capacitor connected thereto. (storage capacitor) (C _st ). The holding capacitor C _st can be omitted as necessary.

The switching element Q is a three-terminal element such as a thin film transistor provided in the lower panel 100, the control terminal of which is connected to the scan signal line G _i , and the input terminal of which is connected to the data line D _j . The output terminal is connected to the liquid crystal capacitor Clc and the storage capacitor Cst.

The liquid crystal capacitor Clc has two terminals, the pixel electrode 191 of the lower panel 100 and the common electrode 270 of the upper panel 200, and the liquid crystal layer 3 between the two electrodes 191 and 270 is a dielectric material. Function as.

The storage capacitor Cst, which serves as an auxiliary part of the liquid crystal capacitor Clc, is formed by overlapping a separate signal line (not shown) and the pixel electrode 191 provided on the lower panel 100 with an insulator interposed therebetween. A predetermined voltage such as the common voltage Vcom is applied to the separate signal line. However, the storage capacitor Cst may be formed such that the pixel electrode 191 overlaps the shear scan signal line immediately above the insulator.

3 is a layout view of a liquid crystal display according to an exemplary embodiment, and FIGS. 4 and 5 are cross-sectional views illustrating the liquid crystal display of FIG. 3 taken along lines IV-IV and V-V.

A plurality of gate lines 121 and a plurality of storage electrode lines 131 are formed on an insulating substrate 110 made of transparent glass or plastic.

The scan signal line 121 transmits a scan signal and mainly extends in a horizontal direction. Each scan signal line 121 includes a plurality of gate electrodes 124 protruding downward and an end portion 129 having a large area for connection with another layer or an external driving circuit. A gate driving circuit (not shown) for generating a scan signal is mounted on a flexible printed circuit film (not shown) attached to the substrate 110, or directly mounted on the substrate 110, or It may be integrated into the substrate 110. When the gate driving circuit is integrated on the substrate 110, the scan signal line 121 may extend to be directly connected to the gate driving circuit.

The storage electrode line 131 receives a predetermined voltage, and includes a stem line extending substantially in parallel with the scan signal line 121 and a plurality of pairs of first and second storage electrodes 133a and 133b separated therefrom. Each of the storage electrode lines 131 is positioned between two adjacent scan signal lines 121, and the stem line is closer to the lower side of the two scan signal lines 121. Each of the sustain electrodes 133a and 133b has a fixed end connected to the stem line and a free end opposite thereto. The fixed end of the first sustain electrode 133a has a large area, and its free end is divided into two parts, a straight portion and a bent portion. However, the shape and arrangement of the storage electrode line 131 may be modified in various ways.

The scan signal line 121 and the sustain electrode line 131 may be formed of aluminum-based metal such as aluminum (Al) or aluminum alloy, silver-based metal such as silver (Ag) or silver alloy, copper-based metal such as copper (Cu) or copper alloy, or molybdenum ( It may be made of molybdenum-based metals such as Mo) or molybdenum alloy, chromium (Cr), tantalum (Ta) and titanium (Ti). However, they may have a multilayer structure including two conductive films (not shown) having different physical properties. One of the conductive films is made of a metal having low resistivity, such as aluminum-based metal, silver-based metal, or copper-based metal, so as to reduce signal delay or voltage drop. In contrast, other conductive films are made of other materials, particularly materials having excellent physical, chemical, and electrical contact properties with indium tin oxide (ITO) and indium zinc oxide (IZO), such as molybdenum-based metals, chromium, tantalum, and titanium. Good examples of such a combination include a chromium bottom film, an aluminum (alloy) top film, and an aluminum (alloy) bottom film and a molybdenum (alloy) top film. However, the gate line 121 and the storage electrode line 131 may be made of various other metals or conductors.

Side surfaces of the scan signal line 121 and the sustain electrode line 131 are inclined with respect to the surface of the substrate 110, and the inclination angle thereof is preferably about 30-80 degrees.

A gate insulating layer 140 made of silicon nitride (SiNx) or silicon oxide (SiOx) is formed on the scan signal line 121 and the storage electrode line 131.

A plurality of linear semiconductors 151 made of hydrogenated amorphous silicon (hereinafter referred to as a-Si) or polysilicon are formed on the gate insulating layer 140. The linear semiconductor 151 mainly extends in the longitudinal direction and includes a plurality of projections 154 extending toward the gate electrode 124. The linear semiconductor 151 is wide in the vicinity of the scan signal line 121 and the sustain electrode line 131 and covers them widely.

A plurality of linear and island ohmic contacts 161 and 165 are formed on the semiconductor 151. The ohmic contacts 161 and 165 may be made of a material such as n + hydrogenated amorphous silicon in which n-type impurities such as phosphorus are heavily doped, or may be made of silicide. The linear ohmic contact 161 has a plurality of protrusions 163, and the protrusion 163 and the island-type ohmic contact 165 are paired and disposed on the protrusion 154 of the semiconductor 151.

Side surfaces of the semiconductor 151 and the ohmic contacts 161 and 165 are also inclined with respect to the surface of the substrate 110 and have an inclination angle of about 30-80 degrees.

A plurality of data lines 171 and a plurality of drain electrodes 175 are formed on the ohmic contacts 163 and 165 and the gate insulating layer 140.

The data line 171 transmits a data signal and mainly extends in the vertical direction to cross the gate line 121. Each data line 171 also crosses the storage electrode line 131 and runs between adjacent sets of storage electrodes 133a and 133b. Each data line 171 includes a plurality of source electrodes 173 extending toward the gate electrode 124 and end portions 179 having a large area for connection with another layer or an external driving circuit. A data driving circuit (not shown) for generating a data signal is mounted on a flexible printed circuit film (not shown) attached to the substrate 110, directly mounted on the substrate 110, or integrated in the substrate 110. Can be. When the data driving circuit is integrated on the substrate 110, the data line 171 may be extended to be directly connected to the data driving circuit.

The drain electrode 175 is separated from the data line 171 and faces the source electrode 173 around the gate electrode 124. Each drain electrode 175 includes one wide end and the other end having a rod shape. The wide end portion overlaps the storage electrode line 131, and the rod-shaped end portion is partially surrounded by the source electrode 173 bent in a J shape.

One gate electrode 124, one source electrode 173, and one drain electrode 175 together with the protrusion 154 of the semiconductor 151 form one switching transistor Q, and the switching transistor Q A channel of is formed in the protrusion 154 between the source electrode 173 and the drain electrode 175. The channel has a width W and a length L, and the characteristic of the device is determined by the ratio of the width W to the length L.

The data line 171 and the drain electrode 175 are preferably made of a refractory metal such as molybdenum, chromium, tantalum, and titanium, or an alloy thereof, and include a refractory metal film (not shown) and a low resistance conductive film. It may have a multilayer structure including (not shown). Examples of the multilayer structure include a double layer of chromium or molybdenum (alloy) lower layer and an aluminum (alloy) upper layer, and a triple layer of molybdenum (alloy) lower layer and aluminum (alloy) interlayer and molybdenum (alloy) upper layer. However, the data line 171 and the drain electrode 175 may be made of various metals or conductors.

The side of the data line 171 and the drain electrode 175 may be inclined at an inclination angle of about 30-80 degrees with respect to the surface of the substrate 110.

The ohmic contacts 161 and 165 exist only between the semiconductor 151 below and the data line 171 and the drain electrode 175 thereon, and lower the contact resistance therebetween. Although the linear semiconductor 151 is narrower than the data line 171 in most places, as described above, the width of the linear semiconductor 151 is widened at the portion where it meets the gate line 121 to smooth the profile of the surface, thereby disconnecting the data line 171. prevent. The semiconductor 151 has an exposed portion between the source electrode 173 and the drain electrode 175, and not covered by the data line 171 and the drain electrode 175.

A passivation layer 180 is formed on the data line 171, the drain electrode 175, and the exposed portion of the semiconductor 151. The passivation layer 180 may be made of an inorganic insulator or an organic insulator, and may have a flat surface. Examples of the inorganic insulator include silicon nitride and silicon oxide. The organic insulator may have photosensitivity and the dielectric constant is preferably about 4.0 or less. However, the passivation layer 180 may have a double layer structure of the lower inorganic layer and the upper organic layer so as not to damage the exposed portion of the semiconductor 151 while maintaining excellent insulating properties of the organic layer.

In the passivation layer 180, a plurality of contact holes 182 and 185 exposing the end portion 179 and the drain electrode 175 of the data line 171 are formed, respectively, and the passivation layer 180 and the gate insulating layer are formed. In the 140, a plurality of contact holes 181 exposing the end portion 129 of the gate line 121 and a plurality of contact holes 183a exposing a part of the storage electrode line 131 near the fixed end of the first storage electrode 133a. And a plurality of contact holes 183b exposing the protruding portion of the free end of the first storage electrode 133a.

A plurality of pixel electrodes 191, a plurality of overpasses 83, and a plurality of contact assistants 81 and 82 are formed on the passivation layer 180. They may be made of a transparent conductive material such as ITO or IZO or a reflective metal such as aluminum, silver, chromium or an alloy thereof.

The pixel electrode 191 is physically and electrically connected to the drain electrode 175 through the contact hole 185 and receives a data voltage from the drain electrode 175. The pixel electrode 191 to which the data voltage is applied generates an electric field together with the common electrode 270 of the other display panel 200 to which the common voltage is applied, thereby generating an electric field between the two electrodes 191 and 270. The direction of liquid crystal molecules (not shown) of the liquid crystal layer 3 is determined. The polarization of light passing through the liquid crystal layer 3 varies according to the direction of the liquid crystal molecules determined as described above. The pixel electrode 191 and the common electrode 270 form a liquid crystal capacitor Clc to maintain an applied voltage even after the thin film transistor is turned off.

The pixel electrode 191 overlaps the storage electrode line 131 including the storage electrodes 133a and 133b. A capacitor in which the pixel electrode 191 and the drain electrode 175 electrically connected thereto overlap with the storage electrode line 131 is called a "storage capacitor", and the storage capacitor enhances the voltage holding capability of the liquid crystal capacitor. .

The contact auxiliary members 81 and 82 are connected to the end portion 129 of the gate line 121 and the end portion 179 of the data line 171 through the contact holes 181 and 182, respectively. The contact auxiliary members 81 and 82 compensate for and protect the adhesion between the end portion 129 of the gate line 121 and the end portion 179 of the data line 171 and the external device. The connecting leg 83 crosses the gate line 121 and exposes the exposed portion of the storage electrode line 131 and the storage electrode through contact holes 183a and 183b positioned on opposite sides with the gate line 121 interposed therebetween. 133b) is connected to the exposed end of the free end. The storage electrode lines 131 including the storage electrodes 133a and 133b may be used together with the connecting legs 83 to repair defects in the gate line 121, the data line 171, or the thin film transistor.

Next, the common electrode display panel 200 will be described with reference to FIGS. 4 and 5.

A light blocking member 220 is formed on an insulating substrate 210 made of transparent glass or the like. The light blocking member 220 is also called a black matrix and prevents light leakage. The light blocking member 220 faces the pixel electrode 191 and has a plurality of openings having substantially the same shape as the pixel electrode 191, and prevents light leakage between the pixel electrodes 191. However, the light blocking member 220 may include a portion corresponding to the scan signal line 121 and the data line 171 and a portion corresponding to the thin film transistor.

A plurality of color filters 230 is also formed on the substrate 210. The color filter 230 is mostly present in an area surrounded by the light blocking member 220, and may extend in the vertical direction along the column of the pixel electrodes 191. Each color filter 230 may display one of primary colors such as three primary colors of red, green, and blue.

An overcoat 250 is formed on the color filter 230 and the light blocking member 220. The overcoat 250 may be made of an (organic) insulator, which prevents the color filter 230 from being exposed and provides a flat surface. The overcoat 250 may be omitted.

The common electrode 270 is formed on the overcoat 250. The common electrode 270 is made of a transparent conductor such as ITO or IZO.

On the other hand, in order to implement color display, each pixel PX uniquely displays one of the primary colors (spatial division) or each pixel PX alternately displays the primary colors over time (time division). The desired color is recognized by the spatial and temporal sum of these primary colors. Examples of the primary colors include three primary colors such as red, green, and blue. 2 and 3 show that each pixel PX includes a color filter 230 representing one of the primary colors in an area of the upper panel 200 corresponding to the pixel electrode 191 as an example of spatial division. Giving. Unlike FIGS. 2 and 3, the color filter 230 may be formed above or below the pixel electrode 191 of the lower panel 100.

The switching transistor Q of the display panel 300 has different device characteristics. The switching transistors Q of the pixels PX forming a row have a different ratio of the width W to the length L of the channel, and the longer the pixel PX from the gate driver 400, the longer the channel length ( The ratio of the width W to L) becomes large. In this case, the ratio of the width W to the length L of the channel of the switching transistors Q of the pixels PX forming the column is constant.

Referring back to FIG. 1, the gray voltage generator 550 generates two gray voltage sets (or reference gray voltage sets) related to the transmittance of the pixel PX. One of the two sets has a positive value for the common voltage Vcom and the other set has a negative value.

The gate driver 400 is connected to the scan signal lines G ₁ -G _n of the liquid crystal panel assembly 300 and includes a combination of a high voltage Von for turning on the switching transistor Q and a low voltage Voff for turning off the switching transistor Q. The scan signal is applied to the scan signal lines G ₁ -G _n .

The data driver 500 is connected to the image data lines D ₁ -D _m of the liquid crystal panel assembly 300 and selects a gray voltage from the gray voltage generator 550 and uses the data line D as a data signal. ₁ -D _m ).

The signal controller 600 controls the gate driver 400, the data driver 500, the sensing signal processor 800, and the like.

Each of the driving devices 400, 500, 550, 600, and 800 may be mounted directly on the liquid crystal panel assembly 300 in the form of at least one integrated circuit chip, or may be a flexible printed circuit film (not shown). It may be mounted on the liquid crystal panel assembly 300 in the form of a tape carrier package (TCP), or mounted on a separate printed circuit board (not shown). Alternatively, these driving devices 400, 500, 550, 600, 800 are connected to signal lines G ₁ -G _n , D ₁ -D _m , S ₁ -S _M , P ₁ -P _N and switching elements Q. The liquid crystal panel assembly 300 may be integrated with the liquid crystal panel assembly 300. In addition, the driving devices 400, 500, 550, 600, and 800 may be integrated into a single chip, in which case at least one of them or at least one circuit element constituting them may be outside the single chip.

6, the operation of the liquid crystal display will be described in detail.

The signal controller 600 receives input image signals R, G, and B and an input control signal for controlling the display thereof from an external graphic controller (not shown). The input control signal includes a vertical sync signal Vsync, a horizontal sync signal Hsync, a main clock MCLK, a data enable signal DE, and the like.

The signal controller 600 applies the input image signals R, G, and B to the operating conditions of the liquid crystal panel assembly 300 and the data driver 500 based on the input image signals R, G, and B and the input control signal. After appropriately processing and generating the gate control signal CONT1 and the data control signal CONT2, the gate control signal CONT1 is sent to the gate driver 400, and the data control signal CONT2 and the processed image signal ( DAT) to the data driver 500.

The gate control signal CONT1 includes a scan start signal STV indicating the start of scanning and at least one clock signal controlling the output period of the first high voltage Von. The gate control signal CONT1 may also further include an output enable signal OE that defines the duration of the first high voltage Von.

The data control signal CONT2 is a load signal LOAD and data for applying the image data signal to the horizontal synchronization start signal STH and the data lines D ₁ -D _m indicating the start of transmission of the group of image data DAT. It includes a clock signal HCLK. The data control signal CONT2 also inverts the voltage polarity of the image data signal relative to the common voltage Vcom (hereinafter referred to as "polarity of the image data signal" by reducing the "voltage polarity of the image data signal with respect to the common voltage"). It may further include an inversion signal RVS.

According to the data control signal CONT2 from the signal controller 600, the data driver 500 receives the digital image signal DAT for the group of pixels PX, and converts the digital image signal DAT into an analog data signal. After conversion to, apply it to the corresponding data lines D ₁ -D _m .

The gate driver 400 applies a high voltage Von to the scan signal lines G ₁ -G _n in response to the gate control signal CONT1 from the signal controller 600.

6 is a waveform diagram illustrating operating characteristics of a transistor of a liquid crystal display according to an exemplary embodiment of the present invention.

FIG. 6 shows the output current I _D against the source-drain voltage V _DS of a metal oxide semiconductor field effect transistor (MOSFET) such as a switching transistor Q. FIG.

Since the switching transistor Q is an analog switching element, it operates in a linear region, and when turned on, outputs an almost linear output current I _D with respect to the source-drain voltage V _DS .

This output current I _D is given by the following equation.

Where I _D is the output current, Φ _n is the electron mobility in the channel, C _ox is the capacitance of the gate insulating film, W is the width of the channel, L is the length of the channel, and V _GS is the gate-source voltage of the switching transistor, , Refers to the voltage level of the scan signal, and V _T refers to the threshold voltage of the switching transistor Q.

The switching transistor Q is turned on when the high voltage Von of the scan signal lines G ₁ -G _n is supplied to the control terminal. At this time, since the scan signal of the high voltage Von has a signal delay and a voltage drop due to the line resistance of the scan signal lines G ₁ -G _n , the pixel far from the gate driver 400 is lower than the high voltage Von. The voltage of the level is applied. As a result, the amount of output current I _D decreases, which may make it impossible to accurately transmit a data signal. However, the liquid crystal display of the present invention increases the ratio of the width (W) to the length (L) of the channel of the gate driver 400 and the far-away pixel PX in the display panel 300, thereby reducing the voltage of the scan signal. Nevertheless, the output current I _D is kept constant to transmit the data signal.

The liquid crystal display reduces the ratio of the width W to the length L of the channel of the pixel PX at a predetermined distance from the gate driver 400 at a predetermined ratio, and the remaining regions are formed in the same manner as in the related art. Similar effects can be obtained.

The difference between the voltage of the data signal applied to the pixel PX and the common voltage Vcom is shown as the charging voltage of the liquid crystal capacitor Clc, that is, the pixel voltage. The arrangement of the liquid crystal molecules varies according to the magnitude of the pixel voltage, thereby changing the polarization of light passing through the liquid crystal layer 3. The change in polarization is represented as a change in the transmittance of light by the polarizer attached to the liquid crystal panel assembly 300, and thus a desired image may be displayed.

This process is repeated in units of one horizontal period (also referred to as "1H" and equal to one period of the horizontal sync signal Hsync and the data enable signal DE), thereby all scan signal lines G ₁ -G _n. ), A high voltage Von is sequentially applied to the data signal to all the pixels PX to display an image of one frame.

When one frame ends, the next frame starts and the state of the inversion signal RVS applied to the data driver 500 is controlled so that the polarity of the data signal applied to each pixel PX is opposite to the polarity of the previous frame. (“Invert frame”). In this case, the polarity of the data signal flowing through one data line is changed according to the characteristics of the inversion signal (RVS) (eg, inverted row and inverted point) within one frame, or the polarity of the data signal applied to one pixel row is also different from each other. (Eg: nirvana, point inversion).

As described above, according to the present invention, the voltage drop according to the line resistance of the scan signal line can be compensated by adjusting the ratio of the width to the channel length of the pixel.

Although the preferred embodiments of the present invention have been described in detail above, the scope of the present invention is not limited thereto, and various modifications and improvements of those skilled in the art using the basic concepts of the present invention defined in the following claims are also provided. It belongs to the scope of rights.

Claims (6)

Liquid crystal capacitors, and A plurality of pixels arranged in a matrix, the switching transistor transferring a data signal to the liquid crystal capacitor, A gate driver formed on one side of the pixel in a column direction and supplying a scan signal to the pixel; A data driver supplying the data signal to the pixel Including; And a switching transistor of the plurality of pixels forming a row has different device characteristics. In claim 1, The device characteristic of the switching transistor is different depending on a ratio of width to length of a channel. In claim 2, The ratio of the width to the length of the channel increases as the distance from the gate driver increases. In claim 3, And a ratio of a width to a length of the channel of the switching transistor of the pixels forming a column is the same. In claim 4, And the switching transistor from the gate driver to a predetermined distance has a width with respect to the length of the channel reduced by a predetermined ratio with respect to the switching transistor outside the predetermined distance. In claim 5, And the switching transistor is an n type thin film transistor.

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