KR20070078898A - A method for manufacturing thin film transistor array panel - Google Patents

Abstract

A method for manufacturing a thin film transistor array panel is provided to simplify a manufacturing process by using a gravure printing method instead of an exposure and developing method using a light shielding mask. A gate line is formed on a substrate(110). A gate insulating layer(140) is formed on the gate line. An intrinsic amorphous silicon layer is formed on the gate insulating layer. An impurity amorphous silicon layer is formed on the intrinsic amorphous silicon layer. A data layer is deposited on the impurity amorphous silicon layer. A first etch mask pattern(400a) is formed on the data layer. The data layer is etched by using the first etch mask pattern as an etch mask. The intrinsic amorphous silicon layer and the impurity amorphous silicon layer are etched by using the first etch mask pattern as the etch mask. A second etch mask pattern(400b) is formed by ashing the first etch mask pattern. The amorphous silicon layer is etched by using the second etch mask pattern as an etch mask. The second etch mask pattern is eliminated. The first etch mask pattern is formed by using a gravure printing method.

Description

A manufacturing method of a thin film transistor array panel {A METHOD FOR MANUFACTURING THIN FILM TRANSISTOR ARRAY PANEL}

1 is a layout view of a thin film transistor array panel according to an exemplary embodiment of the present invention.

2 and 3 are cross-sectional views of the thin film transistor array panel of FIG. 1 taken along lines II-II and III-III, respectively.

4, 7, 24, and 27 are layout views sequentially illustrating a method of manufacturing a thin film transistor array panel according to an exemplary embodiment of the present invention.

5 and 6 are cross-sectional views illustrating the thin film transistor array panel of FIG. 4 taken along lines V-V and VI-VI.

8 and 9 are cross-sectional views of the thin film transistor array panel of FIG. 7 taken along the lines VIII-VIII and IX-IX.

10 to 23 are cross-sectional views sequentially showing the method of manufacturing the thin film transistor array panel of FIG. 7.

25 and 26 are cross-sectional views illustrating the thin film transistor array panel of FIG. 24 taken along lines XXV-XXV and XXVI-XXVI.

28 and 29 are cross-sectional views of the thin film transistor array panel of FIG. 27 taken along lines XXVIII-XXVIII and XXIX-XXIX.

30 is a schematic diagram of an etching mask pattern manufacturing apparatus according to an embodiment of the present invention.

31 to 42 are cross-sectional views sequentially shown according to a method of forming a gravure printing photosensitive layer according to an embodiment of the present invention.

43 to 48 are cross-sectional views sequentially shown according to a method of forming a gravure-printing photosensitive layer according to another embodiment of the present invention.

49 is a layout view of a thin film transistor array panel according to another exemplary embodiment of the present invention.

50 and 51 are cross-sectional views illustrating the thin film transistor array panel of FIG. 49 taken along lines XXXXX-XXXXX and XXXXXI-XXXXXI.

52 to 59 are cross-sectional views sequentially showing the method of manufacturing the thin film transistor array panel of FIG. 49.

<Description of Drawing>

81, 82 ... Contact auxiliary member 9a ... Substrate for supplying photosensitive member

14 ... Transfer roller 83 ... Connection leg

110 ... substrate

131, 132 ... hold electrode wires 133a, 133b ... hold electrode

121, 129 ... gate line 124 ... gate electrode

140 Gate insulating film 151, 154 Semiconductor

161, 163, 165 ... resistive contact layers 171, 179 ... data lines

173 Source electrode 175 Drain electrode

180 ... shield 181, 182, 185 ... contact hole

191 pixel electrode 189 protective film opening

400a, 400b, 400c ... etch mask pattern 400p, 400q, 400r ... mask

The present invention relates to an etching mask pattern formed by a gravure printing method and a method of manufacturing a thin film transistor array panel using the same.

The liquid crystal display is one of the most widely used flat panel display devices. The liquid crystal display includes two display panels on which a field generating electrode is formed and a liquid crystal layer interposed therebetween. It is a display device for adjusting the transmittance of light passing through the liquid crystal layer by changing the.

The thin film transistor array panel of the liquid crystal display includes a plurality of thin films including a gate layer, a data layer, and a semiconductor layer. After laminating each layer, the thin films are coated with a photoresist film and exposed and developed by using respective light blocking masks to form a photoresist pattern, and each layer is etched by using the photoresist pattern as an etch mask. Is formed. However, each time the number of masks is increased, processes such as exposure and development are added, thereby significantly increasing the manufacturing cost and time.

Accordingly, a technical problem to be solved by the present invention is to solve such a problem, and the liquid crystal display is manufactured by simply manufacturing an etching mask used for manufacturing a thin film transistor array panel for a liquid crystal display device as compared to an exposure and developing process using a light blocking mask. It is to provide a method that can reduce the manufacturing cost of the device.

A method of manufacturing a thin film transistor array panel according to an exemplary embodiment of the present invention may include forming a gate line on a substrate, laminating a gate insulating film on the gate line, laminating an intrinsic amorphous silicon layer on the gate insulating film, and forming the amorphous layer. Depositing an impurity amorphous silicon layer on the silicon layer, depositing a data layer on the impurity amorphous silicon layer, attaching a first etching mask pattern on the data layer, and using the first etching mask pattern as an etching mask Etching the data layer, etching an intrinsic amorphous silicon layer and an impurity amorphous silicon layer using the first etching mask pattern as an etching mask, and ashing the first etching mask pattern to form a second etching mask pattern And amorphous silicon using the second etching mask pattern as an etching mask. Step and the second comprising the step of removing the etching mask pattern, and wherein the first etching mask pattern for etching is formed by gravure printing.

The first etching mask pattern may include an upper portion and a lower portion, and the upper portion may be wider than the lower portion.

The attaching of the first etching mask pattern may include forming grooves on the substrate for supplying the first etching mask at a predetermined shape and at regular intervals, and filling the grooves with an etching mask pattern material to form a first etching mask pattern. And transferring the first etch mask pattern onto the transfer roller surface, and attaching the first etch mask pattern on the transfer roller surface to the substrate on which the data layer is formed.

In the method of manufacturing the thin film transistor array panel, the method may further include stacking a protective layer on the substrate, attaching a third etching mask pattern on the protective layer, and etching the protective layer using the third etching mask pattern as an etching mask. Forming an opening in which the electrode is to be formed, depositing a pixel electrode layer on the substrate to which the third etching mask pattern is attached, and removing the third etching mask pattern to form a pixel electrode pattern in the opening. Further comprising, the third etching mask pattern may be formed by gravure printing.

The third etching mask pattern may include an upper portion and a lower portion, and the upper portion may be wider than the lower portion.

The attaching of the third etching mask pattern may include forming grooves in a predetermined shape and at a predetermined interval on the third etching mask supply substrate, and filling the grooves with an etching mask pattern material to form a third etching mask pattern. The method may include transferring the third etch mask pattern to the transfer roller surface, and attaching the third etch mask pattern on the transfer roller surface to the substrate on which the protective layer is formed.

In another embodiment of the present invention, a method of manufacturing a thin film transistor array panel includes forming a gate line on a substrate, sequentially depositing a gate insulating layer, a semiconductor layer, and a data layer on the substrate, and patterning the semiconductor layer and the data layer. Forming a thin film transistor including a drain electrode, stacking a passivation layer on the substrate, attaching an etch mask pattern on the passivation layer, etching the passivation layer using the etch mask pattern as an etch mask, Forming an opening in which the pixel electrode is to be formed, depositing a pixel electrode layer on the substrate to which the etch mask pattern is attached, and removing the etch mask pattern to form an opening in the opening and connecting the drain electrode. Forming a pixel electrode pattern , And the etching mask pattern can be formed by gravure printing.

The etching mask pattern may include an upper portion and a lower portion, and the upper portion may be wider than the lower portion.

The attaching the etch mask pattern may include forming grooves in a predetermined shape and at a predetermined interval on the etching mask supply substrate, forming an etching mask pattern by filling an etching mask pattern material in the grooves, and etching the pattern. And transferring the etching mask pattern on the surface of the transfer roller onto the substrate on which the passivation layer is formed.

DETAILED DESCRIPTION Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art may easily implement the present invention. As those skilled in the art would realize, the described embodiments may be modified in various different ways, all without departing from the spirit or scope of the present invention.

In the drawings, the thickness of layers, films, panels, regions, etc., are exaggerated for clarity. Like parts are designated by like reference numerals throughout the specification. When a portion of a layer, film, region, plate, etc. is said to be "on top" of another part, this includes not only when the other part is "right over" but also when there is another part in the middle. On the contrary, when a part is "just above" another part, there is no other part in the middle.

Next, the thin film transistor array panel according to the exemplary embodiment of the present invention will be described in detail with reference to FIGS. 1 to 3.

1 is a layout view of a thin film transistor array panel according to an exemplary embodiment of the present invention, and FIGS. 2 and 3 are cross-sectional views illustrating the thin film transistor array panel of FIG. 1 taken along lines II-II and III-III, respectively.

A plurality of gate lines 121 and a plurality of storage electrode lines 131 are formed on an insulating substrate 110 made of transparent glass or plastic.

The gate line 121 transmits a gate signal and mainly extends in a horizontal direction. Each gate line 121 includes a plurality of gate electrodes 124 protruding downward and an end portion 129 having a large area for connection with another layer or an external driving circuit. A gate driving circuit (not shown) for generating a gate signal is mounted on a flexible printed circuit film (not shown) attached to the substrate 110 or directly mounted on the substrate 110. , May be integrated into the substrate 110. When the gate driving circuit is integrated on the substrate 110, the gate line 121 may extend to be directly connected to the gate driving circuit.

The storage electrode line 131 receives a predetermined voltage, and includes a stem line extending substantially in parallel with the gate line 121 and a plurality of pairs of first and second storage electrodes 133a and 133b separated therefrom. Each of the storage electrode lines 131 is positioned between two adjacent gate lines 121, and the stem line is closer to the lower side of the two gate lines 121. Each of the sustain electrodes 133a and 133b has a fixed end connected to the stem line and a free end opposite thereto. The fixed end of the first sustain electrode 133a has a large area, and its free end is divided into two parts, a straight portion and a bent portion. However, the shape and arrangement of the storage electrode line 131 may be modified in various ways.

The gate line 121 and the storage electrode line 131 may be formed of aluminum-based metal such as aluminum alloy, silver-based metal such as silver (Ag) or silver alloy, copper-based metal such as copper (Cu) or copper alloy, molybdenum (Mo) or molybdenum alloy. Molybdenum-based metals, such as chromium (Cr), tantalum (Ta), and titanium (Ti). However, they may have a multilayer structure including two conductive films (not shown) having different physical properties. One of the conductive films is made of a metal having low resistivity, such as aluminum-based metal, silver-based metal, or copper-based metal, so as to reduce signal delay or voltage drop. In contrast, other conductive films are made of other materials, particularly materials having excellent physical, chemical, and electrical contact properties with indium tin oxide (ITO) and indium zinc oxide (IZO), such as molybdenum-based metals, chromium, tantalum, and titanium. Good examples of such a combination include a chromium bottom film, an aluminum (alloy) top film, and an aluminum (alloy) bottom film and a molybdenum (alloy) top film. However, the gate line 121 and the storage electrode line 131 may be made of various other metals or conductors.

Side surfaces of the gate line 121 and the storage electrode line 131 are inclined with respect to the surface of the substrate 110, and the inclination angle is preferably about 30 ° to about 80 °.

A gate insulating layer 140 made of silicon nitride (SiNx) or silicon oxide (SiOx) is formed on the gate line 121 and the storage electrode line 131.

A plurality of linear semiconductors 151 made of hydrogenated amorphous silicon (hereinafter referred to as a-Si) or polysilicon are formed on the gate insulating layer 140. The linear semiconductor 151 mainly extends in the longitudinal direction and includes a plurality of projections 154 extending toward the gate electrode 124. The linear semiconductor 151 has a wider width in the vicinity of the gate line 121 and the storage electrode line 131 and covers them widely.

A plurality of linear and island ohmic contacts 161 and 165 are formed on the semiconductor 151. The ohmic contacts 161 and 165 may be made of a material such as phosphorous or silicide. The linear ohmic contact 161 has a plurality of protrusions 163, and the protrusion 163 and the island-type ohmic contact 165 are paired and disposed on the protrusion 154 of the semiconductor 151.

Side surfaces of the semiconductor 151 and the ohmic contacts 161 and 165 are also inclined with respect to the surface of the substrate 110, and the inclination angle is about 30 ° to 80 °.

A plurality of data lines 171 and a plurality of drain electrodes 175 are formed on the ohmic contacts 161 and 165.

The data line 171 transmits a data signal and mainly extends in the vertical direction to cross the gate line 121. Each data line 171 also crosses the storage electrode line 131 and runs between adjacent sets of storage electrodes 133a and 133b. Each data line 171 includes a plurality of source electrodes 173 extending toward the gate electrode 124 and an end portion 179 having a large area for connection with another layer or an external driving circuit. A data driving circuit (not shown) for generating a data signal is mounted on a flexible printed circuit film (not shown) attached to the substrate 110, directly mounted on the substrate 110, or integrated in the substrate 110. Can be. When the data driving circuit is integrated on the substrate 110, the data line 171 may be extended to be directly connected to the data driving circuit.

The drain electrode 175 is separated from the data line 171 and faces the source electrode 173 with respect to the gate electrode 124. Each drain electrode 175 has one end portion having a large area and the other end portion having a rod shape. The wide end portion overlaps the storage electrode line 131, and the rod-shaped end portion is partially surrounded by the bent source electrode 173.

One gate electrode 124, one source electrode 173, and one drain electrode 175 together with the protrusion 154 of the semiconductor 151 form one thin film transistor (TFT). A channel of the transistor is formed in the protrusion 154 between the source electrode 173 and the drain electrode 175.

The data line 171 and the drain electrode 175 are preferably made of a refractory metal such as molybdenum, chromium, tantalum, and titanium, or an alloy thereof, and include a refractory metal film (not shown) and a low resistance conductive film. It may have a multilayer structure including (not shown). Examples of the multilayer structure include a double layer of chromium or molybdenum (alloy) lower layer and an aluminum (alloy) upper layer, and a triple layer of molybdenum (alloy) lower layer and aluminum (alloy) interlayer and molybdenum (alloy) upper layer. However, the data line 171 and the drain electrode 175 may be made of various metals or conductors.

The side of the data line 171 and the drain electrode 175 may also be inclined at an inclination angle of about 30 ° to about 80 ° with respect to the surface of the substrate 110.

The ohmic contacts 161 and 165 exist only between the semiconductor 151 below and the data line 171 and the drain electrode 175 thereon, and lower the contact resistance therebetween.

The semiconductor 151 has a planar shape substantially the same as the data line 171, the drain electrode 175, and the ohmic contacts 161 and 165 thereunder. However, the semiconductors 151 and 154 are exposed between the source electrode 173 and the drain electrode 175.

A passivation layer 180 is formed on the data line 171, the drain electrode 175, and the exposed semiconductor 154.

The passivation layer 180 may be made of an inorganic insulator or an organic insulator, and may have a flat surface. Examples of the inorganic insulator include silicon nitride and silicon oxide. The organic insulator may have photosensitivity and the dielectric constant is preferably about 4.0 or less. However, the passivation layer 180 may have a double layer structure of the lower inorganic layer and the upper organic layer so as not to damage the exposed portion of the semiconductor 151 while maintaining excellent insulating properties of the organic layer.

In the passivation layer 180, a plurality of contact holes 182 and 185 exposing the end portion 179 and the drain electrode 175 of the data line 171 are formed, respectively, and the passivation layer 180 and the gate insulating layer are formed. In the 140, a plurality of contact holes 181 exposing the end portion 129 of the gate line 121 and a plurality of contact holes 183a exposing a part of the storage electrode line 131 near the fixed end of the first storage electrode 133a. ) And a plurality of contact holes 183b exposing the free end protrusion of the first sustain electrode 133a.

A plurality of pixel electrodes 191, a plurality of overpasses 83, and a plurality of contact assistants 81 and 82 are formed on the passivation layer 180. These may be made of a transparent conductive material such as ITO or IZO or a reflective metal such as aluminum, silver or an alloy thereof.

The pixel electrode 191 is physically and electrically connected to the drain electrode 175 through the contact hole 185 and receives a data voltage from the drain electrode 175. The pixel electrode 191 to which the data voltage is applied may generate an electric field together with a common electrode (not shown) of another display panel (not shown) to which a common voltage is applied. The direction of the liquid crystal molecules of the liquid crystal layer (not shown) is determined. The pixel electrode 191 and the common electrode form a capacitor (hereinafter referred to as a "liquid crystal capacitor") to maintain an applied voltage even after the thin film transistor is turned off.

The pixel electrode 191 overlaps the storage electrode line 131 including the storage electrodes 133a and 133b. A capacitor formed by the pixel electrode 191 and the drain electrode 171 electrically connected to the pixel electrode 191 overlapping the storage electrode line 131 is called a storage capacitor, and the storage capacitor enhances the voltage holding capability of the liquid crystal capacitor.

The contact auxiliary members 81 and 82 are connected to the end portion 129 of the gate line 121 and the end portion 179 of the data line 171 through the contact holes 181 and 182, respectively. The contact auxiliary members 81 and 82 compensate for and protect the adhesion between the end portion 129 of the gate line 121 and the end portion 179 of the data line 171 and the external device.

The connecting leg 83 crosses the gate line 121, and exposes the exposed portion of the storage electrode line 131 through a pair of contact holes 183a and 183b positioned opposite to each other with the gate line 121 interposed therebetween. The sustain electrode 133b is connected to the exposed end of the free end. The storage electrode lines 131 including the storage electrodes 133a and 133b may be used together with the connecting legs 83 to repair defects in the gate line 121, the data line 171, or the thin film transistor.

Next, a method of manufacturing the thin film transistor array panel shown in FIGS. 1 to 3 will be described in detail with reference to FIGS. 4 to 29.

4, 7, 24, and 27 are layout views sequentially illustrating a method of manufacturing a thin film transistor array panel according to an exemplary embodiment of the present invention, and FIGS. 5 and 6 illustrate the thin film transistor array panel of FIG. 8 and 9 are cross-sectional views of the thin film transistor array panel of FIG. 7 taken along lines VIII-VIII and IX-IX, and FIGS. 10 to 23 are cross-sectional views of FIG. 25 and 26 are cross-sectional views sequentially illustrating the thin film transistor array panel of FIG. 24 along the lines XXV-XXV and XXVI-XXVI, and FIGS. 28 and 29 are shown in FIG. 27 is a cross-sectional view of the thin film transistor array panel cut along the lines XXVIII-XXVIII and XXIX-XXIX.

First, as shown in FIGS. 4 to 6, the metal layer is laminated on the insulating substrate 110 made of transparent glass or plastic by sputtering or the like, and then photo-etched to form the gate electrode 124 and the end portion 129. A plurality of storage electrode lines 131 including a plurality of gate lines 121 and storage electrodes 133a and 133b are formed.

Next, as shown in FIGS. 7 to 9, the gate insulator 140 is stacked, and the linear intrinsic semiconductor 151 including the protrusion 154, the plurality of linear impurity semiconductors 161, and the source electrode ( A plurality of data lines 171 and a plurality of drain electrodes 175 including 173 and end portions 179 are formed.

Next, a method of manufacturing the thin film transistor array panel illustrated in FIGS. 7 to 9 will be described in detail with reference to FIGS. 10 to 23.

Referring to FIGS. 10 and 11, an intrinsic amorphous silicon layer 150 and an impurity amorphous silicon layer 160 are stacked on the gate insulating layer 140 by chemical vapor deposition, and the data metal layer 170 is sputtered thereon. Laminate in succession.

Next, as shown in FIGS. 12 and 13, the etching mask patterns 400a, 400b, and 400c are disposed at positions corresponding to the patterns of the desired semiconductor layer and the data metal layer.

In this case, the etching mask patterns 400a, 400b, and 400c include a linear intrinsic semiconductor 151 including a protrusion 154, a plurality of linear impurity semiconductors 161, a source electrode 173, and an end portion 179. The plurality of data lines 171 and the plurality of drain electrodes 175 are disposed at positions.

The etch mask pattern 400a is disposed in the region where the thin film transistor is to be formed. The height of the portion where the channel region of the thin film transistor is to be formed on the gate electrode 124 is about 1/2 lower than that of the periphery, and the etch mask pattern 400a is formed. The boundary of the upper part protrudes.

The etching mask patterns 400b and 400c are disposed in regions where the linear data line 171 and the end portion 179 of the data line 171 are to be formed, respectively. It has a form of protruding about 2

The metal layer 170 is etched using the mask patterns 400a, 400b, and 400c as an etch mask, and as shown in FIGS. 14 and 15, the data line 171 having the end portion 179 and the data of the thin film transistor. Form layer 174.

Next, the intrinsic amorphous silicon layer 150 and the impurity amorphous silicon layer 160 are etched using the mask patterns 400a, 400b, and 400c as etch masks, so that the end portions (as shown in FIGS. 16 and 17). The intrinsic amorphous silicon layer 150 and the impurity amorphous silicon layer 160 are removed from the data line 171 including the 179 and the lower portion of the data layer 174 of the thin film transistor.

As described above, the intrinsic amorphous silicon layer 150 is formed using the same etching masks 400a, 400b, and 400c as the process of forming the data line 171 including the end portion 179 and the data layer 174 of the thin film transistor. Since the impurity amorphous silicon layer 160 is etched, the semiconductors 151 and 154 have substantially the same planar shape as the data line 171, the drain electrode 175, and the ohmic contacts 161 and 164 thereunder.

Next, as shown in FIGS. 18 and 19, the etching masks 400a, 400b, and 400c are ashed to reduce the height of the etching mask 400a to 1/2 and at the same time, the etching masks 400b, 400c) is removed.

Next, by using the remaining etching mask 400a as shown in FIGS. 20 and 21, the data metal layer 174 and the impurity amorphous silicon layer 164 remaining in the channel portion of the thin film transistor are etched and removed to form a protrusion ( A plurality of linear resistive contact members 161 and a plurality of island resistive contact members 165 including 163 are completed, while portions of the intrinsic semiconductor 154 thereunder are exposed and shown in FIGS. 22 and 23. As illustrated, the remaining etching mask 400a is removed to include the linear intrinsic semiconductor 151 including the protrusion 154, the plurality of linear impurity semiconductors 161, the source electrode 173, and the end portion 179. A plurality of data lines 171 and a plurality of drain electrodes 175 are completed.

At this time, since the upper portion of the boundary of the etching mask 400a used in the manufacturing method according to the embodiment of the present invention protrudes, the data metal layer 174 and the impurity amorphous silicon layer 164 are etched in this etching step. In addition, the intrinsic amorphous silicon layer patterns 151 and 154 protrude more than the intrinsic amorphous silicon layer patterns 151 and 154 having the boundary between the data patterns 171 and 174 and the impurity amorphous silicon layer patterns 161 and 164. It can also be prevented. Therefore, the semiconductor 151 may not protrude further than the data line 171, the drain electrode 175, and the ohmic contacts 161 and 165 below, and may have substantially the same planar shape.

Next, as shown in FIGS. 24 to 26, the protective film 180 is stacked and patterned to form the protective member 178 and the data line 171 covering the end portion 129 of the gate line 121. A plurality of contact holes exposing an end portion 179, a portion of the storage electrode line 131 near the fixed end of the first storage electrode 133a, a portion of the free end protrusion of the first storage electrode 133a, and a drain electrode 175, respectively. (181, 182, 183a, 183b, and 185) are formed. In this case, after the protective film 180 is laminated, the photosensitive film is coated and then formed through a photolithography process.

27 to 29, a plurality of pixel electrodes 191, a plurality of contact auxiliary members 81 and 82, and a plurality of connection legs 83 are formed on the passivation layer 180. The pixel electrode 191, the plurality of contact auxiliary members 81, 82, and the plurality of connection legs 83 also form ITO or IZO, etc. to form a transparent conductive film, apply a photosensitive film on the transparent conductive film, and photo-etch it. Form.

As described above, in the method of manufacturing the thin film transistor array panel according to the exemplary embodiment of the present invention, the intrinsic amorphous silicon layer 150, the impurity amorphous silicon layer 160, and the data metal layer 170 are sequentially stacked, and the etch mask patterns 400a, By etching and patterning at the same time using 400b, 400c), the process is simpler than the process of forming and etching the etch mask using the exposure and development process using the light blocking mask, and the manufacturing cost can be reduced.

Next, a method of forming the etching mask patterns 400a, 400b, and 400c used in the method of manufacturing the thin film transistor array panel according to the exemplary embodiment of the present invention will be described in detail with reference to FIGS. 30 to 48.

30 is a schematic view of an apparatus for manufacturing an etch mask pattern according to an embodiment of the present invention, and FIGS. 31 to 42 are cross-sectional views sequentially shown according to a method of forming a gravure-printing photosensitive layer according to an embodiment of the present invention. 43 to 48 are cross-sectional views sequentially showing the method of forming a gravure print photosensitive layer according to another exemplary embodiment of the present invention.

First, an etching mask pattern manufacturing apparatus illustrated in FIG. 30 may be used to manufacture a liquid crystal display according to an exemplary embodiment of the present invention. In the etching mask pattern manufacturing apparatus according to the embodiment of the present invention, the etching mask pattern supply substrate 9, the transfer roller 14, the material supply device 15 of the etching mask, doctor blade (doctor blade) (1, 2) It includes.

The etching mask pattern supplying substrate 9 and the supporting plate 12 are installed in the lower frame 10, and the transfer roller 14 and the material supply device 15 of the etching mask are installed in the upper frame 13.

In particular, the etching mask supplying substrate 9 is provided on the printing plate 4, and the spacer supplying substrate 9 is provided with a plurality of grooves 19 into which the material of the etching mask is injected. The substrate for supplying the spacer 9 may be formed of glass, plastic or a metal material, and the groove 19 may be formed by a mold method or a laser processing method.

The grooves 19 have the same spacing and size as the etch mask pattern to be formed on the substrate. The substrate 110 on which the etch mask pattern is to be attached is mounted on the support plate 12.

On the surface of the transfer roller 14, a transfer sheet 3 made of hydrophilic silicone or the like is attached.

The doctor blades 1 and 2 are installed at the rear of the material supply device 15 of the etch mask, and the material of the etching mask dropped on the substrate 9 for supply of the etching mask in the material supply device 15 of the etching mask. It is evenly inserted into the grooves 19 formed in the substrate 9 for supplying the etching mask.

Next, a method of forming an etching mask pattern 400a using the etching mask pattern manufacturing apparatus shown in FIG. 30 according to an embodiment of the present invention will be described.

The etching mask pattern supply substrate 9a according to the exemplary embodiment of the present invention is formed at the same position as a portion where the etching mask pattern 400a is to be attached on the thin film transistor array panel 100 according to the exemplary embodiment of the present invention. It has a plurality of grooves 19a.

Referring to FIG. 31, the etching mask material 400a is dropped onto the etching mask pattern supply substrate 9a on which the plurality of grooves 19a are formed using the material supply device 15 of the etching mask.

Next, as shown in FIG. 32, the etching mask material 400a is pushed into the plurality of grooves 19a formed in the etching mask pattern supply substrate 9a using the doctor blades 1 and 2. Next, the remaining material 400a of the etching mask is removed to form the first etching mask pattern 400p filling the plurality of grooves 19a as shown in FIG. 33.

As shown in FIG. 34, the first etching is formed in the groove 19a of the etching mask pattern supply substrate 9a while rotating the transfer roller 14 in one direction on the etching mask pattern supply substrate 9a. The mask pattern 400p is transferred to the transfer sheet 3 of the transfer roller 14. In this way, the first etching mask pattern 400p is attached onto the transfer sheet 3 of the transfer roller 14 at the same interval as the predetermined interval between the grooves 19a.

Next, on the substrate 110 on which the plurality of thin films are formed, as shown in FIG. 35, the transfer roller 14 having the first etching mask pattern 400p attached to the surface is rotated in the opposite direction, and as shown in FIG. As illustrated, the first etch mask pattern 400p attached to the transfer roller 14 surface is retransmitted on the substrate 110.

As in the manufacturing method of the first etching mask pattern 400p, as shown in FIG. 37, the etching mask pattern supply substrate 9b in which a plurality of grooves 19b having the same shape as the second etching mask pattern 400q is formed is formed. ) Fill the mask pattern material.

Thereafter, as shown in FIG. 38, the second etching is formed in the groove 19b of the etching mask pattern supply substrate 9b while rotating the transfer roller 14 in one direction on the etching mask pattern supply substrate 9b. The mask pattern 400q is transferred to the transfer sheet 3 of the transfer roller 14, and the transfer roller 14 is rotated in the opposite direction on the substrate 110 to which the first etch mask pattern 400p is attached. As shown in FIG. 39, the second etching mask pattern 400q is retransmitted on the substrate 110.

In addition, as in the manufacturing methods of the first and second mask patterns 400p and 400q, an etching mask pattern in which a plurality of grooves 19c having the same shape as that of the third etching mask pattern 400r is formed, as shown in FIG. 40. The mask pattern material is filled in the supply substrate 9c, and the etching roller pattern supply substrate 9c is rotated in one direction on the etching mask pattern supply substrate 9c as shown in FIG. The third etching mask pattern 400r in the groove 19c of the substrate is transferred to the transfer sheet 3 of the transfer roller 14, and the substrate having the first and second etching mask patterns 400p and 400q attached thereto. By rotating the transfer roller 14 in the opposite direction on the 110, the third etch mask pattern 400r is retransmitted onto the substrate 110 as shown in FIG. 42, and thus the etch mask pattern according to the embodiment of the present invention ( 400a is formed and attached on the substrate 110.

Next, a method of forming the etching mask pattern 400a using the etching mask pattern manufacturing apparatus shown in FIG. 30 according to another embodiment of the present invention will be described.

Referring to FIG. 43, the etch mask pattern 401p filled in the grooves 20b having the same shape as the first etch mask pattern 401p is transferred from the etch mask pattern supply substrate 9d to the transfer sheet of the transfer roller 15. 44, the transfer roller 15 is rotated in the opposite direction on the substrate 110 as shown in FIG. 44, and the first etch mask pattern 401p is retransmitted onto the substrate 110 as shown in FIG. 45. do.

Thereafter, as shown in FIG. 46, the transfer roller 15 is oriented in one direction on the etching mask pattern supply substrate 9e on which the second and third etching mask patterns 401q and 401r are formed, as shown in FIG. 47. The second and third etch mask patterns 401q and 401r to be transferred to the transfer sheet of the transfer roller 15, and then transfer roller 15 on the substrate 110 to which the first etch mask pattern 401p is attached. The second and third etch mask patterns 401q and 401r are retransmitted onto the substrate 110 as shown in FIG. 48 by rotating N) in the opposite direction to form an etch mask pattern 400a according to an embodiment of the present invention. To be attached on the substrate 110.

The etching mask patterns 400b and 400c may be formed using the etching mask pattern manufacturing apparatus illustrated in FIG. 30 in a similar manner to the etching mask pattern 400a.

In this case, a plurality of grooves having the same shape as that of the etching mask patterns 400b and 400c are formed in the substrate for supplying the etching mask pattern at the same interval as that of the etching mask patterns 400b and 400c on the substrate 110.

As such, in the method of manufacturing the thin film transistor array panel according to the exemplary embodiment of the present invention, an etching mask pattern 400a for use in patterning the intrinsic amorphous silicon layer 150, the impurity amorphous silicon layer 160, and the data metal layer 170 is provided. By manufacturing the 400b and 400c using the gravure printing method, the manufacturing process is simple as compared with forming the etch mask using the exposure and development process using the light shielding mask, thereby reducing the manufacturing cost.

Next, a thin film transistor array panel according to another exemplary embodiment of the present invention will be described with reference to FIGS. 49 to 51.

49 is a layout view of a thin film transistor array panel according to another exemplary embodiment, and FIGS. 50 and 51 are cross-sectional views illustrating the thin film transistor array panel of FIG. 49 taken along lines XXXXX-XXXXX and XXXXXI-XXXXXI.

The layer structure of the thin film transistor array panel 100 according to the present embodiment is generally the same as that shown in FIGS. 1 to 3.

A plurality of gate lines 121 and a plurality of storage electrode lines 131 are formed on the substrate 110. The gate line 121 includes a plurality of gate electrodes 124 and end portions 129, and the storage electrode line 131 includes a plurality of storage electrodes 133a and 133b. On the gate line 121 and the storage electrode line 131, the gate insulating layer 140, the plurality of linear semiconductors 151 including the protrusions 154, the plurality of linear ohmic contacts 161 including the protrusions 163, and A plurality of island type ohmic contact members 165 are formed in sequence.

A plurality of data lines 171 including a source electrode 173 and an end portion 179, and a plurality of drain electrodes 175 are formed on the ohmic contacts 161 and 165, and a passivation layer 180 is formed thereon. Formed.

However, unlike the liquid crystal display shown in FIGS. 1 to 3, not only the plurality of contact holes 181 and 182 are formed in the passivation layer 180 and the gate insulating layer 140, but the passivation layer 180 has an opening ( 189, a pixel electrode 191 is formed in a region in the opening 189, and the plurality of contact auxiliary members 81 and 82 are made of the same material as the pixel electrode 191 in the contact holes 181 and 182. ) Is formed.

Next, a method of manufacturing the thin film transistor array panel illustrated in FIGS. 49 to 51 will be described in detail with reference to FIGS. 52 to 59.

52 to 59 are cross-sectional views sequentially showing the method of manufacturing the thin film transistor array panel of FIG. 49.

49 to 51 may include a gate line 121, a plurality of sustain electrode lines 131, and a gate insulating layer 140 during the manufacturing steps of the thin film transistor array panel illustrated in FIGS. 1 to 3 described above. ), A plurality of linear semiconductors 151 including protrusions 154, a plurality of linear resistive contact members 161 and a plurality of island resistive contact members 165 including protrusions 163, and a source electrode 173. And forming the plurality of data lines 171 and the plurality of drain electrodes 175 including the end portion 179 may be the same. Therefore, only the subsequent manufacturing steps will be described.

First, as shown in FIGS. 52 and 53, the plurality of linear semiconductors 151 and the protrusions 163 including the gate line 121, the plurality of sustain electrode lines 131, the gate insulating layer 140, and the protrusion 154. A plurality of linear ohmic contacts 161 and a plurality of islands of ohmic contact 165, and a plurality of data lines 171 and a plurality of drain electrodes including a source electrode 173 and an end portion 179. The passivation layer 180 is stacked on the substrate 110 on which the plurality of thin films including the plurality of thin films 175 are formed, and the pixel layer 191 and the contact auxiliary members 81 and 82 are formed. The etching mask pattern 450 is disposed at the position. In this case, the etching mask 450 used may have a shape in which a half of the boundary of the etching mask 450 protrudes, similarly to the etching mask 400a used in the above-described embodiment.

54 and 55, the protective layer 180 is etched using the etching mask pattern 450 to form the pixel electrode 191 and the contact assistants 81 and 82. A plurality of contact holes 181 and 182 and openings 189 are formed in the grooves.

56 and 57, a material such as ITO forming the pixel electrode 191 and the contact auxiliary members 81 and 82 is deposited without removing the etching mask pattern 450. At this time, since the upper portion of the edge of the etch mask pattern 450 formed on the passivation layer 180 protrudes, the pixel electrode 191 and the contact auxiliary member are disposed in the inner side of the passivation layer 180 by the width of the protrusion. (81, 82) are formed.

Finally, as shown in FIGS. 58 and 59, the etch mask pattern 450 disposed on the passivation layer 180 pattern is removed.

Since the etching mask pattern 450 used in the present embodiment is also formed by a gravure printing method using the etching mask pattern manufacturing apparatus shown in FIG. 30, the etching mask pattern 450 is exposed and developed using a light blocking mask to manufacture the etching mask. In comparison, the manufacturing process is simple and the cost is reduced.

In addition, in the method of manufacturing the thin film transistor array panel according to the present embodiment, the passivation layer 180, the pixel electrode 191, and the contact auxiliary members 81 and 82 may be formed by photo etching using different light blocking masks, respectively. Etching is performed using one etching mask 450 and the material layers are stacked to easily form the passivation layer 180, the pixel electrode 191, and the contact auxiliary members 81 and 82, as well as the number of light blocking masks. The reduction can also reduce manufacturing costs.

Although preferred embodiments of the present invention have been described in detail above, the scope of the present invention is not limited thereto, and various modifications and improvements of those skilled in the art using the basic concepts of the present invention defined in the following claims are also provided. It belongs to the scope of the invention.

As described above, instead of exposing and developing the etching mask used in the manufacturing process of the thin film transistor array panel by using the light blocking mask, it is formed by the gravure printing method, thereby not only simplifying the manufacturing process but also the light blocking mask. The reduction in the number can also reduce the manufacturing cost.

Claims (13)

Forming a gate line on the substrate, Stacking a gate insulating film on the gate line; Stacking an intrinsic amorphous silicon layer on the gate insulating film, Stacking an impurity amorphous silicon layer on the amorphous silicon layer, Depositing a data layer on the impurity amorphous silicon layer, Attaching a first etch mask pattern on the data layer; Etching the data layer using the first etching mask pattern as an etching mask; Etching an intrinsic amorphous silicon layer and an impurity amorphous silicon layer using the first etching mask pattern as an etching mask; Ashing the first etching mask pattern to form a second etching mask pattern; Etching an amorphous silicon layer using the second etching mask pattern as an etching mask, and Removing the second etching mask pattern; The first etch mask pattern is formed by gravure printing. In claim 1, The first etch mask pattern includes an upper portion and a lower portion, and the upper portion is wider than the lower portion. In claim 1, Attaching the first etching mask pattern is Forming grooves on the substrate for supplying the first etching mask at regular shapes and at regular intervals Filling the groove with an etching mask pattern material to form a first etching mask pattern; Transferring the first etch mask pattern to a transfer roller surface; and And attaching a first etching mask pattern on the surface of the transfer roller onto a substrate on which the data layer is formed. In claim 1, The first etching mask pattern is Forming first grooves having the same shape as the first portion of the first etching mask pattern at regular intervals on the first etching mask supply substrate, Filling the first groove with an etching mask pattern material to form a first portion of the first etching mask pattern; Transferring the first portion of the first etching mask pattern to a transfer roller surface; Attaching a first portion of a first etch mask pattern on the surface of the transfer roller onto a substrate on which the data layer is formed; Forming second grooves having the same shape as the second portion of the first etching mask pattern at regular intervals on the first etching mask supply substrate; Filling the second groove with an etching mask pattern material to form a second portion of the first etching mask pattern; Transferring a second portion of the first etch mask pattern to a transfer roller surface, and And attaching a second portion of the first etch mask pattern on the surface of the transfer roller onto a substrate to which the first portion of the first etch mask pattern is attached. In claim 4, The first etching mask pattern is Forming third grooves having the same shape as the third portion of the first etching mask pattern at regular intervals on the first etching mask supply substrate; Filling the third groove with an etching mask pattern material to form a third portion of the first etching mask pattern; Transferring a third portion of the first etch mask pattern to a transfer roller surface, and And attaching a third portion of the first etch mask pattern on the surface of the transfer roller onto a substrate to which the first and second portions of the first etch mask pattern are attached. Way. In claim 1, Stacking a protective layer on the substrate; Attaching a third etching mask pattern on the passivation layer; Etching the passivation layer using the third etching mask pattern as an etching mask to form an opening in which the pixel electrode is to be formed; Depositing a pixel electrode layer on the substrate to which the third etching mask pattern is attached; and Removing the third etching mask pattern to form a pixel electrode pattern in the opening; The third etching mask pattern is formed by gravure printing thin film transistor array panel manufacturing method. In claim 6, The third etch mask pattern includes an upper portion and a lower portion, and the upper portion is wider than the lower portion. In claim 6, Attaching the third etching mask pattern is Forming grooves on the third etching mask supply substrate at a predetermined shape and at regular intervals; Filling the groove with an etching mask pattern material to form a third etching mask pattern; Transferring the third etch mask pattern to a transfer roller surface; and And attaching a third etching mask pattern on the surface of the transfer roller onto a substrate on which the passivation layer is formed. Forming a gate line on the substrate, Sequentially depositing a gate insulating film, a semiconductor layer, and a data layer on the substrate; Patterning the semiconductor layer and the data layer to form a thin film transistor including a drain electrode; Stacking a protective layer on the substrate; Attaching an etch mask pattern on the passivation layer; Etching the passivation layer using the etching mask pattern as an etching mask to form an opening in which the pixel electrode is to be formed; Depositing a pixel electrode layer on the substrate to which the etch mask pattern is attached; and Removing the etch mask pattern to form a pixel electrode pattern formed in the opening and connected to the drain electrode; The etching mask pattern is formed by gravure printing thin film transistor array panel manufacturing method. In claim 9, The etching mask pattern includes an upper portion and a lower portion, and the upper portion is wider than the lower portion. In claim 9, Attaching the etching mask pattern is Forming grooves on the etching mask supply substrate at a predetermined shape and at regular intervals; Filling an etching mask pattern material in the groove to form an etching mask pattern; Transferring the etch mask pattern to a transfer roller surface, and And attaching an etch mask pattern on the surface of the transfer roller to a substrate on which the passivation layer is formed. In claim 9, The etching mask pattern is Forming first grooves having the same shape as the first portion of the etching mask pattern on the substrate for etching mask supply at regular intervals, Filling the first groove with an etching mask pattern material to form a first portion of the etching mask pattern; Transferring the first portion of the etch mask pattern to a transfer roller surface, Attaching a first portion of an etch mask pattern on the surface of the transfer roller onto a substrate on which the protective layer is formed; Forming second grooves having the same shape as the second portion of the etching mask pattern at a predetermined interval on the etching mask supply substrate; Filling the second groove with an etching mask pattern material to form a second portion of the etching mask pattern; Transferring a second portion of the etch mask pattern to a transfer roller surface, and And attaching a second portion of the etch mask pattern on the surface of the transfer roller onto a substrate to which the first portion of the etch mask pattern is attached. In claim 12, The etching mask pattern is Forming third grooves having the same shape as the third portion of the etching mask pattern on the etching mask supply substrate at regular intervals; Filling the third groove with an etching mask pattern material to form a third portion of the etching mask pattern; Transferring the third portion of the etch mask pattern to a transfer roller surface, and And attaching a third portion of the etch mask pattern on the surface of the transfer roller onto a substrate to which the first and second portions of the etch mask pattern are attached.

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