KR20070076843A - Thin film transistor substrate and method of testing the same - Google Patents

Abstract

A thin film transistor board and an inspecting method thereof are provided to prevent deterioration of defective inspection due to delay of a storage line by forming plural storage inspecting pads connected to both ends of common storage lines. Plural pixel electrodes(12) are formed in each sub-pixel region in which plural gate lines(GL1 to GLm) are across plural data lines(DL1 to DLn). Plural thin film transistors(TFT) are connected to the gate lines, the data lines and the pixel electrode. Plural storage lines(SL1 to SLm) are overlapped over the pixel electrodes. A first common storage line(22A) is commonly connected to one end of the storage line, and a second common storage line(22b) is commonly connected to the other end of the storage line. Plural storage inspection pads(24A to 24D) are connected to both ends of the first and second common storage lines.

Description

Thin film transistor substrate and its inspection method {THIN FILM TRANSISTOR SUBSTRATE AND METHOD OF TESTING THE SAME}

1 is a plan view schematically showing a thin film transistor substrate according to an embodiment of the present invention.

2 is a plan view schematically illustrating a thin film transistor substrate according to another exemplary embodiment of the present disclosure.

<Description of Main Parts of Drawing>

10 thin film transistor substrate 12 pixel electrode

14A, 14B: Audegate short line 16A, 16B: Even gate short line

Aod Gate Inspection Pad: 18A, 18B, 18C, 19D

Even Gate Inspection Pad: 20A, 20B, 20C, 20D

22A, 22B, 42A, 42B: common storage line

Storage Test Pads: 24A, 24B, 24C, 24D, 46A, 46B

26A: odd data short line 26B: even data short line

28A, 29B: Aod data test pad 30A, 30B: Even data test pad

44A, 44B: Connection Line

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a liquid crystal display device, and more particularly, to a thin film transistor substrate and an inspection method thereof capable of improving defect detection power.

The liquid crystal display displays an image by using the electrical and optical characteristics of the liquid crystal. The liquid crystal display device includes a liquid crystal display panel (hereinafter referred to as a liquid crystal panel) for displaying an image through a pixel matrix using liquid crystal, a driving circuit for driving the liquid crystal panel, and a backlight unit for supplying light to the liquid crystal panel.

The liquid crystal panel is formed by bonding a color filter substrate and a thin film transistor substrate with liquid crystals interposed therebetween. The color filter substrate includes a color filter array formed in each sub pixel region divided by a black matrix, and a common electrode formed on the color filter array. The thin film transistor substrate includes a pixel electrode, a gate line, and a thin film transistor connected between the data line and the pixel electrode, which are formed in each sub pixel region divided by the intersection of the gate line and the data line, and a storage line forming a storage capacitor by overlapping the pixel electrode. The formed thin film transistor array is provided.

The color filter substrate and the thin film transistor substrate may be formed through separate manufacturing processes and then inspected for defect detection. The thin film transistor substrate detects short or open defects in signal lines through electrical and optical inspection methods. In the electrical test method, a test signal is applied to a test pad connected to a thin film transistor array and the input / output signals of the test pad are compared to detect a line defect. The optical inspection method drives an inspection liquid crystal panel included in the optical inspection apparatus with a specific voltage applied to each pixel electrode of the thin film transistor array through an inspection pad, and detects a defective pixel due to a difference in luminance seen through the inspection liquid crystal panel. do.

However, as the liquid crystal panel is enlarged, a test signal is delayed due to an increase in the length of the signal line formed in the thin film transistor array, thereby deteriorating a defect detection force in electrical and optical inspection.

Accordingly, the present invention is to provide a thin film transistor substrate and its inspection method which can be improved to solve the conventional problems and can improve the defect detection ability.

To this end, the thin film transistor substrate according to the present invention includes a plurality of pixel electrodes formed in each sub pixel region defined by the intersection of the plurality of gate lines and the plurality of data lines; A plurality of thin film transistors connected between the plurality of gate lines and the data lines and each of the pixel electrodes; A plurality of storage lines overlapping each of the plurality of pixel electrodes; A first common storage line commonly connected to one end of the plurality of storage lines; A second common storage line connected in common with other ends of the plurality of storage lines; A plurality of storage test pads are respectively connected to both ends of the first and second common storage lines.

And an odd gate short line commonly connected to odd gate lines among the plurality of gate lines, and an even gate short line commonly connected to even gate lines; A plurality of gate check pads respectively connected across the odd and even gate short lines; An odd data short line commonly connected to odd data lines among the plurality of data lines, and an even data short line commonly connected to even data lines; A plurality of data check pads are further provided respectively connected to the odd and even data short lines.

The apparatus may further include third and fourth common storage lines connected between upper and lower portions of the first and second common storage lines, respectively, and include a central portion of each of the third and fourth common storage lines. A plurality of connected storage test pads is further provided.

The inspection method of a thin film transistor substrate according to the present invention includes applying a gate inspection signal to a plurality of gate lines through a plurality of gate inspection pads connected to both ends of the odd and even gate short lines; Applying a data check signal to the plurality of data lines through a plurality of data check pads connected across the odd and even data short lines; And applying a storage test signal to the plurality of storage lines through a plurality of storage test pads connected across the plurality of common storage lines.

Other features and advantages of the present invention in addition to the above technical problem will become apparent from the description of the preferred embodiment of the present invention with reference to the accompanying drawings.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to FIGS. 1 and 2.

1 is a plan view schematically illustrating a thin film transistor substrate according to an exemplary embodiment of the present invention.

In the array area AA of the thin film transistor substrate 10 illustrated in FIG. 1, gate lines GL1 to GLm and data lines DL1 to DLn are formed in an intersecting structure with an insulating layer therebetween. The pixel electrode 12 and the thin film transistor TFT are independently formed in each sub pixel area defined by the intersection structure of the gate lines GL1 to GLm and the data lines DL1 to DLn + 1. The thin film transistor TFT serves to switch the data signal from the data line DL to the pixel electrode 12 in response to the gate signal from the gate line GL. In the array area AA of the thin film transistor substrate 10, a plurality of storage lines SL1 to SLm parallel to the gate lines GL1 to GLm and one side of the plurality of storage lines SL1 to SLm are common. The connected first common storage line 22A and the second common storage line 22B connected to the other end of the plurality of storage lines SL1 to SLm are further formed. The plurality of storage lines SL1 to SLm overlap with each of the pixel electrodes 12 to form a storage capacitor.

In addition, a plurality of short lines and test pads for defect inspection are formed in an outer region surrounding the array region AA of the thin film transistor substrate 10. Specifically, an odd gate short line commonly connected to the odd gate lines GL1, GL3,..., GLm-1 of the plurality of gate lines GL1 to GLm in the left outer region of the thin film transistor substrate 10. An even gate short line 16A commonly connected to 14A and the even gate lines GL2, GL4, ..., GLm is formed. The odd gate test pads 18A and 18B are connected to both ends of the odd gate short line 14A, and the even gate test pads 20A and 20B are connected to both ends of the even gate short line 16A, respectively. Accordingly, the gate test signal input simultaneously through the odd gate test pads 18A and 18B in the test process of the thin film transistor substrate 10 is connected to the odd gate lines GL1, GL3,. The gate check signal supplied to the GLm-1 and simultaneously input through the even gate check pads 20A and 20B is supplied to the even gate lines GL2, GL4, ..., through the even gate short line 16A. GLm). Here, each of the odd and even gate short lines 14A and 16B may be formed in pairs for a smooth supply of test signals.

In the right outer region of the thin film transistor substrate 10, redundancy odd and even gate short lines 14B and 16B, which are symmetrical with the odd and even gate short lines 14A and 16A of the left outer region, may be further formed. In addition, redundancy odd gate test pads 18C and 18D are connected to both ends of the redundancy odd gate short line 14B, and redundancy even gate test pads 20C and redundancy are provided at both ends of the redundancy even gate short line 16B. 20C) are connected respectively. The redundancy odd and even gate short lines 14B and 16B are formed to be separated from the plurality of gate lines GL1 to GLm formed in the array region AA, and then the left and even gate short lines 14A and 16A on the left side. In case of failure, the gate signal GL1 to GLm are connected to supply a test signal.

The odd data short line 26A is commonly connected to the odd data lines DL1, DL3,..., DLn-1 of the plurality of data lines DL1 through DLn in the upper outer region of the thin film transistor substrate 10. And an even data short line 26B commonly connected to the even data lines DL2, DL4, ..., DLn. The odd data test pads 28A and 28B are connected to both ends of the odd data short line 26A, and the even data test pads 30A and 30B are connected to both ends of the even data line 26B, respectively. Accordingly, in the inspection process of the thin film transistor substrate 10, the data inspection signal simultaneously input through the odd data inspection pads 28A and 28B is transmitted through the odd data short line 26A. The data check signal supplied to the DLn-1 and simultaneously inputted through the even data check pads 30A and 30B is supplied to the even data lines DL2, DL4, ..., through the even data short line 26B. DLn).

In the outer region of the thin film transistor substrate 10, first and second storage test pads 24A and 24B connected to both ends of the first common storage line 22A, and both ends of the second common storage line 22B. And third and fourth storage test pads 24C and 24D are formed. Accordingly, the storage test signals simultaneously supplied to the first to fourth storage test pads 24A, 24B, 24C, and 24D distributed in the outer region during the inspection process of the thin film transistor substrate 10 are first and second common storage. Since the plurality of storage lines SL1 to SLm are supplied through the lines 22A and 22B, the delay of the storage check signal may be minimized.

After the thin film transistor substrate 10 is completed, the gate inspection pads 18A, 18B, 20A, and 20B and the data inspection pads 28A, 28B, 30A, and 30B may be used to inspect the line for defects using an optical inspection device. The array area AA is driven by a test signal supplied simultaneously through each of the storage test pads 24A, 24B, 24C, and 24D. Accordingly, the thin film transistor TFT of the array area AA is turned on at the same time so that a specific voltage is applied to each of the pixel electrodes 12 to drive the inspection liquid crystal panel included in the optical inspection apparatus, and through the inspection liquid crystal panel. A defective pixel can be detected by the luminance difference visually recognized. In this case, since the storage test signals are simultaneously supplied to the first and second common storage lines 22A and 22B of the array area AA through four storage test pads 24A, 24B, 24C, and 24D distributed in the outer area. It is possible to prevent the deterioration of the defect detection force due to line delay.

If the line defect is not detected in the inspection process, the thin film transistor substrate 10 of the present invention is bonded to the color filter substrate and cut along the scribing line SCL, thereby providing a plurality of short lines 14A, 14B, 16A, The outer area of the array area AA where the 16B, 26A, 26B and the test pads 18A to 18D, 20A to 20D, 24A to 24D, 28A, 28B, 30A, 30B are present is removed.

2 is a plan view illustrating a thin film transistor substrate according to another exemplary embodiment of the present disclosure.

The thin film transistor substrate 10 shown in FIG. 2 is disposed between the first and second common storage lines 22A and 22B at the upper side and the lower side of the array area AA as compared to the thin film transistor substrate 10 shown in FIG. 1. And third and fourth common storage lines 42A and 42B connected to the second and fourth common storage lines. In addition, a fifth storage test pad 46A formed in the center of the upper outer region and connected to the center of the third common storage line 42A through the first connection electrode 44A, and formed in the center of the lower outer region, And a sixth storage test pad 46B connected to the fourth common storage line 42B through the second connection electrode 44B. During the inspection process, the fifth and sixth storage test pads 46A and 46B may also receive the same storage test signal as the first to fourth storage test pads 24A to 24D, and thus the third and fourth common storage lines 42A and 42B. Supply through). Accordingly, even when the width of the array area AA is increased, the delay of the storage test signal is delayed through the third and fourth common storage lines 42A and 42B and the fifth and sixth storage test pads 46A and 46B. By minimizing, it is possible to prevent the deterioration of the defect detection caused by the line delay.

As described above, the thin film transistor substrate and the inspection method thereof according to the present invention include a plurality of common storage lines commonly connected to a plurality of storage lines, and a plurality of storage test pads connected to both ends of the plurality of common storage lines. As a result, it is possible to prevent the failure detection failure caused by the storage line delay.

Those skilled in the art will appreciate that various changes and modifications can be made without departing from the technical spirit of the present invention. Therefore, the technical scope of the present invention should not be limited to the contents described in the detailed description of the specification but should be defined by the claims.

Claims (5)

A plurality of pixel electrodes formed in each sub pixel region defined by the intersection of the plurality of gate lines and the plurality of data lines; A plurality of thin film transistors connected between the plurality of gate lines and the data lines and each of the pixel electrodes; A plurality of storage lines overlapping each of the plurality of pixel electrodes; A first common storage line commonly connected to one end of the plurality of storage lines; A second common storage line connected in common with other ends of the plurality of storage lines; And a plurality of storage test pads connected to both ends of the first and second common storage lines, respectively. The method of claim 1, An odd gate short line commonly connected to odd gate lines among the plurality of gate lines, and an even gate short line commonly connected to even gate lines; A plurality of gate check pads respectively connected across the odd and even gate short lines; An odd data short line commonly connected to odd data lines among the plurality of data lines, and an even data short line commonly connected to even data lines; And a plurality of data test pads respectively connected to both ends of the odd and even data short lines. The method of claim 2, And a third and a fourth common storage line connected between upper portions and lower portions of the first and second common storage lines, respectively. The method of claim 3, wherein And a plurality of storage test pads connected to a central portion of each of the third and fourth common storage lines. Applying a gate check signal to the plurality of gate lines through a plurality of gate check pads connected across the odd and even gate short lines; Applying a data check signal to the plurality of data lines through a plurality of data check pads connected across the odd and even data short lines; And applying a storage test signal to the plurality of storage lines through a plurality of storage test pads connected across the plurality of common storage lines.

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