KR20070071987A - Array substrate for liquid crystal display and method for manufacturing the same - Google Patents

Abstract

An array substrate for an LCD(Liquid Crystal Display) and a manufacturing method thereof are provided to remove a greenish blot and a spot by minimizing parasitic capacitance near to a common electrode, which causes distortion of a common voltage without any additional process. A gate electrode and a gate line(120) are formed on a transparent insulating substrate. A gate insulating layer is formed on an entire surface of the transparent insulating substrate to cover the gate electrode and the gate line. A metal layer includes a source electrode(142) and a drain electrode(143) formed on the gate insulating layer to face each other and form a thin film transistor(140) together with the gate electrode, a data line intersecting the gate line to define a pixel area, and a pixel electrode(150) formed on the pixel area and contacting the drain electrode. A passivation layer is formed on an entire surface of the transparent insulating substrate to cover the source and drain electrodes, the data line, and the pixel electrode. A common electrode(160) is formed of a transparent conductive metal on the passivation layer. An alignment layer is formed on an entire surface of the transparent insulating substrate to cover the common electrode.

Description

Array substrate for liquid crystal display device and its manufacturing method {Array substrate for liquid crystal display and method for manufacturing the same}

1 is a plan view illustrating an array substrate for a liquid crystal display device according to the prior art.

FIG. 2 is a cross-sectional view illustrating the surface of Ι-Ι ＇of FIG. 1. FIG.

3 is a plan view illustrating an array substrate for a liquid crystal display according to an exemplary embodiment of the present invention.

4 is a simplified cross-sectional view of the thin film transistor of FIG. 3.

5 is a cross-sectional view illustrating the II-II 'surface of FIG. 3.

6 is a plan view illustrating an array substrate for a liquid crystal display according to another exemplary embodiment of the present invention.

FIG. 7 is a simplified cross-sectional view of the thin film transistor of FIG. 6.

FIG. 8 is a cross-sectional view illustrating the III-III ′ surface of FIG. 6.

9 is a flowchart illustrating a method of manufacturing an array substrate for a liquid crystal display according to an exemplary embodiment of the present invention.

(Explanation of symbols for the main parts of the drawing)

100: transparent insulating substrate 110: gate insulating film

111: protective film 112: alignment film

120: gate line 130: data line

140: thin film transistor 141: gate electrode

142: source electrode 143: drain electrode

150: pixel electrode 160: common electrode

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an array substrate for a liquid crystal display device and a method for manufacturing the same, and more particularly, to an array substrate for use in a liquid crystal display device in an in-plane switching (IPS) mode and a method for manufacturing the same.

The liquid crystal display injects a liquid crystal material having anisotropic dielectric constant between the color filter substrate and the array substrate, which are upper and lower transparent insulating substrates, and adjusts the intensity of the electric field formed in the liquid crystal material to change the molecular arrangement of the liquid crystal material. The display device expresses a desired image by adjusting the amount of light transmitted through the transparent insulating substrate. As the liquid crystal display, a thin film transistor liquid crystal display (TFT LCD) using a thin film transistor (TFT) as a switching element is mainly used.

FIG. 1 is a plan view showing an array substrate for a liquid crystal display device according to the prior art, and FIG. 2 is a cross-sectional view showing the Ι-Ι ＇surface of FIG. 1, showing an example of an array substrate used in a liquid crystal display device in an IPS mode. .

As shown in FIG. 1, an array substrate for a liquid crystal display device includes a gate line 20 forming a row and a data line intersecting the gate lines 20 while forming a column having a bent structure. 30 are arranged in a matrix type, and pixel regions P divided by gate lines 20 and data lines 30 intersecting with each other form a frame (screen). When the scan pulse is sequentially applied to the gate lines 20, a data voltage is applied to the data lines 30 in response to the scan pulse, and one frame is displayed on the liquid crystal display.

In each pixel area P, the thin film transistor 40 is disposed at the intersection of the gate line 20 and the data line 30 to operate as a switching element, and the thin film transistor 40 is formed through the drain contact hole CH1. The pixel electrode 50 and the common electrodes 21 and 22 connected to the drain electrode 43 are formed.

The thin film transistor 40 includes a gate electrode formed as part of the gate line 20, and source and drain electrodes 42 and 43 facing each other while overlapping the gate electrode by a predetermined area. In FIG. 1, the drain electrode 43 is formed in an I shape, connected to the pixel electrode 50 through the drain contact hole CH1, and the source electrode 42 branching from the data line 30 is a drain electrode ( 43 is formed in a U-shape surrounding.

The common electrodes 21 and 22 may include two horizontal lines parallel to the gate electrode 20, and two vertical lines arranged in parallel with the data line 30 having a bent shape. ) Is formed on the outermost common electrode 21 and the common electrode 22 arranged to alternate with the pixel electrode 50 while branching in parallel with the data line 30 inside the pixel region P. do.

Referring to Figure 2, looking at the vertical cross-sectional structure of Figure 1 as follows.

As shown in FIG. 2, the common electrode 22 formed inside the pixel region P is formed on the same layer as the pixel electrode 50 and formed on the transparent insulating substrate 10 through the common contact hole CH2. The outermost common electrode 21 is contacted.

The outermost common electrode 21 is formed on the transparent insulating substrate 10 together with the gate line 20, and as shown in FIG. 2, the gate insulating layer 11 is stacked on the upper portion of the common insulating layer 21. A source electrode 42 and a drain electrode 43 facing the source electrode 42 are formed on the upper side along with the data line 30, and an inorganic insulating material such as silicon nitride film (SiNx) or the like is formed thereon. In the passivation film 12 made of an organic insulating material, the pixel electrode 50 and the common electrode 22 that cross each other are configured in the pixel region P on the passivation film 12.

An alignment layer 13 is formed on the array substrate on which the pixel electrode 50 and the common electrode 22 are formed to set the initial alignment of the liquid crystal material to be filled between the color filter substrate. The alignment layer 13 is subjected to rubbing so that the initial alignment of the liquid crystal material forms a predetermined pretilt angle with the substrate surface.

However, in the liquid crystal display of the IPS mode having such a structure, the gap d1 between the data line 30 and the common electrode 21 has to be designed to be quite close by the panel design margin in consideration of the aperture ratio. Therefore, the parasitic capacitance Cdc between the data line 30 to which the data voltage of AC is applied and the common electrode 21 to which the common voltage of DC is increased increases the degree of distortion of the common voltage. There is a problem that the image quality is deteriorated due to the greenisgh, smear, block dim and the like.

Therefore, the technical problem to be achieved by the present invention is to minimize the parasitic capacitance (Cdc) near the common electrode causing distortion of the common voltage without any additional process such as a mask process, thereby improving the image quality by removing the greenish or uneven color It is to provide an array substrate for a liquid crystal display device.

Another object of the present invention is to provide a method of manufacturing an array substrate for a liquid crystal display device which can efficiently manufacture such an array substrate for a liquid crystal display device.

Technical problems to be achieved by the present invention are not limited to the above-mentioned technical problems, and other technical problems not mentioned above will be clearly understood by those skilled in the art from the following description. Could be.

According to another aspect of the present invention, an array substrate for a liquid crystal display device includes a transparent insulating substrate, a gate electrode and a gate line formed on the transparent insulating substrate, the gate electrode and the A gate insulating film formed on the front surface of the transparent insulating substrate to cover the gate line, a source and drain electrode formed to face each other on the gate insulating film to form a thin film transistor together with the gate electrode, and intersecting the gate line; A transparent insulating substrate covering the source layer and the drain electrode, the data line and the pixel electrode, and a metal layer including a data line defining an area, a pixel electrode formed on the pixel area and in contact with the drain electrode. A protective film formed on the front surface of the transparent conductive film on the protective film It characterized by including the alignment film formed on the entire surface of the transparent insulating substrate so as to cover the common electrode and the common electrode formed of a metal.

In the array substrate for a liquid crystal display according to the exemplary embodiment of the present invention, the gate line and the data line have a linear shape and are perpendicular to each other, and a portion of the pixel electrode and the common electrode formed on the pixel area are Parallel to the data lines and staggered with each other.

In an array substrate for a liquid crystal display device according to another embodiment of the present invention, the data lines have a bent shape, and a portion of the pixel electrode and the common electrode formed on the pixel area are parallel with each other and cross each other. It is formed to be.

A method of manufacturing an array substrate for a liquid crystal display according to an exemplary embodiment of the present invention includes forming a gate electrode and a gate line on a transparent insulation substrate, and covering the gate electrode and the gate line to cover the front surface of the transparent insulation substrate. Forming a thin film transistor by forming a gate insulating film on the gate insulating film, and sequentially forming a semiconductor layer, an ohmic contact layer, and a metal layer on the gate insulating film, followed by etching. Forming a data line defining a pixel region crossing the gate line and a pixel electrode on the pixel region in contact with the drain electrode, and covering the source and drain electrodes, the data line, and the pixel electrode; Forming a protective film on an entire surface of the insulating substrate; And forming a common electrode by etching after depositing a transparent conductive metal, it characterized in that it comprises the step of covering the common electrode to form an alignment film on the entire surface of the transparent insulating substrate.

Specific details of other embodiments are included in the detailed description and the drawings. Advantages and features of the present invention and methods for achieving them will be apparent with reference to the embodiments described below in detail with the accompanying drawings. Like reference numerals refer to like elements throughout.

Hereinafter, an array substrate for a liquid crystal display according to a preferred embodiment of the present invention and a manufacturing method thereof will be described in detail with reference to the accompanying drawings.

3 is a plan view illustrating an array substrate for a liquid crystal display according to an exemplary embodiment of the present invention, FIG. 4 is a simplified cross-sectional view of the thin film transistor of FIG. 3, and FIG. 5 is a cross-sectional view illustrating a II-II 'surface of FIG. 3. to be.

The gate line 120 and the data line 130 have a straight line shape to define the pixel region P to be orthogonal to each other, and the thin film transistor 140 is disposed at the intersection of the gate line 120 and the data line 130. Is composed. In addition, the pixel electrode 150 and the common electrode 160 are formed on the pixel region P such that some lines formed in the vertical direction are alternate with each other.

As shown in FIG. 4, the thin film transistor 140 includes a gate electrode 141 formed of a metal material such as aluminum alloy (AlNd) on the transparent insulation substrate 100, and a gate insulating layer formed on the gate electrode 141. And a semiconductor layer 144, an ohmic contact layer 145 and 146, a source electrode 142, a drain electrode 143, and the like.

The gate electrode 141 is formed as a part of the gate line 120 shown in FIG. 3, or is branched from the gate line 120 to the pixel electrode 150.

The semiconductor layer 144 is formed of an undoped amorphous silicon material on the gate insulating layer 110, and a region corresponding to the gate electrode 141 is defined as the channel portion ACT.

3 and 4, the source electrode 142 branching to both sides of the drain electrode 143 in the data line 130 and the drain electrode 143 in contact with the pixel electrode 150 are connected to the channel portion ACT. ) Are positioned to face each other, and the gate electrode 141 and some regions overlap each other.

The ohmic contacts 145 and 146 are formed at the interface between the source electrode 142 and the drain electrode 143 and the semiconductor layer 144, and are made of an n + hydrogenated amorphous silicon material which is heavily doped with n-type impurities.

A passivation layer 111 is formed on the thin film transistor 140, and an alignment layer 112 is formed on the passivation layer 111 by using a material such as polyimide to define an initial orientation of the liquid crystal material.

3 to 5, a vertical cross-sectional structure of an array substrate for a liquid crystal display according to an exemplary embodiment of the present invention will be described in detail.

First, a gate insulating layer 110 covering the gate line 120 and the gate electrode 141 is formed on the front surface of the transparent insulating substrate 100, and is branched from the data line 130 and the data line 130 thereon. The source electrode 142, the pixel electrode 150, and the drain electrode 143 branching from the pixel electrode 150 are formed.

Here, the data line 130, the source electrode 142, the pixel electrode 150, and the drain electrode 143 are formed at the same time by depositing a metal layer on the gate insulating layer 110 and then etching the same. To form a metal layer, it is preferable to use a single film or multiple films of molybdenum (Mo) or molybdenum alloy as the metal layer. Molybdenum and molybdenum alloys do not generate fine bubbles during etching, and can be etched with a gentle slope, and have excellent contact characteristics with the ohmic contacts 145 and 146.

In the conventional IPS mode liquid crystal display, only the data line 30 and the source and drain electrodes 42 and 43 are formed on the gate insulating film 11 which is the same layer, and the pixel electrode 50 covers them. After forming on the passivation layer 12, the structure in which the pixel electrode 50 and the drain electrode 43 are in contact with each other through the drain contact hole CH1 has been generally used (see FIGS. 1 and 2).

In the conventional structure, the pixel electrode 50 passes through the drain contact hole CH1 to increase the load resistance. However, according to the present invention, the pixel electrode 150 is formed on the same layer as the data line 130. Since it is formed in the drain contact hole is unnecessary, this problem can be solved.

A passivation layer 111 is formed over the entire surface of the metal layer including the data line 130, the source electrode 142, the pixel electrode 150, and the drain electrode 143, and indium tin is formed on the passivation layer 111. A common electrode 160 made of a transparent conductive metal having excellent light transmittance, such as indium tinoxide (ITO) or indium zinc oxide (IZO), is formed.

Here, the thickness h1 of the passivation layer 111 shown in FIG. 5 is formed to be relatively high (2.5 μm to 3.5 μm), thereby increasing the distance between the pixel electrode 150 and the common electrode 160 to lower the parasitic capacitance Cdc. To lose.

In the conventional structure, the gate insulating film 11 is formed between the data line 30 and the outermost common electrode 21 (see FIG. 2), and may be formed of an insulating material such as silicon nitride film (SiNx) or silicon oxide film (SiOx). In the case of the gate insulating film formed, the thickness of the gate insulating film is relatively low at a level of 2000 Pa to 4000 Pa, which is a factor of increasing the parasitic capacitance Cdc.

However, in the present invention, the passivation layer 111 formed between the pixel electrode 150 and the common electrode 160 is made of a material that can be easily deposited up to a 3 μm level in view of a process such as photo acryl. In general, the parasitic capacitance Cdc can be reduced by securing the thickness h1 of the protective film 111 without changing the conventional process. The passivation layer 111 may perform the same function as a conventional passivation layer, and may be formed with another organic insulating material that may be deposited relatively thicker than a gate insulating layer made of an insulating material such as silicon nitride film (SiNx) or silicon oxide film (SiOx). It may be replaced by an inorganic insulating material.

The common electrode 160 includes a pixel region P in which a gate line 120 or a data line 130 is formed, in addition to a portion of the common electrode 160 that is formed to cross the pixel electrode 150 inside the pixel region P. FIG. By further configuring a portion extending to the outside of the, it is possible to easily apply the drive signal to the common electrode 160 without additional elements such as a separate input terminal while replacing the conventional outermost common electrode with the expanded portion.

3 illustrates a case where the common electrode 160 is extended to a region corresponding to the data line 130 among the outer portions of the pixel region P as an example for illustrating the expansion of the common electrode 160. .

As described above, when a part of the common electrode 160 is extended to an area on the side of the gate line 120 or the data line 130, when a gate driver or a source driver for applying a driving signal is attached later, It is possible to configure so as to receive a common voltage from the side of the two drivers which are easy to configure.

The structure of the array substrate for the liquid crystal display device described with reference to FIGS. 3 to 5 may be variously applied not only to the IPS structure of FIG. 3 but also to other IPS structures.

6 is a plan view illustrating an array substrate for a liquid crystal display according to another exemplary embodiment of the present invention, FIG. 7 is a simplified cross-sectional view of the thin film transistor of FIG. 6, and FIG. 8 is a cross-sectional view of the III-III ′ surface of FIG. 6. to be.

Another embodiment of the present invention is compared to the embodiment shown in Figures 3 to 5, by forming a portion of the common electrode 160 and the pixel electrode 150 that are staggered to each other in a bent form, the contrast ratio A wider viewing angle can be achieved while compensating for weaknesses in response and response speed.

As shown in FIG. 6, the array substrate for a liquid crystal display device includes a row of gate lines 120 and a data line crossing the gate lines 120 while forming a column having a bent structure. The 130 are arranged in a matrix type, and pixel regions P divided by gate lines 120 and data lines 130 intersecting with each other are gathered to display one frame.

Each pixel region P includes a thin film transistor 140 positioned at an intersection of the gate line 120 and the data line 130 to operate as a switching element, a common electrode 160, a pixel electrode 150, and the like. do.

The thin film transistor 140 includes a gate electrode formed as part of the gate line 130, and source and drain electrodes 142 and 143 facing each other while overlapping the gate electrode by a predetermined area, and the drain electrode 143 is It is formed in an I shape and connected to the pixel electrode 150, and the source electrode 142 is formed in a U shape surrounding the drain electrode 143 and connected to the data line 130.

The U-shaped thin film transistor 140 having such a configuration may have an effect of improving an overlay margin or reducing an area occupied by the source and drain electrodes 142 and 143 to improve the aperture ratio.

The common electrode 160 is composed of two horizontal lines, two vertical lines arranged in parallel with the data line 130 and having a curved shape to surround the pixel area P, and a horizontal line. In FIG. 2, a portion is branched into the pixel region P and disposed to cross the pixel electrode 150.

Unlike the conventional case in which the common electrode 22 on the passivation layer 12 is configured to contact the outermost common electrode 21 through the common contact hole CH2, the common electrode 160 of the present invention is used in all regions. Since it is formed on the same layer, the configuration of the common contact hole becomes unnecessary.

6 to 8, a vertical cross-sectional structure of an array substrate for a liquid crystal display according to another exemplary embodiment of the present invention will be described in detail as follows.

First, a gate insulating layer 110 covering a gate line 120 and a gate electrode 141 defined as a partial region of the gate line 120 is formed on an entire surface of the transparent insulating substrate 100, and a data line thereon. A source electrode 142 branching from the 130 and the data line 130, and a drain electrode 143 branching from the pixel electrode 150 and the pixel electrode 150 are formed.

Here, the data line 130, the source electrode 142, the pixel electrode 150, and the drain electrode 143 are formed at the same time by depositing a metal layer on the gate insulating layer 110 and then etching the same. Molybdenum, molybdenum alloy, etc. are preferably used as the metal layer.

As such, the data line 130, the pixel electrode 150, the source electrode 142, and the drain electrode 143 are formed on the same layer on the gate insulating layer 110, and the common electrode 160 is formed on the passivation layer 111. Since it is formed to be connected to each other, the drain contact hole or the common contact hole is no need to configure.

The common electrode 160 formed on the passivation layer 111 is made of a transparent conductive metal having relatively high light transmittance such as indium tin oxide (ITO) or indium zinc oxide (IZO).

Here, the thickness h1 of the passivation layer 111 is formed to be relatively high (2.5 μm to 3.5 μm) to increase the distance between the pixel electrode 150 and the common electrode 160 to lower the parasitic capacitance Cdc.

The upper surface of the array substrate on which the common electrode 160 is formed is provided with an alignment layer 112 for setting an initial orientation of the liquid crystal material to be filled between the color filter substrate and rubbing to have a constant pretilt angle. do.

As described above, according to the exemplary embodiments of the present invention, the pixel electrode 150 including the data line 130, the source electrode 142, and the drain electrode 143 is formed on the same plane, and is common. By adopting a structure in which the electrode 160 is formed on another plane with the passivation layer 111 interposed therebetween, the load resistance of the pixel electrode 150 or the common electrode 160 is reduced by eliminating the need for a drain contact hole or a common contact hole. In addition, the parasitic capacitance Cdc between the data line 130 and the common electrode 160 may be minimized to stabilize the common voltage.

9 is a flowchart illustrating a method of manufacturing an array substrate for a liquid crystal display according to an exemplary embodiment of the present invention.

A method of manufacturing an array substrate for a liquid crystal display according to an exemplary embodiment of the present invention includes a first mask process for forming the gate electrode 141 and the gate line 120, the source and drain electrodes 142 and 143, and the pixel electrode. Forming a second mask process for forming the 150 and the data line 130, and a third mask process for forming a hole for applying a signal to the source and drain electrodes 142 and 143, and forming the common electrode 160. The fourth mask process can be simplified.

First, in step S100, the gate electrode layer is deposited with a metal material on the transparent insulating substrate 100, a photoresist is applied on the gate electrode layer, and then the gate electrode layer is patterned by a photo process and an etching process using a first mask. As a result, the gate electrode 141 and the gate line 120 are formed. The metal material constituting the gate electrode layer is selected from a metal material having a low resistivity value such as aluminum alloy (AlNd).

Next, in step S110, the gate insulating layer 110 is formed on the entire surface of the transparent insulating substrate 100 to cover the gate electrode 141 and the gate line 120. The gate insulating layer 110 is selected from an organic insulating material or an inorganic insulating material such as silicon nitride film (SiNx) or silicon oxide film (SiOx).

Next, in step S120, the source and drain electrodes 142 and 143, the data line 130, and the pixel electrode 150 are formed at a time by a photo process and an etching process using a second mask. At this time, the semiconductor layer 144 made of an undoped amorphous silicon layer on the gate insulating layer 110, the ohmic contact layers 145 and 146 made of an n + hydrogenated amorphous silicon layer doped with high concentration of n-type impurities, and molybdenum The thin film transistor 140 may be formed by forming the source and drain electrodes 142 and 143 by sequentially stacking and etching a metal layer made of a metal material, such as a metal material. When the metal layer is etched, the data line 130 crossing the gate line 120 and defining the pixel region P and the pixel electrode 150 connected to the drain electrode 142 are formed together.

Next, in operation S130, the passivation layer 111 is formed on the entire surface of the transparent insulation substrate 100 to cover the source and drain electrodes 142 and 143, the data line 130, and the pixel electrode 150. Here, the protective film 111 is preferably formed to have a thickness of 2.5 ㎛ to 3.5 ㎛ made of a material such as photo acrylic.

In this case, since an electric driving signal must be applied to the source and drain electrodes 142 and 143 from an external driving circuit (a gate driver or a source driver), the source and drain electrodes 142 and 143 may be formed using a third mask. Holes are formed in the outer part.

Next, in step S140, after the transparent conductive metal is deposited on the protective layer 111, the common electrode 160 is formed by a photo process and an etching process using a fourth mask. The common electrode 160 may be configured to extend to the outside of the pixel region P in which the gate line 120 or the data line 130 is formed so that the common voltage can be easily applied.

In addition, the arrangement of the gate line 120, the data line 130, the pixel electrode 150, and the common electrode 160 may be modified in various forms within the range of the IPS mode according to the pixel structure to be implemented.

For example, the gate line 120 and the data line 130 have a straight line shape and are orthogonal to each other, and a portion of the pixel electrode 150 and the common electrode 160 formed on the pixel region P may be the data line 130. And parallel to and alternate with each other (see FIG. 3), or a portion of the pixel electrode 150 and the common electrode 160 disposed in parallel with the data line 130 may be formed in a bent shape (FIG. 6). Reference).

Next, in step S150, the alignment layer 112 is formed on the entire surface of the transparent insulating substrate 100 to cover the common electrode 160.

As such, the array substrate for the liquid crystal display device according to the exemplary embodiment and the other exemplary embodiment may be manufactured, and the load resistance of the pixel electrode 150 or the common electrode 160 may be adjusted within a range of minimizing a mask process. The image quality may be improved by stabilizing the common voltage by minimizing the parasitic capacitance Cdc between the common electrode 160 and the data line 130 by adding the passivation layer 111.

Although embodiments of the present invention have been described above with reference to the accompanying drawings, those skilled in the art to which the present invention pertains may implement the present invention in other specific forms without changing the technical spirit or essential features thereof. I can understand that.

Therefore, since the embodiments described above are provided to completely inform the scope of the invention to those skilled in the art, it should be understood that they are exemplary in all respects and not limited. The invention is only defined by the scope of the claims.

The array substrate for a liquid crystal display device according to the preferred embodiment of the present invention made as described above can minimize the parasitic capacitance (Cdc) near the common electrode causing distortion of the common voltage without any additional process such as a mask process. Image quality can be improved by removing spots and the like.

In addition, the method for manufacturing an array substrate for a liquid crystal display device according to a preferred embodiment of the present invention can efficiently manufacture such an array substrate for a liquid crystal display device.

Claims (12)

Transparent insulating substrates; A gate electrode and a gate line formed on the transparent insulating substrate; A gate insulating film formed on an entire surface of the transparent insulating substrate to cover the gate electrode and the gate line; A source and a drain electrode formed to face each other on the gate insulating layer to form a thin film transistor together with the gate electrode, a data line crossing the gate line to define a pixel region, and a drain electrode formed on the pixel region. A metal layer including a pixel electrode in contact with the second electrode; A passivation layer formed on an entire surface of the transparent insulating substrate to cover the source and drain electrodes, the data line, and the pixel electrode; A common electrode formed of a transparent conductive metal on the passivation layer; And And an alignment layer formed on the entire surface of the transparent insulating substrate so as to cover the common electrode. The method of claim 1, The metal layer, An array substrate for a liquid crystal display device comprising molybdenum (Mo). The method of claim 1, The protective film, It has a thickness of 2.5 micrometers-3.5 micrometers, The array substrate for liquid crystal display devices characterized by the above-mentioned. The method of claim 1, The common electrode, And an outer portion of the pixel area where the gate line and the data line are formed. The method of claim 1, The gate line and the data line have a straight line shape and are perpendicular to each other, and a portion of the pixel electrode and the common electrode formed on the pixel area are formed to be parallel to and cross the data line. Array substrate for display device. The method of claim 1, And the data line has a curved shape, and a portion of the pixel electrode and the common electrode formed on the pixel area are formed to be parallel to and intersect with the data line. Forming a gate electrode and a gate line on the transparent insulating substrate; Forming a gate insulating film on an entire surface of the transparent insulating substrate to cover the gate electrode and the gate line; The semiconductor layer, the ohmic contact layer, and the metal layer are sequentially stacked on the gate insulating layer and then etched to form source and drain electrodes to form a thin film transistor. The pixel region is defined by crossing the gate line from the metal layer. Forming a data line and a pixel electrode on the pixel region in contact with the drain electrode; Forming a passivation layer on an entire surface of the transparent insulating substrate to cover the source and drain electrodes, the data line, and the pixel electrode; Depositing a transparent conductive metal on the passivation layer and then etching to form a common electrode; And And forming an alignment layer on the entire surface of the transparent insulating substrate so as to cover the common electrode. The method of claim 7, wherein The metal layer, A method of manufacturing an array substrate for a liquid crystal display device, comprising molybdenum (Mo). The method of claim 7, wherein The protective film, It has a thickness of 2.5 micrometers-3.5 micrometers, The manufacturing method of the array substrate for liquid crystal display devices characterized by the above-mentioned. The method of claim 7, wherein The common electrode, And extending to the outer periphery of the pixel region where the gate line and the data line are formed. The method of claim 7, wherein The gate line and the data line have a linear shape and are perpendicular to each other, and a portion of the pixel electrode and the common electrode formed on the pixel area are formed to be parallel to and cross the data line. A manufacturing method of an array substrate for a display device. The method of claim 7, wherein The data line has a curved shape, and a portion of the pixel electrode and the common electrode formed on the pixel area are formed to be parallel to and alternate with the data line. .

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